CN108780784A - 带Ag基底层的金属部件、带Ag基底层的绝缘电路基板、半导体装置、带散热器的绝缘电路基板及带Ag基底层的金属部件的制造方法 - Google Patents

带Ag基底层的金属部件、带Ag基底层的绝缘电路基板、半导体装置、带散热器的绝缘电路基板及带Ag基底层的金属部件的制造方法 Download PDF

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CN108780784A
CN108780784A CN201780019604.2A CN201780019604A CN108780784A CN 108780784 A CN108780784 A CN 108780784A CN 201780019604 A CN201780019604 A CN 201780019604A CN 108780784 A CN108780784 A CN 108780784A
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layers
basal layers
layer
cream
basal
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CN108780784B (zh
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西元修司
长友义幸
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Mitsubishi Materials Corp
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Mitsubishi Materials Corp
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Abstract

本发明的带Ag基底层的金属部件具备：与被接合体(3)接合的金属部件(12)；和形成于该金属部件(12)的与被接合体(3)的接合面的Ag基底层(30)，Ag基底层(30)由形成于金属部件(12)侧的玻璃层(31)和层压形成于该玻璃层(31)的Ag层(32)构成，Ag基底层(30)的Ag层(32)侧表面的空隙的面积率为25％以下。

Description

带Ag基底层的金属部件、带Ag基底层的绝缘电路基板、半导体 装置、带散热器的绝缘电路基板及带Ag基底层的金属部件的 制造方法
技术领域
本发明涉及：具备与被接合体接合的金属部件和形成于该金属部件的表面的Ag基底层的带Ag基底层的金属部件；具有该带Ag基底层的金属部件的带Ag基底层的绝缘电路基板；具备该带Ag基底层的绝缘电路基板的半导体装置；带散热器的绝缘电路基板；及带Ag基底层的金属部件的制造方法。
本申请主张基于2016年2月1日于日本申请的专利申请2016-017304号的优先权，并将其内容援用于此。
背景技术
在LED或功率模块等半导体装置具有在由导电材料构成的电路层上接合有半导体元件的结构。
为了控制风力发电、电动汽车、混合动力汽车等而使用的大功率控制用的功率半导体元件由于发热量较多，因此，作为搭载该功率半导体元件的基板，一直以来广泛使用绝缘电路基板(功率模块用基板)，该绝缘电路基板具备：绝缘层，由例如具AlN(氮化铝)、Al2O3(氧化铝)等的陶瓷基板构成；及电路层，通过在该绝缘层的一个表面配设导电性优异的金属而形成。
例如，专利文献1所示的功率模块(半导体装置)具有如下结构：具备在陶瓷基板的一面上形成有由Al或Cu等金属构成的电路层的功率模块用基板(绝缘电路基板)；和接合在该电路层上的半导体元件。
另外，还提供了在陶瓷基板的另一面配设导热性优异的金属而形成的金属层的功率模块用基板。而且，在功率模块用基板的金属层接合有散热器，将由半导体元件发送的热传递到功率模块用基板侧，通过散热器向外部散发的结构。
将半导体元件等电子部件接合到电路层时或将散热器接合到金属层时，例如专利文献1所示，广泛使用利用焊锡材的方法。
最近，从环境保护的观点来看，作为接合半导体元件等电子部件与电路层、散热器与金属层时使用的焊锡材，例如Sn-Ag类、Sn-In类或Sn-Ag-Cu类等无铅焊料成为主流。
在此，由铝或铝合金构成的电路层及金属层中，表面形成有铝的自然氧化膜，因此难以通过焊锡材良好地接合半导体元件及散热器。
另外，由铜或铜合金构成的电路层及金属层中，熔化的焊锡材与铜进行反应而在电路层的内部侵入焊锡材的成分，有可能使电路层及金属层的特性劣化。
因此，以往如专利文献1所示，在电路层及金属层的表面形成Ni镀膜之后，通过焊锡材实施半导体元件。
另外，如专利文献1中所记载，使用焊锡材接合半导体元件及散热器的情况下，在高温环境下使用时，焊料的一部分熔化，有可能使半导体元件与绝缘电路基板及散热器与绝缘电路基板的接合可靠性下降。
另一方面，作为不使用焊锡材的接合方法，例如在专利文献2中提出有使用Ag纳米膏来接合半导体元件等电子部件或散热器的技术。
另外，在专利文献3、4中提出有使用含有金属氧化物粒子和由有机物构成的还原剂的氧化物膏来接合半导体元件等电子部件或散热器的技术。
然而，如专利文献2-4中所记载，不使用焊锡材而是使用金属膏或氧化物膏来接合半导体元件等电子部件的情况下，与焊锡材相比，由这些膏的烧成体构成的接合层的厚度形成得较薄，因此有热循环负载时的应力容易作用于半导体元件等电子部件而有可能导致半导体元件等电子部件本身破损。同样地，在金属层与散热器之间形成的接合层变薄时，因绝缘电路基板与散热器的热膨胀系数之差而产生的热应变作用于绝缘电路基板，有可能在绝缘层产生龟裂。
于是，例如专利文献5中提出有如下技术：使用含玻璃Ag膏在由铝或铜构成的电路层上形成Ag基底层之后，通过Ag膏来接合电路层和半导体元件。在该技术中，在由铝或铜构成的电路层的表面涂布含玻璃Ag膏并烧成，由此使形成于电路层的表面的氧化被膜与玻璃进行反应而被去除来形成Ag基底层，在形成有该Ag基底层的电路层上通过由Ag膏的烧成体构成的Ag接合层来接合半导体元件。在此，Ag基底层具备通过玻璃与电路层的氧化被膜进行反应来形成的玻璃层及形成于该玻璃层上的Ag层。该玻璃层中分散有导电性粒子，通过该导电性粒子可确保玻璃层的导电性。
根据该专利文献5所记载的技术，在这种情况下，通过Ag基底层和由Ag膏及氧化银膏的烧成体构成的接合层能够确保充分的厚度，因此能够抑制半导体元件的破损和绝缘层中的龟裂的产生。
专利文献1：日本特开2004-172378号公报
专利文献2：日本特开2006-202938号公报
专利文献3：日本特开2008-208442号公报
专利文献4：日本特开2009-267374号公报
专利文献5：日本特开2013-012706号公报
但是，最近期待着从硅半导体向SiC或GaN等化合物半导体元件的实用化，由于半导体元件本身的耐热性的提高被关注，因此半导体装置的使用温度有增高的倾向。
在此，如专利文献5所公开，使用含玻璃Ag膏在由铝或铜构成的电路层上形成Ag基底层之后，使用Ag膏及氧化银膏接合半导体元件及散热器的情况下，例如施加达到200℃以上的高温的冷热循环负载时，有可能在由Ag膏及氧化银膏的烧成体构成的接合层产生裂纹导致半导体元件及散热器剥离。
因此，要求即使在施加达到高温的冷热循环负载的情况下，也能够抑制接合层中的裂纹的产生的带Ag基底层的金属部件。
发明内容
本发明是鉴于前述的情况而完成的，其目的在于提供一种即使在较高温环境下使用的情况下，也能够抑制接合层内的裂纹的产生，被接合体与金属部件的接合可靠性优异的带Ag基底层的金属部件、包括该带Ag基底层的金属部件的带Ag基底层的绝缘电路基板、使用该带Ag基底层的绝缘电路基板的半导体装置和带散热器的绝缘电路基板、以及带Ag基底层的金属部件的制造方法。
为了解决上述课题并实现所述目的，本发明人等进行深入研究的结果，得出了以下见解：在Ag基底层上，形成由接合材的烧成体构成的接合层来接合被接合体、其中所述接合材包含Ag及氧化银中的一方或双方和有机物的情况下，例如施加达到200℃以上的高温的冷热负载时，以Ag基底层中的与接合层相接的表面中存在的空隙为起点在接合层内产生裂纹。
本发明根据上述见解而完成，本发明的带Ag基底层的金属部件具备：与被接合体接合的金属部件；和形成于该金属部件的与所述被接合体的接合面的Ag基底层，其特征在于，所述Ag基底层由形成于所述金属部件侧的玻璃层和层压形成于该玻璃层的Ag层构成，所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下。
在该结构的带Ag基底层的金属部件中，由于所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下，因此即使在该Ag基底层上形成由接合材的烧成体构成的接合层来接合被接合体、其中所述接合材包含Ag及氧化银中的一方或双方和有机物的情况下，也能够抑制在高温环境下使用时以Ag基底层的Ag层侧表面的空隙为起点在接合层内产生裂纹。由此，本发明的带Ag基底层的金属部件即使在高温环境下也能够稳定地使用。
另外，本发明的带Ag基底层的绝缘电路基板具备：绝缘层；配设于该绝缘层的一面的电路层；和形成于所述电路层中的与所述绝缘层相反侧的面的Ag基底层，其特征在于，所述电路层和所述Ag基底层设为上述的带Ag基底层的金属部件，所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下。
在该结构的带Ag基底层的绝缘电路基板中，由于所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下，因此即使在该Ag基底层上形成由接合材的烧成体构成的接合层来接合半导体元件等电子部件、其中所述接合材包含Ag及氧化银中的一方或双方和有机物的情况下，也能够抑制在高温环境下使用时以Ag基底层的Ag层侧表面的空隙为起点在接合层内层产生裂纹。由此，即使在高温环境下使用的情况下，也能够确保电路层与半导体元件等电子部件的接合可靠性。
进而，本发明的带Ag基底层的绝缘电路基板具备：绝缘层；配设于该绝缘层的一面的电路层；配设于所述绝缘层的另一面的金属层；和形成于所述金属层中的与所述绝缘层相反侧的面的Ag基底层，其特征在于，所述电路层和所述Ag基底层设为上述的带Ag基底层的金属部件，所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下。
在该结构的带Ag基底层的绝缘电路基板中，由于所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下，因此即使在该Ag基底层上形成由接合材的烧成体构成的接合层来接合散热器等、其中所述接合材包含Ag及氧化银中的一方或双方和有机物的情况下，也能够抑制在高温环境下使用时以Ag基底层的Ag层侧表面的空隙为起点在接合层内层产生裂纹。由此，即使在高温环境下使用的情况下，也能够确保金属层与散热器等的接合可靠性。
另外，本发明的半导体装置，其特征在于，具备：上述的带Ag基底层的绝缘电路基板；和接合于所述电路层的所述Ag基底层的半导体元件，所述半导体元件与所述Ag基底层通过接合材的烧成体构成的接合层而接合，所述接合材包含Ag及氧化银中的一方或双方和有机物。
根据该结构的半导体装置，由于所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下，因此能够抑制以Ag基底层的Ag层侧表面的空隙为起点在接合层内层产生裂纹。由此，即使在高温环境下使用的情况下，也能够确保电路层与半导体元件等的接合可靠性。
进而，本发明的带散热器的绝缘电路基板，其特征在于，具备：上述的带Ag基底层的绝缘电路基板；和接合于所述金属层的散热器，所述散热器与形成于所述金属层的所述Ag基底层通过接合材的烧成体构成的接合层而接合，所述接合材包含Ag及氧化银中的一方或双方和有机物。
根据该结构的带散热器的绝缘电路基板，由于所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下，因此能够抑制以Ag基底层的Ag层侧表面的空隙为起点在接合层内层产生裂纹。由此，即使在高温环境下使用的情况下，也能够确保金属层与散热器的接合可靠性。
另外，本发明的带Ag基底层的金属部件的制造方法，其特征在于，其为上述的具有基底层的金属部件的制造方法，具备：含玻璃Ag膏涂布工序，对所述金属部件中的接合所述被接合体的接合面涂布含有玻璃成分的含玻璃Ag膏；第一干燥工序，使涂布后的含玻璃Ag膏干燥；Ag膏涂布工序，在干燥后的所述含玻璃Ag膏上涂布Ag膏；第二干燥工序，使涂布后的Ag膏干燥；以及烧成工序，对干燥后的所述含玻璃Ag膏和所述Ag膏进行烧成，形成具有玻璃层和Ag层的Ag基底层，并且将所述Ag基底层的所述Ag层侧表面的空隙的面积率设为25％以下。
根据该结构的带Ag基底层的金属部件的制造方法，由于对金属部件涂布含玻璃Ag膏并干燥之后，在涂布干燥的含玻璃Ag膏上涂布Ag膏并干燥，然后进行烧成，因此在金属部件侧形成有玻璃层，在该玻璃层上形成有Ag层，并且在Ag层的表面不会产生因玻璃引起的裂纹，能够将Ag层的表面中的空隙的面积率设为25％以下。
根据本发明，能够提供一种即使在较高温环境下使用的情况下，也能够抑制接合层内的裂纹的产生，被接合体与金属部件的接合可靠性优异的带Ag基底层的金属部件、包括该带Ag基底层的金属部件的带Ag基底层的绝缘电路基板、使用该带Ag基底层的绝缘电路基板的半导体装置和带散热器的绝缘电路基板、以及带Ag基底层的金属部件的制造方法。
附图说明
图1是作为本发明的第一实施方式的半导体装置(功率模块)的概略说明图。
图2是表示Ag基底层与电路层的接合部分的主要部分放大剖视图。
图3是作为本发明的第一实施方式的带Ag基底层的绝缘电路基板(带Ag基底层的功率模块用基板)的制造方法及半导体装置(功率模块)的制造方法的流程图。
图4是作为本发明的第一实施方式的带Ag基底层的绝缘电路基板(带Ag基底层的功率模块用基板)的制造方法及半导体装置(功率模块)的制造方法的概略说明图。
图5是作为本发明的第二实施方式的半导体装置(功率模块)及带散热器的绝缘电路基板(带散热器的功率模块用基板)的概略说明图。
图6是作为本发明的第二实施方式的带散热器的绝缘电路基板(带散热器的功率模块用基板)的制造方法及半导体装置(功率模块)的制造方法的流程图。
图7A是作为本发明的第二实施方式的带Ag基底层的绝缘电路基板(带散热器的功率模块用基板)的制造方法的概略说明图。
图7B是作为本发明的第二实施方式的带Ag基底层的绝缘电路基板(带散热器的功率模块用基板)的制造方法的概略说明图。
图8是作为本发明的第二实施方式的带散热器的绝缘电路基板(带散热器的功率模块用基板)的制造方法及半导体装置(功率模块)的制造方法的概略说明图。
图9是作为本发明的其他实施方式的半导体装置的概略说明图。
图10是本发明例及比较例中的Ag基底层的Ag层侧表面的观察照片。
具体实施方式
以下，参考附图对本发明的实施方式进行说明。
<第一实施方式>
首先，对本发明的第一实施方式进行说明。此外，作为本实施方式的半导体装置是搭载了为了控制风力发电、电动汽车等电气车辆等而使用的大功率控制用的功率半导体元件的功率模块。
图1表示作为本发明的第一实施方式的功率模块(半导体装置)1。该功率模块1具备：具有Ag基底层30和功率模块用基板10的带Ag基底层的功率模块用基板(带Ag基底层的绝缘电路基板)50；及在该带Ag基底层的功率模块用基板50的一面(图1中为上表面)通过接合层2而接合的半导体元件3。
如图1所示，功率模块用基板10具备：构成绝缘层的陶瓷基板11；及配设于该陶瓷基板11的一面(图1中为上表面)的电路层12。
陶瓷基板11为防止配设于作为绝缘层的陶瓷基板11的一面的电路层12与配设于作为绝缘层的陶瓷基板11的另一面的金属层(未图示)之间的电连接的基板，例如，由绝缘性较高的AlN(氮化铝)、Si3N4(氮化硅)、Al2O3(氧化铝)等构成。在本实施方式中，由散热性优异的AlN(氮化铝)构成。并且，陶瓷基板11的厚度被设定在0.2～1.5mm的范围内，在本实施方式中设定为0.635mm。
电路层12通过在陶瓷基板11的一面接合具有导电性的金属板来形成。在本实施方式中，电路层12通过将由纯度为99.99质量％以上的铝(所谓的4N铝)的轧制板构成的铝板接合于陶瓷基板11来形成。此外，该电路层12形成有电路图案，其一面(图1中为上表面)设为搭载半导体元件3的搭载面。在此，电路层12的厚度被设定在0.1mm以上且3.0mm以下的范围内，在本实施方式中设定为0.6mm。
而且，在该电路层12的一面(与陶瓷基板11相反侧的面)形成有Ag基底层30。在本实施方式中，上述的电路层12和Ag基底层30设为带Ag基底层的金属部件。
如后所述，该Ag基底层30设为包含玻璃成分的含玻璃Ag膏的烧成体。该Ag基底层30在接合半导体元件3之前的状态下，如图1和图2所示，具备形成于电路层12侧的玻璃层31和形成于该玻璃层31上的Ag层32。
玻璃层31内部分散有粒径为几纳米程度的微细的导电性粒子33。该导电性粒子33设为含有Ag或Al中的至少一个的结晶性粒子。此外，玻璃层31内的导电性粒子33通过使用例如透射电子显微镜(TEM)来观察。
另外，Ag层32的内部分散有粒径为几纳米程度的微细的玻璃粒子(未图示)。
另外，在本实施方式中，电路层12由纯度为99.99质量％以上的铝构成，因此电路层12的表面形成有在大气中自然产生的铝氧化被膜12A。在此，形成有前述的Ag基底层30的部分中，该铝氧化被膜12A被去除，在电路层12上直接形成有Ag基底层30。即，如图2所示，构成电路层12的铝与玻璃层31直接接合。
如图2所示，在本实施方式中，在电路层12上自然产生的铝氧化被膜12A的厚度to设为4nm≤to≤6nm的范围内。另外，玻璃层31的厚度tg成为0.01μm≤tg≤5μm的范围内，Ag层32的厚度ta成为1μm≤ta≤100μm的范围内。
此外，该Ag基底层30的厚度方向的电阻值P设为0.5Ω以下。在此，在本实施方式中，Ag基底层30的厚度方向上的电阻值P设为图2中的Ag基底层30的上表面与电路层12的上表面之间的电阻值。这是因为构成电路层12的铝(4N铝)的电阻与Ag基底层30的厚度方向的电阻相比非常小。此外，测量该电阻时，测量Ag基底层30的上表面中央点与从Ag基底层30的下表面端部向着电路层12的外周方向隔开规定距离的电路层12上的点之间的电阻，其中，该规定距离与从Ag基底层30的所述上表面中央点至Ag基底层30的上表面端部的距离相同。
而且，在作为本实施方式的带Ag基底层的功率模块用基板50中，Ag基底层30的Ag层32侧的表面、即接合有半导体元件3的接合面上的空隙的面积率设为25％以下。此外，对于该Ag基底层30的Ag层32侧的表面中的空隙的面积率，能够通过激光显微镜观察Ag基底层30的Ag层32侧的表面，将得到的图像进行二值化处理并将黑色部分判定为空隙来计算。
在作为本实施方式的功率模块1中，如图1所示，在半导体元件3与Ag基底层30之间设置有接合层2。
接合层2设为包括Ag粒子及氧化银粒子的至少一方或双方和有机物的接合材的烧成体，在本实施方式中，设为包括氧化银粒子和由有机物构成的还原剂的氧化银膏的烧成体。即，接合层2设为氧化银被还原的Ag的烧成体。在此，通过还原氧化银来生成的粒子由于例如粒径10nm～1μm而非常微细，因此形成由致密的Ag的烧成体构成的接合层2。
在接合层2中并未分散有如Ag层32那样粒径为几纳米程度的微细的玻璃粒子。
接着，参照图3及图4，对作为本实施方式的功率模块1的制造方法、以及带Ag基底层的功率模块用基板50的制造方法进行说明。
(含玻璃Ag膏涂布工序S01)
首先，准备在陶瓷基板11的一面形成有电路层12的功率模块用基板10，在该功率模块用基板10的电路层12上涂布含玻璃Ag膏40。此外，涂布含玻璃Ag膏40时能够采用网版印刷法、胶版印刷法、感光性工艺等各种方法。
含玻璃Ag膏40的涂布厚度设为1μm以上且30μm以下的范围内即可。在本实施方式中通过网版印刷法将含玻璃Ag膏40形成为图案状。
在此，对上述的含玻璃Ag膏进行说明。
该含玻璃Ag膏含有Ag粉末、玻璃粉末、树脂、溶剂及分散剂，由Ag粉末和玻璃粉末构成的粉末成分的含量设为含玻璃Ag膏整体的60质量％以上且90质量％以下，余量设为树脂、溶剂、分散剂。
此外，在本实施方式中，由Ag粉末和玻璃粉末构成的粉末成分的含量设为含玻璃Ag膏整体的85质量％。
另外，该含玻璃Ag膏的粘度调节为10Pa·s以上且500Pa·s以下，更优选调节为50Pa·s以上且300Pa·s以下。
Ag粉末的粒径设为0.05μm以上且1.0μm以下，在本实施方式中使用平均粒径为0.8μm的粉末。
玻璃粉末例如含有氧化铅、氧化锌、氧化硅、氧化硼、氧化磷及氧化铋中的任意一种或两种以上，其玻璃化转变温度设为300℃以上且450℃以下，软化温度设为600℃以下，结晶化温度设为450℃以上。
在本实施方式中使用由氧化铅、氧化锌及氧化硼构成，平均粒径为0.5μm的玻璃粉末。
另外，Ag粉末的重量A与玻璃粉末的重量G的重量比A/G调节在80/20至99/1的范围内，在本实施方式中设为A/G＝80/5。
溶剂适合沸点为200℃以上的溶剂，在本实施方式中使用二乙二醇二丁醚。
树脂为调节含玻璃Ag膏的粘度的树脂，适合在500℃以上可分解的树脂。在本实施方式中使用乙基纤维素。
另外，在本实施方式中添加有二羧酸系的分散剂。此外，也可不添加分散剂而构成含玻璃Ag膏。
该含玻璃Ag膏通过如下的方法来制备：即，将混合Ag粉末和玻璃粉末而成的混合粉末与混合溶剂和树脂而成的有机混合物与分散剂一同利用搅拌器进行预混合，利用辊磨机边混入所得到的预混合物边进行混合之后，利用膏过滤器过滤所得到的混匀物。
(第一干燥工序S02)
接着，在电路层12的一面涂布有含玻璃Ag膏40的状态下进行干燥。此外，在该第一干燥工序S02中，为了充分干燥溶剂，在100℃以上且150℃以下的温度保持15分钟以上且30分钟以下来进行干燥处理。干燥时的气氛可以在大气、真空、N2或Ar等惰性气氛下进行。
(Ag膏涂布工序S03)
接着，在干燥的含玻璃Ag膏40上涂布Ag膏42。作为Ag膏42的涂布厚度，设为1μm以上且30μm以下即可。
此外，该Ag膏42设为从上述的含玻璃Ag膏40去除了玻璃成分的物质。用于Ag膏42的Ag粉末优选为与含玻璃Ag膏40中使用的Ag粉末具有相同粒径。通过使用相同粒径的Ag粉末，从而能够在后述的烧成工序中使Ag粉末良好地烧结。
Ag膏42以与含玻璃Ag膏40同样的方法，涂布在干燥的含玻璃Ag膏40上。
(第二干燥工序S04)
接着，以层压在含玻璃Ag膏40的方式涂布有Ag膏42的状态下进行干燥。此外，在该第二干燥工序S04中，为了充分干燥溶剂，在100℃以上且150℃以下的温度保持15分钟以上且30分钟以下来进行干燥处理。干燥时的气氛可以在大气、真空、N2或Ar等惰性气氛下进行。
在此，干燥后的含玻璃Ag膏40的厚度t1与Ag膏42的厚度t2之比t1/t2优选设为0.2以上且5.0以下的范围内。
(烧成工序S05)
接着，在电路层12的一面层压有含玻璃Ag膏40及Ag膏42的状态下，装入加热炉71内进行加热处理，进行含玻璃Ag膏40的烧成。此外，此时的烧成温度例如设定为350℃以上且645℃以下。通过该烧成工序S05，形成具备玻璃层31和Ag层32的Ag基底层30。另外，Ag基底层30的Ag层32侧的表面中的空隙的面积率设为25％以下。
在烧成工序S05中，含玻璃Ag膏40中的玻璃粉末成分软化流动的同时与Ag或Al进行反应，形成了分散有粒径为几纳米程度的微细的导电性粒子33的玻璃层31和分散有粒径为几纳米程度的微细的玻璃粒子的Ag层32。
由于Ag膏42未含有成为烧结的阻碍的玻璃，因此Ag的结晶粒易生长。由此，在Ag膏42烧结的区域、即在Ag基底层30的Ag层32侧的表面，空隙降低。空隙的面积率更优选为15％以下。
在该烧成工序S05中，烧成含玻璃Ag膏40时，通过玻璃层31在电路层12的表面自然产生的铝氧化被膜12A被熔化去除，在电路层12上直接形成玻璃层31。另外，玻璃层31的内部分散有粒径为几纳米程度的微细的导电性粒子33。该导电性粒子33设为含有Ag或Al中的至少一个的结晶性粒子，推测为烧成时析出于玻璃层31内部。
进而，Ag层32的内部分散有粒径为几微米程度的玻璃粒子。该玻璃粒子被推测为在Ag粒子的烧结进行的过程中，由残存的玻璃成分凝集而成。
如此，制造作为本实施方式的带Ag基底层的功率模块用基板50。
(接合材涂布工序S06)
接着，在Ag基底层30的表面，作为成为接合层2的接合材，涂布包含Ag及氧化银中的一方或双方和有机物的接合材45。在本实施方式中，作为接合材使用氧化银膏。
此外，涂布氧化银膏时，能够采用网版印刷法、胶版印刷法、感光性工艺等各种方法。在本实施方式中，通过网版印刷法印刷氧化银膏45。
在此，对上述的氧化银膏进行说明。
该氧化银膏含有氧化银粉末(氧化银粒子)、还原剂、树脂和溶剂，在本实施方式中，在这些的基础上还含有有机金属化合物粉末。
在氧化银膏中，氧化银粉末的含量设为氧化银膏整体的60质量％以上且92质量％以下、还原剂的含量设为氧化银膏整体的5质量％以上且20质量％以下、有机金属化合物粉末的含量设为氧化银膏整体的0质量％以上且10质量％以下、余量设为溶剂。为了抑制通过烧结得到的接合层2中残留有未反应的有机物，在氧化银膏中不添加分散剂及树脂。
还原剂设为具有还原性的有机物，例如可以使用醇、有机酸。
有机金属化合物具有通过因热分解生成的有机酸促进氧化银的还原反应或有机物的分解反应的作用，例如可适用甲酸银、乙酸银、丙酸银、苯甲酸银、草酸银等的羧酸系金属盐等。
此外，该氧化银膏的粘度调节为10Pa·s以上且500Pa·s以下，更优选调节为50Pa·s以上且300Pa·s以下。
(半导体元件接合工序S07)
接着，在涂布接合材(氧化银)45的状态下干燥(例如，在室温、大气气氛下保管24小时)之后，在接合材45上层压半导体元件3，在层压半导体元件3和带Ag基底层的功率模块用基板50的状态下装入加热炉72内，进行接合材(氧化银膏)45的烧成，形成接合层2并接合半导体元件3。
在该半导体元件接合工序S07中，通过在层压方向上加压半导体元件3和带Ag基底层的功率模块用基板50的状态下进行加热，从而能够更切实地进行接合。在这种情况下，层压方向的加压压力优选设为0.5～10MPa。
如此，在Ag基底层30上形成有接合层2，半导体元件3与电路层12被接合。由此，制造作为本实施方式的功率模块1。
根据如上构成的本实施方式所涉及的功率模块1及带Ag基底层的功率模块用基板50，在电路层12的一面形成有由玻璃层31和层压配置于该玻璃层31上的Ag层32构成的Ag基底层30，Ag基底层30中的Ag层32侧表面(即，与半导体元件3的接合侧面或与接合层2的接触面)上的空隙的面积率设为25％以下，因此即使在施加达到较高温的冷热循环负载的情况下，也能够抑制形成于Ag基底层30上的由氧化银膏的烧成体构成的接合层2中产生以Ag基底层30的Ag层32侧表面的空隙为起点的裂纹。由此，即使在高温环境下使用的情况下，也能够确保电路层12与半导体元件3的接合可靠性。
本发明中高温环境下是指200℃以上的温度环境。
另外，本实施方式中具备：含玻璃Ag膏涂布工序S01，在电路层12上涂布含玻璃Ag膏40；第一干燥工序S02，使涂布后的含玻璃Ag膏40干燥；Ag膏涂布工序S03，在干燥的含玻璃Ag膏40上涂布Ag膏42；第二干燥工序S04，使涂布后的Ag膏42干燥；以及烧成工序S05，对层压于电路层12上的含玻璃Ag膏40及Ag膏42烧成，因此在电路层12侧形成有玻璃层31，在该玻璃层31上形成有Ag层32，并且在Ag层32的表面不会产生因玻璃引起的空隙，能够将Ag层32侧表面的空隙的面积率设为25％以下。
<第二实施方式>
接着，参考图5至图8，对本发明的第二实施方式进行说明。
图5示出作为本发明的第二实施方式的半导体装置101。该半导体装置101具备：带散热器的功率模块用基板(带散热器的绝缘电路基板)160、和在带散热器的功率模块用基板160的一面(图5中为上表面)侧通过第一接合层102接合的半导体元件103。
另外，带散热器的功率模块用基板160具备带Ag基底层的功率模块用基板150、和在该带Ag基底层的功率模块用基板150的另一面(图5中为下表面)侧通过第二接合层105接合的散热器161。
如图5所示，带Ag基底层的功率模块用基板150具备：陶瓷基板111、配设于该陶瓷基板111的一面(图5中为上表面)的电路层112(金属部件)、配设于陶瓷基板111的另一面(图5中下表面)的金属层113(金属部件)、形成于电路层112的一面的第一Ag基底层130a、和形成于金属层113的另一面的第二Ag基底层130b。
陶瓷基板111为防止电路层112与金属层113之间的电连接的基板，在本实施方式中，由绝缘性较高的AlN(氮化铝)构成。在此，陶瓷基板111的厚度被设定在0.2～1.5mm的范围内，在本实施方式中设定为0.635mm。
电路层112通过在陶瓷基板111的一面接合由铜或铜合金构成的铜板来形成。在本实施方式中，作为构成电路层112的铜板，可使用无氧铜的轧制板。该电路层112形成有电路图案，该一面设为搭载半导体元件103的搭载面。
在此，电路层112的厚度被设定在0.1mm以上且3.0mm以下的范围内，在本实施方式中设定为0.6mm。
金属层113通过在陶瓷基板111的另一面接合由铝或铝合金构成的铝板来形成。在本实施方式中，作为构成金属层113的铝板，可使用纯度99.99质量％以上的铝(4N铝)的轧制板。在此，金属层113的厚度被设定在0.5mm以上且6mm以下的范围内，在本实施方式中设定为1.0mm。
散热器161用于散发绝缘电路基板110侧的热。散热器161优选由导热性良好的材质构成，在本实施方式中由A6063(Al合金)构成。在该散热器161中设置有供冷却用流体流动的流路162。
另外，散热器161中的与金属层113接合的区域中，形成有第三Ag基底层130c。
在本实施方式中，电路层112和第一Ag基底层130a、金属层113和第二Ag基底层130b、散热器161和第三Ag基底层130c分别成为带Ag基底层的金属部件。
这些第一Ag基底层130a、第二Ag基底层130b、第三Ag基底层130c与第一实施方式同样，设为包含玻璃成分的含玻璃Ag膏与Ag膏的烧成体。这些第一Ag基底层130a、第二Ag基底层130b、第三Ag基底层130c在接合前的状态下，与第一实施方式同样，具备形成于电路层112、金属层113和散热器161侧的玻璃层、以及形成于该玻璃层上的Ag层。
而且，在本实施方式中，第一Ag基底层130a、第二Ag基底层130b、第三Ag基底层130c中的Ag层侧表面的空隙的面积率设为25％以下。
另外，在本实施方式的功率模块101中，第一接合层102和第二接合层105设为包含Ag粒子及氧化银粒子的至少一方或双方和有机物的接合材的烧成体，在本实施方式中，与第一实施方式同样，设为包含氧化银粒子和由有机物构成的还原剂的氧化银膏的烧成体。
接着，参照图6至图8，对作为本实施方式的功率模块101的制造方法、带Ag基底层的功率模块用基板150及带散热器的功率模块用基板160的制造方法进行说明。
(含玻璃Ag膏涂布工序S101)
首先，准备在陶瓷基板111的一面形成有电路层112，在陶瓷基板111的另一面形成有金属层113的功率模块用基板110，在该功率模块用基板110的电路层112涂布含玻璃Ag膏40，并且在金属层113涂布含玻璃Ag膏40。作为涂布厚度，设为1μm以上且30μm以下即可。
进而，在散热器161中的与金属层113接合的接合面涂布含玻璃Ag膏40。
(第一干燥工序S102)
接着，在电路层112、金属层113和散热器161涂布有含玻璃Ag膏40的状态下进行干燥。
(Ag膏涂布工序S103)
接着，在干燥的含玻璃Ag膏40上涂布Ag膏42。
此外，该Ag膏42设为从上述的含玻璃Ag膏40去除了玻璃成分的物质。用于Ag膏42的Ag粉末优选为与含玻璃Ag膏40中使用的Ag粉末具有相同粒径。通过使用相同粒径的Ag粉末，从而能够在后述的烧成工序中使Ag粉末良好地烧结。
(第二干燥工序S104)
接着，以在含玻璃Ag膏40层压的方式涂布Ag膏42的状态下进行干燥。
在此，干燥后的含玻璃Ag膏40的厚度t1与Ag膏42的厚度t2之比t1/t2优选设为0.2以上且5.0以下的范围内。
(烧成工序S105)
接着，在层压含玻璃Ag膏40和Ag膏42的状态下，装入加热炉171、172内进行加热处理，进行含玻璃Ag膏40和Ag膏42的烧成。此外，此时的烧成温度例如设定为350℃～645℃。
通过该烧成工序S105，形成具备玻璃层和Ag层的第一Ag基底层130a、第二Ag基底层130b、第三Ag基底层130c。
另外，第一Ag基底层130a、第二Ag基底层130b、第三Ag基底层130c中的Ag层侧表面的空隙的面积率设为25％以下。
如此，制造作为本实施方式的带Ag基底层的功率模块用基板150，并且制造形成了第三Ag基底层130c的散热器161。
(接合材涂布工序S106)
接着，在第一Ag基底层130a的表面，作为成为第一接合层102的接合材，涂布包含Ag及氧化银中的一方或双方和有机物的接合材45，并且在第二Ag基底层130b的表面，作为成为第二接合层105的接合材，涂布包含Ag及氧化银中的一方或双方和有机物的接合材45。此外，在本实施方式中，作为接合材使用氧化银膏。
(散热器接合工序S107和半导体元件接合工序S108)
接着，在涂布接合材(氧化银膏)45的状态下干燥(例如，在室温、大气气氛下保管24小时)之后，在涂布于第一Ag基底层130a的接合材45上层压半导体元件103，并且在涂布于第二Ag基底层130b的接合材45上层压散热器161。此时，形成于散热器161的第三Ag基底层130c朝向接合材45侧配置。
而且，在层压半导体元件103、绝缘电路基板110和散热器161的状态下装入加热炉173内，进行接合材(氧化银膏)45的烧成。此时，通过在层压方向上加压半导体元件103、绝缘电路基板110和散热器161的状态下进行加热，从而能够更切实地进行接合。在这种情况下，加压压力优选设为0.5～10MPa。
如此，半导体元件103与电路层112被接合，并且金属层113与散热器161被接合，制造作为本实施方式的半导体装置101和带散热器的功率模块用基板160。
根据如上构成的第二实施方式的半导体装置101和带Ag基底层的功率模块用基板150，能够实现与第一实施方式同样的效果。
另外，根据本实施方式的带散热器的功率模块用基板160，在金属层113的表面形成有第二Ag基底层130b，在散热器161的接合面形成有第三Ag基底层130c，在这些第二基底层130b、第三Ag基底层130c之间形成有由氧化银膏的烧成体构成的第二接合层105，因此能够切实地接合金属层113与散热器161。
而且，第二Ag基底层130b和第三Ag基底层130c中的Ag层侧的表面中的空隙的面积率设为25％以下，因此在高温环境下使用时，能够抑制以第二Ag基底层130b和第三Ag基底层130c的Ag层侧表面中存在的空隙为起点在接合层105产生裂纹。由此，即使在高温环境下使用的情况下，也能够确保金属层113与散热器161的接合可靠性。
以上，对本发明的实施方式进行了说明，但本发明并不限定于此，在不脱离本发明的技术思想的范围内能够进行适当变更。
例如，将构成电路层的金属板设为纯度99.99质量％的纯铝(4N铝)的轧制板或无氧铜的轧制板来进行了说明，但并不限定于此，也可由其他铝或铝合金、铜或铜合金构成。进而，还可以为固相扩散接合铜板和铝板的结构。
另外，作为绝缘层使用由AlN构成的陶瓷基板进行了说明，但并不限定于此，可使用由Si3N4或Al2O3等构成的陶瓷基板，也可由绝缘树脂构成绝缘层。
另外，散热器并不限定于本实施方式中的示例，散热器的结构并不特别限定。
进而，可在散热器与金属层之间设置缓冲层。作为缓冲层，能够使用由铝或铝合金或者包含铝的复合材料(例如AlSiC等)构成的板材。
另外，在本实施方式中，作为半导体装置，举出搭载了功率半导体元件的功率模块为例进行了说明，但并不限定于此，只要在由导电性材料构成的电路层上搭载半导体元件的半导体装置即可。
例如图9所示，还可以为搭载LED元件(半导体元件)的LED装置(半导体装置)。
图9所示的LED装置201具备LED元件203和由导电性材料构成的电路层212。此外，LED元件203的结构为通过接合线207与电路层212电连接，具备由封装材208封装LED元件203和接合线207而成的结构。在电路层212的一面设有由含玻璃Ag膏和Ag膏的烧成体构成的Ag基底层230，在LED元件203的背面设有导电性反射膜216和保护膜215。而且，具备LED元件203在Ag基底层230上通过接合层202接合的结构，所述接合层202由包含Ag及氧化银中的一方或双方和有机物的接合材的烧成体构成。
在这种LED装置201中，也在电路层212的一面形成有Ag基底层230，在该Ag基底层230的Ag层侧表面(即，与LED元件203的接合面)上的空隙的面积率设为25％以下，因此即使在高温环境下使用的情况下，也能够抑制因Ag层侧表面中存在的空隙而在接合层产生裂纹。由此，即使在高温环境下，电路层212与LED元件203的接合可靠性也优异。
实施例
对为了确认本发明的有效性而进行的确认实验进行说明。
在陶瓷基板的一面和另一面接合金属板来形成电路层和金属层。在此，陶瓷基板设为AlN，尺寸设为27mm×17mm×0.6mm。成为电路层和金属层的金属板设为表1所示的材质，尺寸设为25mm×15mm×0.3mm。
此外，金属板为铝板的情况下，作为接合材使用无铅的Al-Si类钎料。另外，金属板为铜板的情况下，作为接合材使用无铅的活性金属钎料(Ag-Cu-Ti钎料)。
在本发明例中，在电路层的表面涂布在实施方式中说明的含玻璃Ag膏并在150℃下干燥30分钟之后，涂布Ag膏并在150℃下干燥30分钟，然后在550℃下进行30分钟加热处理，从而形成Ag基底层。
此外，作为含玻璃Ag膏的玻璃粉末使用包含90.6质量％的Bi2O3、2.6质量％的ZnO、6.8质量％的B2O3的无铅玻璃粉末。另外，作为树脂使用乙基纤维素，作为溶剂使用二乙二醇二丁醚。进而，添加二羧酸系的分散剂。Ag粉末使用粒径0.8μm的粉末。
另外，作为Ag膏使用从上述的含玻璃Ag膏去除了玻璃粉末的物质。
此外，含玻璃Ag膏的涂布量和Ag膏的涂布量如表1记载。
如上所述，得到本发明例的带Ag基底层的功率模块用基板。
而且，在本发明例的带Ag基底层的功率模块用基板的Ag基底层上涂布氧化银膏(涂布厚度：10μm)之后，配置半导体元件，烧成氧化银膏，从而形成接合层，制作了本发明例的半导体装置。
在此，氧化银膏的烧成条件设为氮气气氛、烧成温度300℃、烧成时间10分钟、加压压力5MPa。
另外，作为氧化银膏，使用如下的氧化银膏：即，该氧化银膏通过使用市售的氧化银粉末(和光纯药工业株式会社制)、作为还原剂的肉豆蔻醇、以及作为溶剂的2,2,4-三甲基-1,3-戊二醇单异丁酸酯，以氧化银粉末:80质量％、还原剂(肉豆蔻醇):10质量％、溶剂(2,2,4-三甲基-1,3-戊二醇单异丁酸酯):余量的比例混合而成。
比较例中，在电路层的表面涂布在实施方式中说明的含玻璃Ag膏并干燥之后，在550℃下加热处理10分钟，从而形成Ag基底层，得到比较例的带Ag基底层的功率模块用基板。
此外，含玻璃Ag膏的涂布量如表1记载。
而且，在比较例的带Ag基底层的功率模块用基板的Ag基底层上涂布氧化银膏(涂布厚度：10μm)之后，配置半导体元件，以与本实施例同样的条件下烧成氧化银膏，从而形成接合层，制作比较例的半导体装置。
(Ag基底层的Ag层侧表面的空隙的面积率)
在本发明例和比较例中，通过激光显微镜(株式会社KEYENCE制VKX-200)观察形成的Ag基底层的Ag层侧表面，将得到的图像通过激光显微镜附属软件进行二值化处理，将黑色部分判定为空隙并通过下式求出空隙的面积率。
空隙的面积率(％)＝(黑色部分(空隙)面积/Ag基底层整体的面积)×100
此外，图10示出本发明例和比较例中的Ag基底层的Ag层侧表面的激光显微镜观察照片。图10的(a-1)为比较例1的观察照片、(a-2)为(a-1)的二值化处理后的图像、图10的(b-1)为本发明例3的观察照片、(b-2)为(b-1)的二值化处理后的图像。
(冷热循环前后的接合率)
对上述的本发明例和比较例的半导体装置，使用超声波探伤装置，根据下式求出半导体元件与电路层的接合率。在此，初始接合面积是指接合前应接合的面积、即半导体元件面积。超声波探伤图像中接合部内的白色部分表示剥离，因此将该白色部分的面积设为剥离面积。
(接合率)＝[{(初始接合面积)-(剥离面积)}/(初始接合面积)]×100
此外，对半导体装置利用气相进行冷热循环试验，比较初始的接合率与冷热循环试验后的接合率。冷热循环试验设为-40℃×15分钟←→200℃×15分钟、3000次循环。在表1中示出评价结果。
[表1]
*4N铝:纯度99.99质量％以上的铝
在Ag基底层的Ag层侧表面的空隙的面积率超过25％的比较例中，冷热循环后的接合率大幅降低。推测是由于当施加达到200℃的高温的冷热循环负载时，在由氧化银膏的烧成体构成的接合层产生以Ag基底层表面的空隙为起点的裂纹。
与此相对，在Ag基底层的Ag层侧表面的空隙的面积率设为25％以下的本发明例中，即使在冷热循环后接合率也没有太大变化。
如上所示，根据本发明例，即使在较高温环境下使用的情况下，也能够抑制接合层中的裂纹的进展，提供能够与被接合体牢固地接合的带Ag基底层的金属部件。
符号说明
1、101 功率模块(半导体装置)
3、103 半导体元件
10、110 功率模块用基板(绝缘电路基板)
11、111 陶瓷基板(绝缘层)
12、112、212 电路层
30、130a、130b、130c、230 Ag基底层
31 玻璃层
32 Ag层
50、150 带Ag基底层的功率模块用基板(带Ag基底层的绝缘电路基板)
113 金属层
160 带散热器的功率模块用基板(带散热器的绝缘电路基板)
161 散热器

Claims (6)

1.一种带Ag基底层的金属部件，具备：与被接合体接合的金属部件；和形成于该金属部件的与所述被接合体的接合面的Ag基底层，其特征在于，
所述Ag基底层由形成于所述金属部件侧的玻璃层和层压形成于该玻璃层的Ag层构成，
所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下。
2.一种带Ag基底层的绝缘电路基板，具备：绝缘层；配设于该绝缘层的一面的电路层；和形成于所述电路层中的与所述绝缘层相反侧的面的Ag基底层，其特征在于，
所述电路层和所述Ag基底层设为权利要求1所述的带Ag基底层的金属部件，
所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下。
3.一种带Ag基底层的绝缘电路基板，具备：绝缘层；配设于该绝缘层的一面的电路层；配设于所述绝缘层的另一面的金属层；和形成于所述金属层中的与所述绝缘层相反侧的面的Ag基底层，其特征在于，
所述电路层和所述Ag基底层设为权利要求1所述的带Ag基底层的金属部件，
所述Ag基底层的所述Ag层侧表面的空隙的面积率为25％以下。
4.一种半导体装置，其特征在于，具备：权利要求2所述的带Ag基底层的绝缘电路基板；和接合于所述电路层的所述Ag基底层的半导体元件，
所述半导体元件与所述Ag基底层通过接合材的烧成体构成的接合层而接合，所述接合材包含Ag及氧化银中的一方或双方和有机物。
5.一种带散热器的绝缘电路基板，其特征在于，具备：权利要求3所述的带Ag基底层的绝缘电路基板；和接合于所述金属层的所述Ag基底层的散热器，
所述散热器与所述Ag基底层通过接合材的烧成体构成的接合层而接合，所述接合材包含Ag及氧化银中的一方或双方和有机物。
6.一种带Ag基底层的金属部件的制造方法，其特征在于，其为权利要求1所述的带Ag基底层的金属部件的制造方法，具备：
含玻璃Ag膏涂布工序，对所述金属部件中的接合所述被接合体的接合面涂布含有玻璃成分的含玻璃Ag膏；
第一干燥工序，使涂布后的含玻璃Ag膏干燥；
Ag膏涂布工序，在干燥后的所述含玻璃Ag膏上涂布Ag膏；
第二干燥工序，使涂布后的Ag膏干燥；以及
烧成工序，对干燥后的所述含玻璃Ag膏和所述Ag膏进行烧成，形成具有玻璃层和Ag层的Ag基底层，并且将所述Ag基底层的所述Ag层侧表面的空隙的面积率设为25％以下。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246871A (zh) * 2007-02-15 2008-08-20 Tdk株式会社 多层陶瓷衬底及其制造方法
JP2011014556A (ja) * 2009-06-30 2011-01-20 Hitachi Ltd 半導体装置とその製造方法
JP2013202648A (ja) * 2012-03-28 2013-10-07 Mitsubishi Materials Corp はんだ接合構造、パワーモジュール、ヒートシンク付パワーモジュール用基板、並びに、はんだ接合構造の製造方法、パワーモジュールの製造方法、ヒートシンク付パワーモジュール用基板の製造方法
CN104704618A (zh) * 2012-10-09 2015-06-10 三菱综合材料株式会社 半导体装置、陶瓷电路基板及半导体装置的制造方法
CN104885214A (zh) * 2012-12-27 2015-09-02 三菱综合材料株式会社 功率模块用基板、自带金属部件的功率模块用基板、自带金属部件的功率模块、功率模块用基板的制造方法、以及自带金属部件的功率模块用基板的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3369665B2 (ja) * 1993-08-27 2003-01-20 日本特殊陶業株式会社 半導体パッケージ用のセラミック製リッド基板およびセラミック製リッド
JP2002362987A (ja) * 2001-06-08 2002-12-18 Hitachi Ltd 電子部品およびその製造方法
JP3922166B2 (ja) 2002-11-20 2007-05-30 三菱マテリアル株式会社 パワーモジュール用基板の製造方法並びにパワーモジュール用基板及びパワーモジュール
JP2006202938A (ja) 2005-01-20 2006-08-03 Kojiro Kobayashi 半導体装置及びその製造方法
JP4737116B2 (ja) 2007-02-28 2011-07-27 株式会社日立製作所 接合方法
US8513534B2 (en) 2008-03-31 2013-08-20 Hitachi, Ltd. Semiconductor device and bonding material
WO2009150741A1 (ja) 2008-06-12 2009-12-17 三菱電機株式会社 光起電力装置の製造方法
JP5966379B2 (ja) 2011-05-31 2016-08-10 三菱マテリアル株式会社 パワーモジュール、及び、パワーモジュールの製造方法
JP5780191B2 (ja) * 2012-03-28 2015-09-16 三菱マテリアル株式会社 パワーモジュール、及び、パワーモジュールの製造方法
TWI642154B (zh) * 2013-12-25 2018-11-21 日商三菱綜合材料股份有限公司 電源模組用基板及其製造方法、電源模組

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246871A (zh) * 2007-02-15 2008-08-20 Tdk株式会社 多层陶瓷衬底及其制造方法
JP2011014556A (ja) * 2009-06-30 2011-01-20 Hitachi Ltd 半導体装置とその製造方法
JP2013202648A (ja) * 2012-03-28 2013-10-07 Mitsubishi Materials Corp はんだ接合構造、パワーモジュール、ヒートシンク付パワーモジュール用基板、並びに、はんだ接合構造の製造方法、パワーモジュールの製造方法、ヒートシンク付パワーモジュール用基板の製造方法
CN104704618A (zh) * 2012-10-09 2015-06-10 三菱综合材料株式会社 半导体装置、陶瓷电路基板及半导体装置的制造方法
CN104885214A (zh) * 2012-12-27 2015-09-02 三菱综合材料株式会社 功率模块用基板、自带金属部件的功率模块用基板、自带金属部件的功率模块、功率模块用基板的制造方法、以及自带金属部件的功率模块用基板的制造方法

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