CN108735770B - 半导体封装件 - Google Patents

半导体封装件 Download PDF

Info

Publication number
CN108735770B
CN108735770B CN201810310753.0A CN201810310753A CN108735770B CN 108735770 B CN108735770 B CN 108735770B CN 201810310753 A CN201810310753 A CN 201810310753A CN 108735770 B CN108735770 B CN 108735770B
Authority
CN
China
Prior art keywords
chip
semiconductor
semiconductor chip
image sensor
sensor unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810310753.0A
Other languages
English (en)
Other versions
CN108735770A (zh
Inventor
金志澈
赵汊济
韩相旭
赵京淳
金载春
朴佑炫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN108735770A publication Critical patent/CN108735770A/zh
Application granted granted Critical
Publication of CN108735770B publication Critical patent/CN108735770B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14806—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92227—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

本发明公开了一种半导体封装件，其包括：衬底上的第一半导体芯片；第二半导体芯片，其位于衬底上并且与第一半导体装置间隔开；模制层，其位于衬底上并且覆盖第一半导体芯片的侧部和第二半导体芯片的侧部；以及图像传感器单元，其位于第一半导体芯片、第二半导体芯片和模制层上。图像传感器单元电连接至第一半导体芯片。

Description

半导体封装件
相关申请的交叉引用
本申请要求于2017年4月18日在韩国知识产权局提交的韩国专利申请No.10-2017-0049704的优先权，该申请的公开以引用方式全文并入本文中。
技术领域
本发明构思涉及一种半导体封装件以及一种制造半导体封装件的方法。更具体地说，本发明构思涉及堆叠的CMOS半导体封装件。
背景技术
通常，电子图像传感器是一种基于半导体的装置，其将光学图像转换为电信号。这种电子图像传感器可主要分为电荷耦合器件(CCD)或者互补金属氧化物半导体(CMOS)图像传感器(CIS)。这两种类型的图像传感器均已用于数码相机、摄录机、个人计算机和监视摄像机中。
然而，CCD图像传感器具有许多不足，诸如复杂驱动方法和高功耗以及需要多步骤光刻工艺的复杂制造工艺。
发明内容
根据本发明构思的一方面，提供了一种半导体封装件，包括：衬底；第一半导体芯片，其位于衬底上；第二半导体芯片，其位于衬底上并且与第一半导体芯片横向间隔开；模制层，其位于衬底上并且覆盖第一半导体芯片的侧部和第二半导体芯片的侧部；以及图像传感器单元，其位于第一半导体芯片、第二半导体芯片和模制层上，并且其中，图像传感器单元包括电连接至第一半导体芯片的电子图像传感器。
根据本发明构思的另一方面，提供了一种半导体封装件，包括：图像传感器单元，其具有相对的第一主表面和第二主表面、其第二主表面上的像素区和与像素区操作性地关联以感测入射于像素区上的光的电子光电探测器；第一下半导体芯片和第二下半导体芯片，位于图像传感器单元的第一主表面上；模制层，其位于图像传感器单元的第一主表面上，并且覆盖第一下半导体芯片的侧部和第二下半导体芯片的侧部；以及连接端子，其介于图像传感器单元的第一主表面与第一下半导体芯片之间，所述连接端子将第一下半导体芯片电连接至图像传感器单元。第一下半导体芯片和第二下半导体芯片的宽度之和小于图像传感器单元的宽度，宽度是在平行于图像传感器单元的第一主表面和第二主表面的方向上测量的尺寸。
根据本发明构思的另一方面，提供了一种半导体封装件，包括：衬底；第一芯片，其布置在衬底上；第二芯片，其布置在衬底上，与第一芯片在第一方向上横向间隔开；模制层，其包封衬底上的第一芯片和第二芯片；第三芯片，其布置在模制层上，并且整体上覆盖第一芯片和第二芯片；以及布置在第三芯片上的像素阵列。第一芯片是存储器芯片，第二芯片是有源芯片、无源芯片或伪芯片，并且第三芯片是电连接至像素阵列和存储器芯片的逻辑芯片。
附图说明
图1是根据本发明构思的半导体封装件的示例的剖视图；
图2和图3是示出封装件中的热传递的图1的半导体封装件的局部剖视图；
图4、图5、图6、图7、图8和图9是半导体封装件在其制造过程中的剖视图，并且一起示出了根据本发明构思的制造半导体封装件的方法；
图10、图11、图12、图13和图14是批量制造的物品的剖视图，并且一起示出了根据本发明构思的制造半导体封装件的批量生产方法。
具体实施方式
现在，将参照附图更完全地描述本发明构思的各个示例。然而，本发明构思可按照许多替代形式实施，并且不应理解为仅限于下文中所述的示例。
图1是示出根据本发明构思的半导体装置的剖视图。在下面的图中，为了清楚起见，将省略或简化半导体芯片中的互连图案和集成电路元件的示出。另外，在随后的描述中，如附图所示，即使示例具有明显可进行相同描述的多个相同类型的元件或特征，为了简单起见，也可参照单个元件(例如，焊盘)或特征(例如，表面)进行描述。
参照图1，可设置衬底100。例如，衬底100可包括印刷电路板(PCB)。衬底100可包括衬底焊盘120和外部端子130。衬底焊盘120可布置在衬底100的(绝缘)主体的上表面上。外部端子130可包括焊料球或者焊料凸块。外部端子130可如虚线所示地经衬底100电连接至衬底焊盘120。电连接可为直接(无中间有源或无源电子组件)或者间接电连接。
可在衬底100上设置第一半导体芯片200。第一半导体芯片200可为诸如DRAM、SRAM、MRAM或闪速存储器的存储器芯片。第一半导体芯片200可为基于硅的芯片。第一半导体芯片200的上表面可为有源表面。例如，第一半导体芯片200可包括设置在其上部的第一导电图案210和第一芯片焊盘220。第一芯片焊盘220可电连接至第一导电图案210的或者由第一导电图案210构成的至少一个集成电路元件或多个集成电路。
可在衬底100上设置第二半导体芯片300。第二半导体芯片300可与第一半导体芯片200横向间隔开，例如，第一半导体芯片200和第二半导体芯片300可并列布置。第二半导体芯片300可具有单层结构，即，可由单一材料构成(在下面更详细地描述的伪芯片的情况下)，或者可具有不同材料的多层结构。尤其在其中第二半导体芯片300具有单层结构的情况下，第二半导体芯片300可包括硅(诸如多晶硅)或金属。
在一些示例中，第二半导体芯片300是存储器芯片、逻辑芯片、电容器或被构造为它们的组合的混合芯片。在这些示例中，第二半导体芯片300可为基于硅的芯片。第二半导体芯片300的上表面可为有源表面。例如，第二半导体芯片300可包括设置在其上部的第二导电图案310和第二芯片焊盘320。第二芯片焊盘320可电连接至由第二导电图案310构成的集成电路(IC)。在其中第二半导体芯片300是存储器芯片、逻辑芯片或者混合芯片的示例中，第二半导体芯片300因其包括IC(即，有源电子组件)而被看作是有源芯片。在其中第二半导体芯片300是电容器(即，芯片电容器)的示例中，第二半导体芯片300因其包括无源电子组件而没有有源电子组件而被看作是无源芯片。
在其它示例中，第二半导体芯片300是伪芯片。在其中第二半导体芯片300是伪芯片的一些示例中，省略了第二导电图案310和第二芯片焊盘320，并且芯片在封装件中电隔离。这里，术语“芯片”仅用于指代占据第三半导体芯片610下方的模制层400中的挨着第一半导体芯片200的空间的主体(诸如单层材料)。本领域公知，术语“伪”是指封装件中的无电子功能的组件。因此，本文所用的“伪芯片”是指与诸如存储器芯片的标准有源芯片或者无源芯片具有相似大小和形状但不执行封装件中的电子操作的材料主体。
第一半导体芯片200和第二半导体芯片300可附着于衬底100。为此，衬底粘合层110可介于第一半导体芯片200和第二半导体芯片300与衬底100之间。
可在衬底100上设置模制层400。模制层400可覆盖第一半导体芯片200和第二半导体芯片300。第一半导体芯片200的侧部200a和第二半导体芯片300的侧部300a可由模制层400覆盖，以不暴露于外部环境。模制层400可填充第一半导体芯片200与第二半导体芯片300之间的空间。模制层400可不覆盖第一半导体芯片200和第二半导体芯片300的下表面。模制层400可暴露出第一半导体芯片200的第一芯片焊盘220和第二半导体芯片300的第二芯片焊盘320。模制层400可防止第一半导体芯片200和第二半导体芯片300被外部碰撞、湿气等损坏。模制层400可包括诸如环氧模塑化合物的绝缘聚合物。模制层400可比衬底100以及第一半导体芯片200和第二半导体芯片300具有更低的导热率。因为模制层400不覆盖第一半导体芯片200和第二半导体芯片300的下表面，所以在半导体封装件的操作过程中，从第一半导体芯片200和第二半导体芯片300产生的热可通过衬底100消散至半导体封装件以外。
图像传感器单元600可布置在模制层400上方。图像传感器单元600的宽度W1可大于第一半导体芯片200的宽度W2和第二半导体芯片300的宽度W3。图像传感器单元600的宽度W1可大于第一半导体芯片200的宽度W2与第二半导体芯片300的宽度W3之和。在平面图中，图像传感器单元600可与第一半导体芯片200和第二半导体芯片300整体重叠。通常，第三半导体芯片610至少在其中第一半导体芯片200和第二半导体芯片300横向彼此间隔开的方向上位于第一半导体芯片200和第二半导体芯片300整体上方。
图像传感器单元600可具有上主表面600a和下主表面600b。图像传感器单元600的上主表面600a可为光入射表面，即，在操作中专用于接收入射光的表面。图像传感器单元600的下主表面600b可面朝第一半导体芯片200和第二半导体芯片300。在一些示例中，在图像传感器单元600的下主表面600b与第一半导体芯片200和第二半导体芯片300之间设置粘合层。图像传感器单元600的下主表面600b可通过粘合层牢固地附着于第一半导体芯片200和第二半导体芯片300。图像传感器单元600的侧部(或者侧“表面”)600c可与模制层400的侧部(或者侧“表面”)400c基本共面。图像传感器单元600可在其整个底表面上被模制层400支承。因此，图像传感器单元600可通过第一半导体芯片200和第二半导体芯片300以及模制层400被稳定地支承在封装件中。图像传感器单元600可感测入射在上主表面600a上的光，并且可将感测到的光作为电信号输出。为此，如将在下面更详细地描述的，图像传感器单元可具有微处理器和微处理器上的包括像素阵列的光电探测器。
图像传感器单元600可包括第三半导体芯片610和感测芯片620，可认为它们之一或二者构成电子图像传感器。感测芯片620可包括将光转换为电荷的光电二极管的形式的光电探测器。第三半导体芯片610可为将通过感测芯片620产生的电荷转换(即，处理)为代表图像的电信号的逻辑芯片。
第三半导体芯片610可包括第一基本层611、第一电路层612、第一过孔613和第一键合焊盘614。第一基本层611可包括硅衬底。第一电路层612可设置在第一基本层611上。第一电路层612可包括集成电路(例如，晶体管)和至少一个互连图案。第一过孔613可穿过第一基本层611，并且可将第一电路层612电连接至第一半导体芯片200和/或第二半导体芯片300。因此，第一半导体芯片200和/或第二半导体芯片300与第三半导体芯片610之间的电路径可相对短。第一键合焊盘614可布置在第三半导体芯片610的上表面上。第三半导体芯片610的上表面可为有源表面。
感测芯片620可布置在第三半导体芯片610上。感测芯片620可包括第二基本层621、第二电路层622、第二过孔623和第二键合焊盘624。第二基本层621可包括硅衬底。第二电路层622可设置在感测芯片620的下部，邻近于第三半导体芯片610。第二电路层622可包括光电二极管(例如，可具有光敏晶体管)和至少一个互连图案的集成电路。至少一个光敏晶体管可构成CMOS。第二键合焊盘624可布置在感测芯片620的下表面上。感测芯片620的下表面可为有源表面。第二键合焊盘624可接触第一键合焊盘614。因此，感测芯片620可通过第一键合焊盘614和第二键合焊盘624电连接至第三半导体芯片610。第二过孔623可延伸穿过感测芯片620的至少一部分。在一些示例中，第二过孔623延伸穿过感测芯片620，以电连接至第三半导体芯片610。在其它示例中，第二过孔623部分地延伸穿过感测芯片620，并且电连接至第三半导体芯片610。
像素阵列区可设置在图像传感器单元600的上部。像素阵列区可包括感测芯片620中的像素区P。在平面图中，像素区P可布置在图像传感器单元600的中心区中。滤色器630和微透镜640可布置在图像传感器单元600的上主表面600a上，并且可设置在每一个像素区P中。像素区P和感测芯片620的集成电路可一起构成像素的阵列。
连接焊盘650可布置在图像传感器单元600的上主表面600a上。连接焊盘650可布置在图像传感器单元600的边缘部分的上主表面600a上。在平面图中，连接焊盘650可与像素阵列区间隔开。连接焊盘650可电连接至感测芯片620的第二过孔623。连接焊盘650可经键合线700连接至衬底焊盘120，即，衬底100的端子。图像传感器单元600可经键合线700电连接至衬底100。
在一些示例中，在图像传感器单元600与第一半导体芯片200和第二半导体芯片300之间设置再分布层500。再分布层500可在模制层400与图像传感器单元600之间延伸。在一些示例中，可在再分布层500与第一半导体芯片200和第二半导体芯片300之间设置粘合层，以可将再分布层500与第一半导体芯片200和第二半导体芯片300牢固地粘合。再分布层500可包括绝缘层510和再分布(布线)图案520。再分布图案520可包括至少一个导电层和导电过孔。再分布层500可电连接至第三半导体芯片610。第一半导体芯片200可通过设置在其与再分布层500之间的第一连接端子230电连接至再分布层500。第二半导体芯片300可通过设置在其与再分布层500之间的第二连接端子330电连接至再分布层500。再分布层500可允许布置第一半导体芯片200和第二半导体芯片300的自由度增加。在一些示例中，第二半导体芯片300不电连接至再分布层500。
保持器810可设置在衬底100上并且可支承透镜800。即，透镜800可布置在保持器810上。透镜800可与图像传感器单元600间隔开，以面对图像传感器单元600。透镜800可将光聚焦在图像传感器单元600的入射表面上。
根据上述任何一个示例的半导体封装件可具有改进的散热效率。
图2和图3示出了根据本发明构思的半导体封装件中的热传递。在图2和图3中，为了清楚起见，省略了上述一些元件。
参照图2，示出了在操作过程中产生热并且将热聚集在图像传感器单元600中的热源HS。热源HS可不限于图2所示的位置。例如，热源HS可位于第三半导体芯片610和感测芯片620中的各个位置。在图像传感器单元600操作时，热可能从热源HS的位置朝着图像传感器单元600的上主表面600a传递。在其中发生这种热传递的情况下，在像素区P中可由于热而产生诸如暗电流的噪声。
如果即使作为伪芯片的第二半导体芯片300未设置在图像传感器单元600下方的空间中，则图像传感器单元600下方的这一空间应该被模制层400填充。模制层400通常具有相对低的导热率，例如，0.88W/mK。因此，图像传感器单元600中的热源HS产生的热不应该通过模制层400消散。
相反，在根据本发明构思的半导体封装件的示例中，第二半导体芯片300布置在本来是图像传感器单元600下方的额外空间中。第二半导体芯片300可包括导热率高于模制层400的导热率的金属或硅。例如，硅的导热率可为149W/mK。因为图像传感器单元600下方的模制层400的一部分主要由第二半导体芯片300替代，因此提高了半导体封装件的散热效率。
根据图3所示的本发明构思的一方面，半导体封装件的散热效率并不特别取决于热源HS的位置。以其中邻近于图像传感器单元600的边缘(外周边部分)布置的热源HS产生热的情况为例进行讨论。其中图像传感器单元600与第一半导体芯片200和第二半导体芯片300重叠的区域与其中图像传感器单元600仅与一个芯片重叠的情况(即，其中未设置第二半导体芯片300的情况)相比相对更大。与其中未设置第二半导体芯片300的后一种情况相比，在热源HS的位置产生的热在前一种情况下可(即，通过根据本发明构思的第一半导体芯片200和第二半导体芯片300)更容易地消散至半导体封装件以外。即使在其中热从在图像传感器单元600的各个位置的热源HS产生的情况下，热也可通过第一半导体芯片200和第二半导体芯片300容易地消散至半导体封装件以外。
另外，半导体封装件可不包括用于将第一半导体芯片200和第二半导体芯片300与图像传感器单元600电连接的额外的中介件或者额外的连接端子(例如，键合线或者焊料球)，但是可包括用于将第一半导体芯片200和第二半导体芯片300与图像传感器单元600电连接的板形衬底(例如，再分布层500)。因此，可最小化图像传感器单元600下面的半导体封装件的一部分的厚度，以使得半导体封装件的尺寸或大小可相应地保持较小，从而可有利于热朝着半导体封装件下方消散。
半导体封装件可通过第一半导体芯片200和第二半导体芯片300消散热，以可防止热传递至像素区P。因此，可防止热在图像传感器单元600中产生噪声，并且可提高图像传感器单元600的图像质量。
另外，在其中第二半导体芯片300是有源芯片的示例中，半导体封装件可具有提高的性能。例如，第二半导体芯片300可为用于增大半导体封装件的存储器容量的存储器芯片。在一些示例中，第二半导体芯片300可为逻辑芯片或者包括电容器(例如，第二半导体芯片300可为芯片电容器)，以改进半导体封装件的功率效率或者信号传输特征。在一些示例中，第二半导体芯片300可包括不止一种以上安装类型的芯片独立于封装件安装在一起的模块。
在一些示例中，第二半导体芯片300可包括用于控制封装件的操作的逻辑电路的一部分。因此，可最小化图像传感器单元600的尺寸或大小，从而可实现相对紧凑的半导体封装件。
图4至图9示出了根据本发明构思的制造诸如上述封装件的半导体封装件的方法的示例。在图4至图9中省略了与上述封装件的元件相同的那些元件，并且为了简明起见将不详细描述它们。下文中，可相对于图1讨论封装件的包括第一半导体芯片200和第二半导体芯片300的上表面和下表面、再分布层500和图像传感器单元600的那部分。
参照图4，可设置图像传感器单元600。例如，第三半导体芯片610可键合至感测芯片620的下表面620b，以形成图像传感器单元600。
可通过在第二基本层621上形成第二电路层622和形成第二键合焊盘624以及在第二基本层621中形成第二过孔623来制造感测芯片620。滤色器630、微透镜640和连接焊盘650可设置在感测芯片620的上表面620a(例如，第二基本层621的上表面)上。可通过在第一基本层611上形成第一电路层612和第一键合焊盘614和在第一基本层611中形成第一过孔613来形成第三半导体芯片610。第一键合焊盘614和第二键合焊盘624包括诸如金属的导电材料。
接着，感测芯片620和第三半导体芯片610可键合至彼此。感测芯片620和第三半导体芯片610可通过直接键合处理键合。例如，将感测芯片620与第三半导体芯片610键合的处理可包括：按照其中第二键合焊盘624与第一键合焊盘614对齐的方式在第三半导体芯片610上设置感测芯片620；在感测芯片620和第三半导体芯片610上执行热处理工艺，以键合第一键合焊盘614和第二键合焊盘624，以使得第三半导体芯片610和感测芯片620键合并电连接至彼此。在一些其中第三半导体芯片610和感测芯片620包括硅的示例中，第三半导体芯片610与感测芯片620之间的界面可在热处理工艺中被氮化或氧化，从而第三半导体芯片610和感测芯片620可键合至彼此。
参照图5，图像传感器单元600可设置在承载衬底900上。感测芯片620的上表面620a可面对承载衬底900。图像传感器单元600可通过承载粘合层910附着于承载衬底900。
接着，可去除第三半导体芯片610的一部分615。例如，第一基本层611可变薄以暴露出第一过孔613。例如，可在第一基本层611的与感测芯片620的下表面620b远离并背对的表面上执行研磨工艺。
参照图6，再分布层500可形成在图像传感器单元600的下主表面600b上。可将在去除其一部分615之后暴露出的第三半导体芯片610的表面称作图像传感器单元600的下主表面600b，并且可将图像传感器单元600的与其下主表面600b相反的另一表面称作其上主表面600a。再分布层500的形成可包括在第三半导体芯片610上形成绝缘层510和再分布图案520。再分布图案520可电连接至第一过孔613。再分布图案520可根据第一半导体芯片200和第二半导体芯片300在下面描述的处理中排列的位置具有各种形状。
参照图7，第一半导体芯片200和第二半导体芯片300可安装在再分布层500上。例如，第一半导体芯片200和第二半导体芯片300可设置在再分布层500的下表面500b上。第一连接端子230可形成在再分布层500与第一半导体芯片200之间，以将第一半导体芯片200电连接至图像传感器单元600。第二连接端子330可位于再分布层500与第二半导体芯片300之间，以将第二半导体芯片300电连接至图像传感器单元600。
参照图8，模制层400可形成在再分布层500上。模制层400可覆盖第一半导体芯片200的侧部200a和第二半导体芯片300的侧部300a和再分布层500。模制层400可不覆盖第一半导体芯片200的下表面200b和第二半导体芯片300的下表面300b。模制层400的侧部(表面)400c可与再分布层500的侧部(表面)500c和图像传感器单元600的侧部(表面)600c基本上共面。可通过上述工艺制造芯片堆叠件10。
参照图9，在倒置芯片堆叠件10之后，芯片堆叠件10可布置在包括衬底焊盘120和外部端子130的衬底100上。此时，第一半导体芯片200的下表面200b和第二半导体芯片300的下表面300b可面朝衬底100。衬底粘合层110可位于衬底100与第一半导体芯片200和第二半导体芯片300之间，以允许第一半导体芯片200和第二半导体芯片300固定在衬底100上。可去除承载衬底900和承载粘合层910，从而暴露出滤色器630、微透镜640和连接焊盘650。然后，可形成键合线700以将连接焊盘650和衬底焊盘120连接。
参照图1，保持器810可设置在衬底100上。保持器810可支承透镜800。透镜800可面对图像传感器单元600，并且与图像传感器单元600间隔开。因此，可通过上述工艺制造半导体封装件。
图10至图14是示出根据本发明构思的批量制造半导体封装件的方法的剖视图。为了简单起见，将不再次详细描述与上面描述的元件和构造相同的一些元件和构造。
参照图10，第一半导体衬底1610和第二半导体衬底1620可键合至彼此。可将多个第三半导体芯片610设置在第一半导体衬底1610中。第一半导体衬底1610可为半导体晶圆衬底。多个感测芯片620可设置在第二半导体衬底1620中。第二半导体衬底1620可为半导体晶圆衬底。当第一半导体衬底1610和第二半导体衬底1620键合时，感测芯片620可分别电连接至第三半导体芯片610。形成感测芯片620和第三半导体芯片610的工艺和键合第一半导体衬底1610和第二半导体衬底1620的工艺可与参照图4描述的形成和键合感测芯片620和第三半导体芯片610的工艺相似。
参照图11，可将第一半导体衬底1610和第二半导体衬底1620倒置，因此，第二半导体衬底1620可设置在承载衬底900上。第二半导体衬底1620可通过承载粘合层910附着于承载衬底900。第一半导体衬底1610可位于承载衬底900上方。
可去除第一半导体衬底1610的一部分。例如，可使第一半导体衬底1610变薄以暴露出第一过孔613。
参照图12，再分布层500可形成在第一半导体衬底1610上，以覆盖第三半导体芯片610。
参照图13，第一半导体芯片200和第二半导体芯片300可安装在再分布层500上。第一半导体芯片200和第二半导体芯片300可通过晶圆上芯片工艺(chip-on-wafer process)形成。例如，多个第一半导体芯片200中的每一个和多个第二半导体芯片300中的每一个可安装在第三半导体芯片610中的每一个上。
参照图14，可在第一半导体芯片200和第二半导体芯片300上形成模制层400。模制层400可与参照图8描述的模制层400基本相同。
可沿着锯切线SL锯切第一半导体衬底1610、第二半导体衬底1620和模制层400。芯片堆叠件10可通过锯切工艺彼此单独地分离。芯片堆叠件10中的每一个可与参照图8示出和描述的芯片堆叠件10相同。例如，芯片堆叠件10各自可包括第一半导体芯片200和第二半导体芯片300、模制层400、第三半导体芯片610和感测芯片620。由于芯片堆叠件10通过锯切工艺彼此分离，因此在芯片堆叠件10中的每一个中，模制层400的宽度可基本等于再分布层500的宽度和图像传感器单元600的宽度。
然后，如图9所示，在将芯片堆叠件10安装在衬底100上之后，可将保持器810和透镜800设置在衬底100上，从而完成制造半导体封装件。
虽然已经参照本发明构思的示例具体示出和描述了本发明构思，但是本领域普通技术人员应该理解，在不脱离由随附的权利要求限定的本发明构思的精神和范围的情况下，可对所公开的示例作出各种形式和细节上的改变。

Claims (19)

1.一种半导体封装件，包括：
衬底；
第一半导体芯片，其位于所述衬底上；
第二半导体芯片，其位于所述衬底上并且与所述第一半导体芯片横向间隔开；
模制层，其位于所述衬底上并且覆盖所述第一半导体芯片的侧部和所述第二半导体芯片的侧部；以及
图像传感器单元，其位于所述第一半导体芯片、所述第二半导体芯片和所述模制层上，所述图像传感器单元包括电连接至所述第一半导体芯片的电子图像传感器，
其中，所述模制层覆盖所述第一半导体芯片和所述第二半导体芯片的上表面，并且不覆盖所述第一半导体芯片和所述第二半导体芯片的下表面，所述第一半导体芯片和所述第二半导体芯片的上表面比所述第一半导体芯片和所述第二半导体芯片的下表面更靠近所述图像传感器单元，所述第二半导体芯片的导热率高于所述模制层的导热率。
2.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片是存储器芯片，
所述第二半导体芯片是由单层硅或金属构成的伪芯片。
3.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片是存储器芯片，
所述第二半导体芯片是存储器芯片、逻辑芯片、芯片电容器或包括选自由存储器、逻辑电路和电容器构成的组中的至少两个组件的组合的芯片，并且
所述第二半导体芯片电连接至所述图像传感器单元的电子图像传感器。
4.根据权利要求1所述的半导体封装件，其中，所述模制层的侧部与所述图像传感器单元的侧部实质上共面。
5.根据权利要求1所述的半导体封装件，其中，所述图像传感器单元包括：
第三半导体芯片；以及
堆叠在所述第三半导体芯片上的感测芯片，
所述感测芯片包括光电探测器，并且
所述第三半导体芯片具有电连接至所述第一半导体芯片的逻辑电路。
6.根据权利要求1所述的半导体封装件，其中，在所述半导体封装件的平面图中，所述图像传感器单元与所述第一半导体芯片和所述第二半导体芯片重叠。
7.根据权利要求1所述的半导体封装件，还包括介于所述模制层与所述图像传感器单元之间的再分布层，所述再分布层电连接至所述图像传感器单元的电子图像传感器。
8.根据权利要求7所述的半导体封装件，其中，所述第一半导体芯片具有面朝所述图像传感器单元并且电连接至所述再分布层的有源表面。
9.根据权利要求1所述的半导体封装件，还包括：
连接焊盘，其位于所述图像传感器单元的上表面上；以及
键合线，其将所述连接焊盘电连接至所述衬底的端子。
10.一种半导体封装件，包括：
图像传感器单元，其具有相对的第一主表面和第二主表面，所述图像传感器单元包括其第二主表面上的像素区和与所述像素区操作性地关联以感测入射于所述像素区上的光的电子光电探测器；
第一下半导体芯片和第二下半导体芯片，位于所述图像传感器单元的第一主表面上，其中，所述第一下半导体芯片和所述第二下半导体芯片的宽度之和小于所述图像传感器单元的宽度，宽度是在平行于所述图像传感器单元的第一主表面和第二主表面的方向上测量的尺寸；
模制层，其位于所述图像传感器单元的第一主表面上，并且覆盖所述第一下半导体芯片的侧部和所述第二下半导体芯片的侧部；以及
连接端子，其介于所述图像传感器单元的第一主表面与所述第一下半导体芯片之间，所述连接端子将所述第一下半导体芯片电连接至所述图像传感器单元，
其中，所述模制层覆盖所述第一下半导体芯片和所述第二下半导体芯片的上表面，并且不覆盖所述第一下半导体芯片和所述第二下半导体芯片的下表面，所述第一下半导体芯片和所述第二下半导体芯片的上表面比所述第一下半导体芯片和所述第二下半导体芯片的下表面更靠近所述图像传感器单元，所述第二下半导体芯片的导热率高于所述模制层的导热率。
11.根据权利要求10所述的半导体封装件，其中，所述第一下半导体芯片是存储器芯片，
所述第二下半导体芯片是由单层硅或金属构成的伪芯片。
12.根据权利要求10所述的半导体封装件，其中，所述第一下半导体芯片是存储器芯片，
所述第二下半导体芯片包括存储器芯片、逻辑芯片、电容器或包括选自由存储器、逻辑电路和电容器构成的组中的至少两个组件的组合的芯片，并且
所述第二下半导体芯片电连接至所述图像传感器单元。
13.根据权利要求10所述的半导体封装件，还包括：
连接焊盘，其位于所述图像传感器单元的第二主表面上；
衬底，其位于所述第一下半导体芯片和所述第二下半导体芯片的下表面上，所述下表面与所述第一下半导体芯片和所述第二下半导体芯片的面对所述图像传感器单元的第一主表面的上表面相对；以及
键合线，其将所述连接焊盘电连接至所述衬底的端子。
14.根据权利要求10所述的半导体封装件，其中，所述图像传感器单元还包括：
上半导体芯片，其包括逻辑电路；以及
感测芯片，其位于所述上半导体芯片上，并且包括所述电子光电探测器。
15.根据权利要求14所述的半导体封装件，其中，所述上半导体芯片包括电连接至所述逻辑电路的过孔，并且
所述过孔连接至所述连接端子。
16.一种半导体封装件，其包括：
衬底；
第一芯片，其布置在所述衬底上；
第二芯片，其布置在所述衬底上，与所述第一芯片在第一方向上横向间隔开；
模制层，其包封所述衬底上的所述第一芯片和所述第二芯片；
第三芯片，其布置在所述模制层上，并且整体上覆盖所述第一芯片和所述第二芯片；以及
像素阵列，其布置在所述第三芯片上，
其中，所述第一芯片是存储器芯片，
所述第二芯片是有源芯片、无源芯片和伪芯片之一，并且
所述第三芯片是电连接至所述像素阵列和所述存储器芯片的逻辑芯片，
其中，所述模制层覆盖所述第一芯片和所述第二芯片的上表面并且不覆盖所述第一芯片和所述第二芯片的下表面，所述第一芯片和所述第二芯片的上表面比所述第一芯片和所述第二芯片的下表面更靠近所述第三芯片，所述第二芯片的导热率高于所述模制层的导热率。
17.根据权利要求16所述的半导体封装件，其中，所述第二芯片包括集成电路和无源电子组件中的至少一个，并且电连接至所述逻辑芯片。
18.根据权利要求16所述的半导体封装件，其中，所述第二芯片是在所述半导体封装件中不执行电子操作的伪芯片。
19.根据权利要求16所述的半导体封装件，其中，所述像素阵列包括布置在所述第三芯片上并且包括光敏晶体管集成电路的感测芯片以及布置在所述感测芯片上的滤色器和微透镜。
CN201810310753.0A 2017-04-18 2018-04-09 半导体封装件 Active CN108735770B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2017-0049704 2017-04-18
KR1020170049704A KR102275684B1 (ko) 2017-04-18 2017-04-18 반도체 패키지

Publications (2)

Publication Number Publication Date
CN108735770A CN108735770A (zh) 2018-11-02
CN108735770B true CN108735770B (zh) 2024-02-23

Family

ID=63790903

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810310753.0A Active CN108735770B (zh) 2017-04-18 2018-04-09 半导体封装件

Country Status (3)

Country Link
US (3) US10510737B2 (zh)
KR (1) KR102275684B1 (zh)
CN (1) CN108735770B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102605617B1 (ko) 2016-11-10 2023-11-23 삼성전자주식회사 적층 반도체 패키지
TW202315106A (zh) * 2017-10-30 2023-04-01 日商索尼半導體解決方案公司 固體攝像裝置及電子機器
KR102511008B1 (ko) * 2018-01-11 2023-03-17 삼성전자주식회사 반도체 패키지
JP2019165312A (ja) * 2018-03-19 2019-09-26 ソニーセミコンダクタソリューションズ株式会社 撮像装置および電子機器
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
US10707257B2 (en) * 2018-08-14 2020-07-07 Semiconductor Components Industries, Llc Multi-chip packaging structure for an image sensor
TW202101744A (zh) * 2018-12-20 2021-01-01 日商索尼半導體解決方案公司 背面照射型固體攝像裝置、背面照射型固體攝像裝置之製造方法、攝像裝置及電子機器
US10892250B2 (en) * 2018-12-21 2021-01-12 Powertech Technology Inc. Stacked package structure with encapsulation and redistribution layer and fabricating method thereof
CN111627939B (zh) * 2019-02-27 2023-04-18 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
CN111627941B (zh) * 2019-02-27 2023-04-18 中芯集成电路（宁波）有限公司 Cmos图像传感器封装模块及其形成方法、摄像装置
US11650430B2 (en) * 2019-04-19 2023-05-16 Tdk Taiwan Corp. Method of adjusting optical system
SG10201908828WA (en) 2019-09-23 2021-04-29 Apple Inc Embedded Packaging Concepts for Integration of ASICs and Optical Components
US11064615B2 (en) * 2019-09-30 2021-07-13 Texas Instruments Incorporated Wafer level bump stack for chip scale package
TWI701777B (zh) * 2019-10-22 2020-08-11 財團法人工業技術研究院 影像感測器封裝件及其製造方法
US11217144B2 (en) 2019-11-06 2022-01-04 Silicon Works Co., Ltd. Driver integrated circuit and display device including the same
CN212587504U (zh) * 2020-06-09 2021-02-23 深圳市大疆创新科技有限公司 半导体封装结构
KR20220057116A (ko) * 2020-10-29 2022-05-09 삼성전자주식회사 반도체 패키지
KR20220059722A (ko) 2020-11-03 2022-05-10 삼성전자주식회사 Bs-pdn 구조를 가진 집적회로 칩
US20230213715A1 (en) * 2022-01-03 2023-07-06 Apple Inc. Technologies for Increased Volumetric and Functional Efficiencies of Optical Packages

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779219A (zh) * 2014-01-15 2015-07-15 三星电子株式会社 电子器件、半导体封装件及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100442698B1 (ko) * 2002-06-19 2004-08-02 삼성전자주식회사 촬상용 반도체 장치 및 그 제조방법
US7005310B2 (en) * 2002-08-14 2006-02-28 Renesas Technology Corporation Manufacturing method of solid-state image sensing device
US7361989B1 (en) * 2006-09-26 2008-04-22 International Business Machines Corporation Stacked imager package
KR101070921B1 (ko) * 2006-10-19 2011-10-06 삼성테크윈 주식회사 이미지 센서용 칩 패키지 및 그 제조방법
TWI332790B (en) * 2007-06-13 2010-11-01 Ind Tech Res Inst Image sensor module with a three-dimensional dies-stacking structure
US20120281113A1 (en) 2011-05-06 2012-11-08 Raytheon Company USING A MULTI-CHIP SYSTEM IN A PACKAGE (MCSiP) IN IMAGING APPLICATIONS TO YIELD A LOW COST, SMALL SIZE CAMERA ON A CHIP
JP2012242587A (ja) 2011-05-19 2012-12-10 Toshiba Corp カメラモジュールおよびカメラモジュールの製造方法
JP5791571B2 (ja) 2011-08-02 2015-10-07 キヤノン株式会社 撮像素子及び撮像装置
US8497536B2 (en) 2011-09-16 2013-07-30 Omnivision Technologies, Inc. Dual-facing camera assembly
US9607971B2 (en) 2012-06-04 2017-03-28 Sony Corporation Semiconductor device and sensing system
JP2014099582A (ja) 2012-10-18 2014-05-29 Sony Corp 固体撮像装置
US9318640B2 (en) 2013-03-15 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
JP2016134587A (ja) 2015-01-22 2016-07-25 ソニー株式会社 固体撮像装置、及び、電子機器
JP6693068B2 (ja) 2015-03-12 2020-05-13 ソニー株式会社 固体撮像装置および製造方法、並びに電子機器
US9601471B2 (en) * 2015-04-23 2017-03-21 Apple Inc. Three layer stack structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104779219A (zh) * 2014-01-15 2015-07-15 三星电子株式会社 电子器件、半导体封装件及其制造方法

Also Published As

Publication number Publication date
KR102275684B1 (ko) 2021-07-13
US11600608B2 (en) 2023-03-07
US10510737B2 (en) 2019-12-17
US20210202462A1 (en) 2021-07-01
CN108735770A (zh) 2018-11-02
US20190348407A1 (en) 2019-11-14
US20180301443A1 (en) 2018-10-18
KR20180117239A (ko) 2018-10-29
US10985152B2 (en) 2021-04-20

Similar Documents

Publication Publication Date Title
CN108735770B (zh) 半导体封装件
US11482554B2 (en) Semiconductor package and method of fabricating the same
US10008533B2 (en) Semiconductor package
CN110911427B (zh) 半导体封装件及其制造方法
US7361989B1 (en) Stacked imager package
US7411306B2 (en) Packaging structure and method of an image sensor module
US11152416B2 (en) Semiconductor package including a redistribution line
US7084474B2 (en) Photosensitive semiconductor package and method for fabricating the same
JP2008130738A (ja) 固体撮像素子
JP2012094882A (ja) ウェハーレベルのイメージセンサモジュールの製造方法
US11380726B2 (en) Sensor device
KR100652955B1 (ko) 이미지 센서 패키지 제조방법
US11955499B2 (en) Image sensor package including glass substrate and a plurality of redistribution layers disposed below the glass substrate and spaced apart from each other by a predetermined distance
KR101232886B1 (ko) 재배선용 기판을 이용한 반도체 패키지 및 그 제조 방법
KR20210080718A (ko) 반도체 패키지
KR20240013563A (ko) 이미지 센서 칩 및 이를 포함하는 반도체 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant