CN108735146B - 像素电路 - Google Patents
像素电路 Download PDFInfo
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Abstract
一种像素电路包括发光元件、第一至第三晶体管、第一至第二电容及电压设定电路。发光元件接收系统低电压。第一晶体管接收系统高电压并受控于发光信号。第二晶体管耦接于第一晶体管及发光元件间。第一电容耦接第二晶体管。第二电容耦接于第一电容与第一晶体管间。电压设定电路接收第一至第二扫描信号、源极驱动信号及数据电压,以依据第一至第二扫描信号对第一电容进行电荷消除且接着依据源极驱动信号写入数据电压至第一电容。第三晶体管受控于第二扫描信号且接收第一参考电压。
Description
技术领域
本发明涉及一种显示装置,且特别涉及一种像素电路。
背景技术
随着电子技术的进步,显示装置已成为人们生活中不可或缺的工具。为提供良好的人机界面,高品质的显示面板已成为显示装置中必要的设备。
在显示装置中,由于显示面板所呈现的显示画面容易受到像素电路中的驱动晶体管的临界电压(Threshold Voltage)影响,导致显示画面的品质降低。因此,显示装置会针对驱动晶体管的临界电压进行补偿,以进一步降低临界电压对于显示画面的影响。
另一方面,在高分辨率的显示面板中,像素电路执行数据写入动作的时间长度会缩短,也就是说,像素电路对临界电压进行补偿的时间长度会缩短,使得像素电路对于临界电压的补偿效果将会受到影响。因此,如何改善临界电压对于显示画面的品质影响,将是本领域相关技术人员重要的课题。
发明内容
本发明提供一种像素电路,可以划分像素电路操作于画面期间中的电压补偿期间及数据写入期间,以使临界电压的补偿时间长度可以被调整,并且此补偿时间长度可以不受数据写入时间长度的影响,进而改善显示面板所呈现的显示画面的品质。
本发明的像素电路包括发光元件、第一至第三晶体管、第一至第二电容以及电压设定电路。发光元件具有阳极及接收系统低电压的阴极。第一晶体管具有接收系统高电压的第一端、接收发光信号的控制端以及第二端。第二晶体管具有耦接第一晶体管的第一端、控制端以及耦接发光元件的第二端。第一电容具有第一端及耦接第二晶体管的第二端。第二电容具有耦接第一电容的第一端及耦接第一晶体管的第二端。电压设定电路耦接第一电容的第一端及第二端,并且接收第一至第二扫描信号、源极驱动信号及数据电压,以依据第一扫描信号及第二扫描信号对第一电容进行电荷消除且接着依据源极驱动信号写入数据电压至第一电容。第三晶体管具有耦接第二晶体管的第一端、耦接第二扫描信号的控制端以及接收第一参考电压的第二端。
基于上述,本发明实施例所述像素电路中的电压设定电路可以依据第一扫描信号及第二扫描信号来对第一电容进行电荷消除,并且可以依据源极驱动信号来将数据电压写入至第一电容。如此一来,像素电路对于补偿临界电压时的时间长度,将不受数据写入至第一电容时的时间长度影响,借此改善显示面板所呈现的显示画面的品质。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合说明书附图作详细说明如下。
附图说明
图1是依照本发明一实施例的像素电路的电路图。
图2是依照本发明一实施例的像素电路的波形示意图。
图3是依照本发明另一实施例的像素电路的电路图。
图4是依照本发明再一实施例的像素电路的电路图。
图5是依照本发明一实施例的像素电路的另一种波形示意图。
附图标记说明:
100、300、400:像素电路
110、310、410:电压设定电路
LED:发光元件
C1~C2:电容
M1~M10:晶体管
Vref1~Vref2:参考电压
Vdata:数据电压
OVDD:系统高电压
OVSS:系统低电压
S1:第一扫描信号
S1[n-1]:先前第一扫描信号
S2:第二扫描信号
SD:源极驱动信号
EM:发光信号
NA~ND:节点
Id:导通电流
TFR:像素期间
Tr:电压重置期间
Tc:电压补偿期间
Td:数据写入期间
Te:发光期间
具体实施方式
图1是依照本发明一实施例的像素电路100的电路图。请参照图1,在本实施例中,像素电路100包括发光元件LED、第一至第三晶体管M1~M3、第十晶体管M10、第一至第二电容C1~C2以及电压设定电路110。电压设定电路110耦接至第一电容C1的第一端及第二端及第二电容C2的第一端,并且电压设定电路110可以接收第一扫描信号S1、第二扫描信号S2、源极驱动信号SD以及数据电压Vdata。并且,电压设定电路110可以包括第四至第六晶体管M4~M6,并且本实施例的第一至第六晶体管M1~M6及第十晶体管M10是以P型晶体管为例,但本发明实施例不以此为限。
在本实施例中,发光元件LED具有阳极及接收系统低电压OVSS的阴极。其中,本实施例的发光元件LED可以例如是有机发光二极管及微型发光二极管的其中之一,但本发明实施例不以此为限。另一方面,第一晶体管M1的源极(对应于第一端)接收系统高电压OVDD,第一晶体管M1的栅极(对应于控制端)接收发光信号EM,第一晶体管M1的漏极(对应于第二端)耦接至第二电容C2的第二端。第二晶体管M2的源极(对应于第一端)耦接至第一晶体管M1的漏极,第二晶体管M2的栅极(对应于控制端)耦接至第一电容C1的第二端。第三晶体管M3的源极(对应于第一端)耦接至第二晶体管M2的漏极(对应于第二端),第三晶体管M3栅极(对应于控制端)接收第二扫描信号S2,第三晶体管M3的漏极(对应于第二端)接收第一参考电压Vref1。第十晶体管M10的源极(对应于第一端)耦接至第二晶体管M2的漏极,第十晶体管M10的栅极(对应于控制端)接收发光信号EM,第十晶体管M10的漏极(对应于第二端)耦接至发光元件LED的阳极。
另一方面,在本实施例的电压设定电路110中,第四晶体管M4的源极(对应于第一端)接收第二参考电压Vref2,第四晶体管M4的栅极(对应于控制端)接收第二扫描信号S2,第四晶体管M4的漏极(对应于第二端)耦接至第一电容C1的第一端。第五晶体管M5的源极(对应于第一端)接收第二参考电压Vref2,第五晶体管M5的栅极(对应于控制端)接收第一扫描信号S1,第五晶体管M5的漏极(对应于第二端)耦接至第一电容C1的第二端。第六晶体管M6的源极(对应于第一端)接收数据电压Vdata,第六晶体管M6的栅极(对应于控制端)接收源极驱动信号SD,第六晶体管M6的漏极(对应于第二端)耦接至第一电容C1的第一端及第二电容C2的第一端。其中,本实施例的第二参考电压Vref2可以大于第一参考电压Vref1,并且第一参考电压Vref1可以小于系统低电压OVSS与发光元件LED的点亮临界电压的总和电压,但本发明实施例不以此为限。
值得一提的是,在本实施例中,电压设定电路110可以依据第一扫描信号S1及第二扫描信号S2来对第一电容C1进行电荷消除,并且电压设定电路110可以依据源极驱动信号SD来将数据电压Vdata写入至第一电容C1。换句话说,电压设定电路110可以依据上述的第一扫描信号S1、第二扫描信号S2、源极驱动信号SD,来对第一电容C1进行重置及数据写入的相关动作。
顺带一提的是,在本发明实施例中,上述的第一扫描信号S1及第二扫描信号S2可以例如是由显示面板(未示出)中的多条栅极线(Gate Line)的其中之一来传送。另外,数据电压Vdata可以例如由显示面板(未示出)中的多条数据线(Data Line)的其中之一来传送。并且,显示面板(未示出)中的多个像素(Pixel)是以矩阵排列,并且配置于数据线与栅极线的交错处,以通过相对应的栅极线与数据线来控制像素电路(例如是像素电路100)进行电路操作。
图2是依照本发明一实施例的像素电路的波形示意图。请参照图2,在本实施例中,像素电路100的一个像素期间TFR可以区分为电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te,并且电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te彼此不相互重叠。其中,电压补偿期间Tc是位于电压重置期间Tr之后,数据写入期间Td是位于电压补偿期间Tc之后,并且发光期间Te是位于数据写入期间Td之后。举例来说,在像素期间TFR中,像素电路100的电压重置期间Tr与电压补偿期间Tc可以视为像素电路100的设定时间;像素电路100的数据写入期间Td可以视为像素电路100的数据写入时间;像素电路100的发光期间Te可以视为像素电路100的显示时间。
请同时参照图1及图2。详细来说,当像素电路100操作于电压重置期间Tr时,可以设定第一扫描信号S1、第二扫描信号S2以及发光信号EM为致能(使能)(例如为低电压电平),以使第一至第五晶体管M1~M5以及第十晶体管M10可以被导通,并且设定源极驱动信号SD为禁能(例如为高电压电平),以使第六晶体管M6可以被断开,进而使得数据电压Vdata无法被传送至像素电路100中。在此情况下,第一电容C1的第一端(亦即节点NA)与第二端(亦即节点NB)上的电压值可以为第二参考电压Vref2,借此消除预先残留于第一电容C1中的电荷。
另一方面,由于第一晶体管M1为导通状态,因此,第二晶体管M2的第一端(亦即节点NC)可以接收系统高电压OVDD,以使得节点NC上的电压值为系统高电压OVDD的电压值。由于第三晶体管M3及第十晶体管M10皆为导通状态,因此,节点ND上的电压值可以放电至第一参考电压Vref1。换言之,第一参考电压Vref1与系统低电压OVSS之间的电压差值会小于发光元件的临界电压值,因此发光元件在此阶段不会发光。
当像素电路100操作于电压补偿期间Tc时,可以设定第一扫描信号S1及第二扫描信号S2维持在致能(例如为低电压电平)状态,以使第二至第五晶体管M2~M5可以持续被导通,并且设定源极驱动信号SD及发光信号EM为禁能(例如为高电压电平),以使第一晶体管M1、第六晶体管M6以及第十晶体管M10可以被断开,进而使得数据电压Vdata持续无法被传送至像素电路100中。
在此情况下,节点NA、NB上的电压值可以持续为第二参考电压Vref2的电压值,并且可以持续重置第一电容C1中所存储的数据状态。此外,由于第一晶体管M1为断开状态,因此,节点NC无法接收到系统高电压OVDD,使得节点NC上的电压值可以由原先的系统高电压OVDD的电压值(亦即像素电路100操作于电压重置期间Tr时,节点NC上的电压值),放电至第二参考电压Vref2与第二晶体管M2中的临界电压的总和电压值。
因此,第二电容C2会存储第二晶体管M2中的临界电压,换句话说,当像素电路100操作于电压补偿期间Tc时,像素电路100可以针对所述临界电压来进行补偿。除此之外,由于第十晶体管M10亦为断开状态,因此,节点ND上的电压值可以持续维持于第一参考电压Vref1的电压值,并且使发光元件LED持续被断开而无法被点亮。
另一方面,当像素电路100操作于数据写入期间Td时,可以设定第一扫描信号S1及源极驱动信号SD为致能(例如为低电压电平),以使第二晶体管M2、第五晶体管M5以及第六晶体管M6可以被导通,进而使得数据电压Vdata可以被传送至像素电路100中。并且设定第二扫描信号S2及发光信号EM为禁能(例如为高电压电平),以使第一晶体管M1、第三至第四晶体管M3~M4以及第十晶体管M10可以被断开,进而使得节点NA可以接收数据电压Vdata。
在此情况下,节点NA上的电压值可以为数据电压Vdata的电压值,并且节点NB上的电压值可以持续为第二参考电压Vref2的电压值。值得一提的是,由于第一晶体管M1为断开状态,因此,节点NC无法接收到系统高电压OVDD,使得节点NC上的电压值可以由原先的第二参考电压Vref2与第二晶体管M2中的临界电压的总和电压值(亦即像素电路100操作于电压补偿期间Tc时,节点NC上的电压值),调整为数据电压Vdata与第二晶体管M2中的临界电压的总和电压值,因此,第二电容C2仍存储第二晶体管M2中的临界电压。
具体来说,当像素电路100操作于数据写入期间Td时,像素电路100可以通过致能(例如为低电压电平)源极驱动信号SD,以使第六晶体管M6可以被导通,进而使得数据电压Vdata可以写入至像素电路100中,并且利用第一电容C1来存储写入数据电压Vdata与第二参考电压Vref2之间的压差。除此之外,由于第十晶体管M10为断开状态,因此,节点ND上的电压值可以持续维持于第一参考电压Vref1的电压值,并且使发光元件LED持续被断开而无法被点亮。
现有像素补偿电路多为临界电压补偿与数据写入为同一期间进行,但当显示面板的分辨率越高时,其每一列像素(pixel row)所被分配到的数据写入时间会越短,导致临界电压补偿的时间也会越短,使得像素补偿电路补偿临界电压的效果下降,显示面板依然会面临亮度不均的问题。
值得注意的是,像素电路100的电压补偿期间Tc与数据写入期间Td并不彼此重叠(overlap),因此电压补偿期间Tc的时间长度并不会受限于数据写入期间Td的时间长度,亦即,电压补偿期间Tc的时间长度不会受限于显示面板的分辨率,而可以由设计者自由调整电压补偿期间Tc的长度,使得像素电路100无论是应用于低分辨率或是高分辨率的面板,都可以得到最佳的临界电压补偿效果,以维持面板亮度的均匀性。
另一方面,当像素电路100操作于发光期间Te时,可以设定第一扫描信号S1、第二扫描信号S2以及源极驱动信号SD为禁能(例如为高电压电平),以使第三至第六晶体管M3~M6可以被断开,进而使得数据电压Vdata无法被传送至像素电路100中,并且节点NA、NB皆为浮接状态。此外,可以设定发光信号EM为致能(例如为低电压电平),以使第一至第二晶体管M1~M2以及第十晶体管M10可以被导通。
具体来说,当像素电路100操作于发光期间Te时,由于第一至第二晶体管M1~M2以及第十晶体管M10皆为导通的状态下,使得系统高电压OVDD至系统低电压OVSS之间可以形成一导通路径。并且,第二晶体管M2的导通程度涉及第一至第二电容C1~C2的跨压的总和,像素电路100中流经发光元件LED的导通电流Id是相关于数据电压Vdata与第二参考电压Vref2,使得发光元件LED可以对应数据电压Vdata被点亮。
依据上述,当本实施例的像素电路100操作于电压重置期间Tr及电压补偿期间Tc时,电压设定电路110可以依据第一扫描信号S1及第二扫描信号S2来对第一电容C1进行电荷消除及重置,其中,当像素电路100操作于电压补偿期间Tc时,像素电路100可以更进一步的利用第二电容C2来存储第二晶体管M2中的临界电压,借此针对所述临界电压来进行补偿。除此之外,当像素电路100操作于数据写入期间Td时,电压设定电路110可以依据源极驱动信号SD来将数据电压Vdata写入至第一电容C1,以使第一电容C1可以存储数据电压Vdata与第二参考电压Vref2的压差。如此一来,本实施例的像素电路100对于补偿临界电压时的时间长度,将不受数据写入至第一电容C1时的时间长度影响,借此改善显示面板(未示出)所呈现的显示画面的品质。
图3是依照本发明另一实施例的像素电路300的电路图。请参照图1及图3,像素电路300大致相同于像素电路100,其不同之处在于电压设定电路310,其中相同或相似元件使用相同或相似标号。在本实施例中,电压设定电路310可以包括第七至第九晶体管M7~M9,并且本实施例的第七至第九晶体管M7~M9同样是以P型晶体管为例,但本发明实施例不以此为限。
在本实施例的电压设定电路310中,第七晶体管M7的源极(对应于第一端)接收第二参考电压Vref2,第七晶体管M7的栅极(对应于控制端)接收第一扫描信号S1,第七晶体管M7的的漏极(对应于第二端)耦接至第一电容C1的第一端。第八晶体管M8的源极(对应于第一端)接收第二参考电压Vref2,第八晶体管M8的栅极(对应于控制端)接收第二扫描信号S2,第八晶体管M8的漏极(对应于第二端)耦接至第一电容C1的第二端。第九晶体管M9的源极(对应于第一端)耦接至第一电容C1的第二端,第九晶体管M9的栅极(对应于控制端)接收源极驱动信号SD,第九晶体管M9的漏极(对应于第二端)接收数据电压Vdata。
请参照图2及图3,本实施例的第九晶体管M9的功能是相似于像素电路100中的第六晶体管M6,亦即第九晶体管M9同样是用于决定数据电压Vdata是否可以传送至像素电路300中,以使第一电容C1可以存储第二参考电压Vref2与数据电压Vdata之间的压差。此外,在本实施例中,像素电路300操作于电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te时的作动关系,可参照像素电路100操作于电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te时的作动关系,在此恕不多赘述。
图4是依照本发明再一实施例的像素电路400的电路图。请参照图1及图4,像素电路400大致相同于像素电路100,其不同之处在于像素电路400省略第十晶体管M10,其中相同或相似元件使用相同或相似标号。关于像素电路400操作于电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te时的相关作动关系,可参照像素电路100操作于电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te时的作动关系,在此恕不多赘述。此时,无论第二晶体管M2中的载子迁移率(Mobility)是高或低,由于节点NC会对应地变动,因此发光元件LED的发光程度会自动平衡。需注意到的是,由于在图1及图3的实施例中,像素电路100及像素电路300中皆具有第十晶体管M10,在此情况下,第三晶体管M3的控制端可以耦接至第一扫描信号S1或第二扫描信号S2。举例来说,若第三晶体管M3的控制端耦接至第一扫描信号S1时,则在数据写入后,可以因应各像素间第二晶体管M2载子迁移率的不同,而相对应的调整各像素间节点NC的电压。另一方面,若第三晶体管M3的控制端耦接至第二扫描信号S2时,则在数据写入后,节点NC上的电压值不会因各像素间第二晶体管M2载子迁移率的不同而相对应的被调整。因此,不同于图1及图3的第三晶体管M3的控制端皆耦接至第二扫描信号S2,在图4的实施例中,第三晶体管M3的控制端可以耦接至第一扫描信号S1。
图5是依照本发明一实施例的像素电路100的另一种波形示意图。请参照图1及图5,在本实施例中,像素电路100的一个像素期间TFR同样可以区分为电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te,并且电压重置期间Tr、电压补偿期间Tc、数据写入期间Td以及发光期间Te彼此不相互重叠。其不同于图2之处在于未使用第二扫描信号S2。详细来说,本实施例的像素电路100可以配置于显示面板(未绘制)中的一像素列(未绘制)中,并且第二扫描信号S2可以为提供至一先前像素列(未绘制)的先前第一扫描信号S1[n-1],其中n为引导数。如此一来,本实施例的像素电路100仅需要通过第一扫描信号S1来控制像素电路100中的第一至第五晶体管M1~M5的导通状态,借此降低所需扫描线的数量。
综上所述,本发明所述像素电路操作于电压重置及电压补偿期间时,像素电路中的电压设定电路可以依据第一扫描信号及第二扫描信号来对第一电容进行电荷消除,并且当像素电路操作于数据写入期间时,所述电压设定电路可以依据源极驱动信号来将数据电压写入至第一电容。如此一来,像素电路对于补偿临界电压时的时间长度,将不受数据写入至第一电容时的时间长度影响,借此改善显示面板所呈现的显示画面的品质。
虽然本发明已以实施例公开如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的精神和范围内,当可作些许的变动与润饰,故本发明的保护范围当视权利要求所界定者为准。
Claims (11)
1.一种像素电路,包括:
一发光元件,具有一阳极及接收一系统低电压的一阴极;
一第一晶体管,具有接收一系统高电压的一第一端、接收一发光信号的一控制端、以及一第二端;
一第二晶体管,具有耦接该第一晶体管的该第二端的一第一端、一控制端、以及耦接该发光元件的该阳极的一第二端;
一第一电容,具有一第一端及耦接该第二晶体管的该控制端的一第二端;
一第二电容,具有耦接该第一电容的该第一端的一第一端及耦接该第一晶体管的该第二端的一第二端;
一电压设定电路,耦接该第一电容的该第一端及该第二端,并且接收一第一扫描信号、一第二扫描信号、一源极驱动信号及一数据电压,以依据该第一扫描信号及该第二扫描信号对该第一电容进行电荷消除且接着依据该源极驱动信号写入该数据电压至该第一电容;以及
一第三晶体管,具有耦接该第二晶体管的该第二端的一第一端、耦接该第一扫描信号的一控制端、以及接收一第一参考电压的一第二端,
其中该电压设定电路包括:
一第四晶体管,具有接收一第二参考电压的一第一端、接收该第二扫描信号的一控制端、以及耦接该第一电容的该第一端的一第二端;
一第五晶体管,具有接收该第二参考电压的一第一端、接收该第一扫描信号的一控制端、以及耦接该第一电容的该第二端的一第二端;以及
一第六晶体管,具有接收该数据电压的一第一端、接收该源极驱动信号的一控制端、以及耦接该第一电容的该第一端的一第二端。
2.如权利要求1所述的像素电路,其中该第二参考电压大于该第一参考电压。
3.一种像素电路,包括:
一发光元件,具有一阳极及接收一系统低电压的一阴极;
一第一晶体管,具有接收一系统高电压的一第一端、接收一发光信号的一控制端、以及一第二端;
一第二晶体管,具有耦接该第一晶体管的该第二端的一第一端、一控制端、以及耦接该发光元件的该阳极的一第二端;
一第一电容,具有一第一端及耦接该第二晶体管的该控制端的一第二端;
一第二电容,具有耦接该第一电容的该第一端的一第一端及耦接该第一晶体管的该第二端的一第二端;
一电压设定电路,耦接该第一电容的该第一端及该第二端,并且接收一第一扫描信号、一第二扫描信号、一源极驱动信号及一数据电压,以依据该第一扫描信号及该第二扫描信号对该第一电容进行电荷消除且接着依据该源极驱动信号写入该数据电压至该第一电容;以及
一第三晶体管,具有耦接该第二晶体管的该第二端的一第一端、耦接
该第一扫描信号的一控制端、以及接收一第一参考电压的一第二端,
其中该电压设定电路包括:
一第七晶体管,具有接收一第二参考电压的一第一端、接收该第一扫描信号的一控制端、以及耦接该第一电容的该第一端的一第二端;
一第八晶体管,具有接收该第二参考电压的一第一端、接收该第二扫描信号的一控制端、以及耦接该第一电容的该第二端的一第二端;以及
一第九晶体管,具有耦接该第一电容的该第二端的一第一端、接收该源极驱动信号的一控制端、以及接收该数据电压的一第二端。
4.如权利要求1或3所述的像素电路,还包括:
一第十晶体管,具有耦接该第二晶体管的该第二端的一第一端、接收该发光信号的一控制端、以及耦接该发光元件的该阳极的一第二端。
5.如权利要求1或3所述的像素电路,其中该像素电路配置于一像素列中,并且该第二扫描信号为提供至一先前像素列的一先前第一扫描信号。
6.如权利要求1或3所述的像素电路,其中驱动该像素电路的一画面期间包括一电压重置期间、一电压补偿期间、一数据写入期间及一发光期间。
7.如权利要求6所述的像素电路,其中该电压补偿期间紧跟在该电压重置期间之后,该数据写入期间紧跟在该电压补偿期间之后,并且该发光期间紧跟在该数据写入期间之后。
8.如权利要求6所述的像素电路,其中该第一扫描信号致能于该电压重置期间、该电压补偿期间及该数据写入期间,该第二扫描信号致能于该电压重置期间及该电压补偿期间,该源极驱动信号致能于该数据写入期间,并且该发光信号致能于该电压重置期间及该发光期间。
9.如权利要求6所述的像素电路,其中该电压补偿期间的时间长度对应于一显示面板的一分辨率。
10.如权利要求1或3所述的像素电路,其中该第一参考电压小于该系统低电压与该发光元件的一点亮临界电压的一总和电压。
11.如权利要求1或3所述的像素电路,其中该发光元件包括一有机发光二极管及一微型发光二极管的其中之一。
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