CN108630648B - 半导体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 239000011347 resin Substances 0.000 claims abstract description 140
- 229920005989 resin Polymers 0.000 claims abstract description 140
- 238000007789 sealing Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 description 27
- 229910000679 solder Inorganic materials 0.000 description 8
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H02K—DYNAMO-ELECTRIC MACHINES
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
本发明提供采用抗振性高的单列直插式封装的半导体装置。从内置磁传感器等的树脂密封体(3)引出外部端子(2a~2c),在外部端子与相邻的外部端子之间设置树脂突起部,在树脂突起部与外部端子之间设置间隙。当安装到安装基板时,将树脂突起部固定在安装基板表面,外部端子在设置在安装基板的孔内固接。
Description
技术领域
本发明涉及采用单列直插式封装的半导体装置。
背景技术
在汽车行驶中有必要感测无电刷电动机或引擎的旋转状态,并将该感测结果反馈而控制旋转,从而提高旋转精度。为了响应这些需要,用于感测无电刷电动机或汽车引擎的旋转的磁传感器等的传感器元件被需求。传感器元件与半导体集成电路组合并纳入半导体封装。作为搭载传感器元件的半导体封装之一,一般知晓引脚(pin)插入型封装、所谓的单列直插式封装。后面,称为SIP。
SIP由树脂密封的树脂主体和从树脂主体引出的至少3根以上的外部端子构成,外部端子的长度相对于树脂主体至少为2倍以上,且在安装基板后外部端子的大部分也从基板露出。若以外部端子的大部分露出的状态将SIP搭载到基板,则汽车引擎或无电刷电动机的旋转造成的固有振动会传递到外部端子。树脂主体经由外部端子以对安装基板浮起的状态被保持,因此安装位置较高,容易反复受到来自无电刷电动机或汽车引擎的振动。反复受到振动,从而应力集中到SIP的外部端子部,容易发生外部端子自身的缺损、或用于固定连接基板和SIP的焊锡的裂缝。若发生这样的不良,则有可能导致安装基板和SIP的电路被粉碎,因运行中的引擎停止或冷却扇的停止而温度上升从而烧坏基板或部件这一不良。
为了解决这些课题,提出了抗振性高的SIP。(例如,参照专利文献1)
【现有技术文献】
【专利文献】
【专利文献1】日本特开平6-213741号公报。
发明内容
【发明要解决的课题】
通过利用记载于专利文献1的技术来降低受到振动的影响,但是外部端子的基准距(stand off)部露出,因此会挡住振动负荷所以保留不少振动的影响,抗振性并不充分。
本发明鉴于上述课题而构思,提供采用了抗振性高的单列直插式封装的半导体装置。
【用于解决课题的方案】
为了解决上述课题,因此,在本发明中采用了以下的方案。
一种半导体装置,采用了从树脂密封体的一个面引出的外部端子排成一列地排列的单列直插式封装,所述半导体装置的特征在于具备:从所述树脂密封体延伸设置的树脂突起部;以及设置在所述树脂突起部与相邻的树脂突起部之间的树脂切口部,在所述树脂切口部配置有所述外部端子,所述外部端子的前端比所述树脂突起部的前端更突出。
【发明效果】
通过采用上述方案,能够做成采用了减轻来自外部的振动的影响的、抗振性更高的单列直插式封装的半导体装置。
附图说明
【图1】是本发明的第1实施方式所涉及的半导体装置的鸟瞰图。
【图2】是从各方向观看图1中的本发明的第1实施方式所涉及的半导体装置的平面图。
【图3】是示出本发明的第1实施方式所涉及的半导体装置的制造方法的鸟瞰图。
【图4】是示出接着图3的、本发明的第1实施方式所涉及的半导体装置的制造方法的鸟瞰图。
【图5】是示出本发明的第1实施方式所涉及的半导体装置的搭载安装基板时的状态的鸟瞰图。
【图6】是从D方向观看图5中的本发明的第1实施方式所涉及的半导体装置的图。
【图7】是图6中的E部的放大图。
【图8】是本发明的第2实施方式所涉及的半导体装置的平面图。
【图9】是本发明的第3实施方式所涉及的半导体装置的平面图。
【图10】是本发明的第4实施方式所涉及的半导体装置的平面图。
【图11】是本发明的第5实施方式所涉及的半导体装置的平面图。
具体实施方式
以下,基于附图,对本发明的半导体装置进行说明。
图1是本发明的第1实施方式所涉及的半导体装置的鸟瞰图。半导体装置具备树脂密封体3和从树脂密封体3的左跟前的一个面即底面突出的树脂突起部3a、3b、3c、3d和外部端子2a、2b、2c,该树脂密封体3密封磁传感器或者角速度传感器等的传感器元件或者不包含磁传感器或者角速度传感器等的非传感器元件(以下将这些统称为半导体元件),在邻接的树脂突起部3a、3b、3c、3d之间设置没有树脂的部分即树脂切口部4a、4b、4c,在树脂切口部4a、4b、4c分别设置外部端子2a、2b、2c。外部端子2a、2b、2c排成一列,构成单列直插式封装。虽然未图示,但是外部端子2a、2b、2c与密封在树脂密封体3的半导体元件电连接。
图2是从各方向观看图1中的本发明的第1实施方式所涉及的半导体装置的平面图,(a)是从A方向观看的图,(b)是从B方向观看的图,(c)是从C方向观看的图。
图2(a)中将外部端子2a、2b、2c设为下侧而图示,安装到基板的情况下的安装面为本图的下表面。在树脂密封体3的下表面有树脂突起部3a、3b、3c、3d突出,在树脂突起部3a与3b之间设置“コ”字型的树脂切口部4a,在树脂突起部3b与3c之间设置树脂切口部4b,在树脂突起部3c与3d之间设置树脂切口部4c。在各个“コ”字型的树脂切口部4a、4b、4c分别设置从树脂密封体3引出的外部端子2a、2b、2c,与树脂密封体3相接的外部端子2a、2b、2c的基部被收入树脂切口部4a、4b、4c,外部端子2a、2b、2c的前端部比树脂突起部前端3h更突出。树脂切口部4a、4b、4c的宽度比外部端子2a、2b、2c的宽度更宽,在树脂切口部的内侧面与外部端子的侧面之间有间隙,该间隙确保在安装基板时在收纳形成在比树脂突起部前端3h更靠上侧的焊脚上具有充分的宽度及高度。在外部端子为宽度0.4mm的情况下,树脂切口部的内侧面(树脂突起部的侧面)与外部端子的侧面之间的间隙有至少0.1mm就是充分的,一般优选为0.1mm~0.2mm、即相对于外部端子的宽度而言具有1/4~1/2的间隙。
图2(b)是从图1的B方向观看的图。在树脂突起部前端3h与基板接触而安装的面,外部端子2a、2b、2c从树脂突起部前端3h突出的部分进入或嵌合到设置在基板的孔,从而进行安装。
图2(c)中图示了从图1的C方向观看的图。以在树脂切口部4a配置外部端子2a、在树脂切口部4b配置外部端子2b、在树脂切口部4c配置外部端子2c的方式,树脂切口部和外部端子成对配置。而且,外部端子2a、2b、2c排成一条直线地排列。在本实施例中,以外部端子为3根的情况为例进行说明,但是如果增加外部端子数则与其相应地会增加树脂切口部。
接着,利用图3及图4,对本发明的第1实施方式所涉及的半导体装置的制造方法进行说明。
如图3(a)所示,在引线框架1的1个边连接有外部端子2a、2b、2c,在外部端子2b连有搭载半导体元件9的岛部5,在岛部5的端部配置有延伸的内部端子7a、7b。另外,从外部端子2a、2c延伸的内部端子6a、6c在岛部5的附近与岛部5分离地设置。此外,作为引线框材料一般使用194Alloy材料或铜合金。
图3(b)是小片接合工序后的图,示出使半导体元件9经由芯片贴装材料8粘接在岛部5的表面的状态。
图3(c)是引线接合工序后的图,示出经由金属线10电连接半导体元件9的表面的电极焊盘和内部端子6a、6c、7a的状态。图中用金属线10来连接从岛部5延伸的内部端子7a和半导体元件9,但是鉴于半导体元件9上的电极焊盘的配置状态,连接到从岛部5延伸的内部端子7b也无妨。
图4是接着图3的、示出本发明的第1实施方式所涉及的半导体装置的制造方法的鸟瞰图。
图4(a)是示出通过树脂密封体3来密封载放于岛部5上的半导体元件9和内部端子6a、6c、7a和金属线10的状态的图。此时,引线框架1和外部端子2a、2b、2c从树脂密封体3露出。以包围外部端子2a、2b、2c与树脂密封体3相接的基部的三个面的方式形成树脂切口部4a、4b、4c。
接着,使焊锡镀层附着在引线框架1及外部端子2a、2b、2c的整个面,若在外部端子2a、2b、2c的前端切断而切开引线框架1,则完成如图4(b)所示的本发明的半导体装置。
该半导体装置在树脂密封体3的一个面具有由树脂突起部3a、3b、3c、3d和树脂切口部4a、4b、4c构成的凹凸,示出在树脂密封体3的树脂切口部4a、4b、4c配置有外部端子2a、2b、2c的外观。
图5是示出本发明的第1实施方式所涉及的半导体装置的搭载安装基板时的状态的鸟瞰图。准备安装基板11,以使安装基板11的表面和树脂密封体3的凹凸面相对接的方式安装。
图6是从D方向观看图5中的本发明的第1实施方式所涉及的半导体装置的图。另外,图7是图6中的E部(虚线的圆圈部)的放大图。
关于从安装在安装基板11的本发明的半导体装置的树脂密封体3引出的外部端子2a、2b、2c,其下半部分多进入形成在安装基板11的布线用孔12,经由基板安装用焊锡13固接在布线用孔12。此时,与布线用孔12的深度相比,固接的外部端子2a、2b、2c的长度设定为相等或短几分,以不会从安装基板11的背面凸出。而且,构成树脂密封体3的底面即凹凸面的树脂突起部3a~3d与安装基板11相接而固定。树脂突起部3a~3d的前端具有同一高度,以对安装基板11同等地相接。
另外,外部端子的不足上半部分位于安装基板11上,周围被树脂突起部3a~3d包围。由基板安装用焊锡13拱起的焊脚形成在外部端子侧面,在外部端子2a、2b、2c与形成在树脂密封体3的树脂切口部4a、4b、4c之间的间隙填充有焊脚,因此外部端子2a、2b、2c的上部和树脂突起部3a~3d经由焊脚而接合。
如以上那样,若在安装基板安装本发明的实施方式所涉及的半导体装置,则不仅使安装基板和外部端子固接,而且安装基板和树脂突起部相接而固定,进而,树脂突起部和外部端子经由焊脚连接,因此,即便从外部反复受到振动也难以导致外部端子缺损或焊锡裂缝。
在图8(a)示出本发明的第2实施方式所涉及的半导体装置的平面图。
图2(a)中将外部端子2a、2b、2c的侧面、和与其相对的树脂切口部4a、4b、4c的侧面平行地配置,但是在图8(a)中在树脂切口部4a、4b、4c的侧面设置锥形,树脂切口部和外部端子所形成的间隙设为从外部端子的基部逐渐宽度变宽的梯形形状。通过这样构成,能够避免填充到间隙中的、用于外部端子2a、2b、2c与布线用孔12的接合的基板接合用焊锡13的多余部分从布线用孔12溢出而侵入树脂突起部3a~3d与安装基板之间这样的不良。图8(b)及(c)为(a)的变形例,使各个树脂切口部的侧面形成为其间的间隙从外部端子的基部以阶梯状宽度变宽,形成为以圆弧状宽度变宽,与图8(a)的实施例同样,是抑制焊锡侵入树脂突起部3a~3d与安装基板之间的构造。
在图9(a)示出本发明的第3实施方式所涉及的半导体装置的平面图。
图9(a)与图2(a)的差异在于:在树脂突起部3a~3d的各个前端中央部设置槽部15这一点。槽部15与上述树脂切口部4a~4c相比,被设定为切口高度较低,设置为从图的跟前贯通到最里面。图9(b)及(c)是分别与图2(c)对应的图并且是从带有外部端子的半导体装置底面观看的平面图。图9(b)中槽部15从树脂突起部3a~3d各自的上边贯通到相反侧的底边,对于外部端子2a、2b、2c所排列的方向垂直设置,成为完全分割树脂突起部3a~3d的形状。图9(c)中槽部15分别局部地设置在树脂突起部3a~3d,槽部15为周围被树脂突起部3a~3d包围的形状。槽部15的长度(图的上下方向)比外部端子2a、2b、2c的厚度(图的上下方向)的长度更长,并设置在外部端子2a、2b、2c的两侧。在本实施例中外部端子2a、2b、2c的厚度为0.4mm,槽部15的长度设为0.6mm。在图9(b)、(c)中图示了对于一个树脂突起部设置一个槽部的形态,但是如在后面以图11说明那样,也可以设置多个槽部15。通过这样构成,能够将从安装基板布线用孔溢出的焊锡在附近通过各个槽部15来堵住。
如以上那样,通过设置该槽部,即便有焊锡侵入树脂突起部与安装基板之间,也能避免端子间的短路。
在图10(a)示出本发明的第4实施方式所涉及的半导体装置的平面图。
图10(a)与图2(a)的差异在于:在树脂突起部3a~3d的前端中央部设置第2树脂突起部16这一点。该第2树脂突起部16最好为不比外部端子2a、2b、2c突出的程度的高度。在对置的安装基板中在与第2树脂突起部16对应的位置设置孔,该孔与第2树脂突起部16嵌合,从而使得本发明的实施方式所涉及的半导体装置与安装基板的接合进一步牢固。此外,该孔与第2树脂突起部16的接合既可以仅仅是嵌合,也可以经由绝缘性粘接剂而接合。图10(b)是与图2(c)对应的图并且是从带有外部端子的半导体装置底面观看的平面图。关于第2树脂突起部16,在树脂突起部3a~3d上配置成使专有面积小于树脂突起部3a~3d,但是以外部端子2a、2b、2c和第2树脂突起部16排成一条直线的方式尽量配置在外部端子2a、2b、2c的近旁,从而能够减轻振动对外部端子2a、2b、2c的影响。进而,最好外部端子2a、2b、2c和两侧的第2树脂突起部16以等距离(对称地)配置。另外,在图10中示出对于一个树脂突起部设置一个第2树脂突起部16的形态,然而通过配置多个第2树脂突起部16能够更加牢固地接合。另外,在对于与第2树脂突起部16对应的孔的配置有制约的情况下,也可以在树脂突起部3a及3d不设置第2树脂突起部16而只设置树脂突起部3b及3c。
在图11(a)示出本发明的第5实施方式所涉及的半导体装置的平面图。
图11(a)与图10(a)对应,图11(b)与图10(b)对应。与图10的差异在于:在第2树脂突起部16的两侧设置槽部15这一点。通过这样的结构,能够预料到通过第2树脂突起部16提高接合和通过槽部15来避免端子间短路这两方。
以上,如说明的那样,本发明的半导体装置在外部端子的两侧具有树脂突起部,从而不仅使安装基板与外部端子固接,而且使得安装基板与树脂突起部相接地固定,进而,树脂突起部与外部端子经由焊脚而连接,所以,即便从外部反复受到振动也难以导致外部端子的缺损或焊锡裂缝。进而,外部端子为笔直形状并且能够做成引线框加工用冲压机模具的冲压冲头也是单纯形状并且冲头数也较少的廉价的模具。另外,外部端子较短,从而如果是同一尺寸的引线框则能够在引线框面内布局许多本发明的半导体装置,能够增加每一个引线框的半导体装置数,能够降低总的封装制造成本。
标号说明
1 引线框架;2、2a、2b、2c 外部端子;3 树脂密封体;3a、3b、3c、3d 树脂突起部;3h 树脂突起部前端;4a、4b、4c 树脂切口部;5 岛部;6a、6c、7a、7b 内部端子;8芯片贴装剂;9 半导体元件;10 金属线;11 安装基板;12 布线用孔;13 基板接合用焊锡;14 树脂切口与外部端子的间隙;15 槽部;16 第2树脂突起部。
Claims (6)
1.一种半导体装置,采用了从树脂密封体的一个面所引出的外部端子被排成一列地排列的单列直插式封装,其特征在于:
所述半导体装置具备:
从所述树脂密封体延伸设置的树脂突起部;以及
设置在所述树脂突起部与所相邻的树脂突起部之间的树脂切口部,
在所述树脂切口部配置有所述外部端子,所述外部端子的前端比所述树脂突起部的前端更突出,
在所述树脂突起部设置槽部,所述槽部被配置在所述外部端子与跟所述外部端子相邻的外部端子之间。
2.一种半导体装置,采用了从树脂密封体的一个面所引出的外部端子被排成一列地排列的单列直插式封装,其特征在于:
所述半导体装置具备:
从所述树脂密封体延伸设置的树脂突起部;以及
设置在所述树脂突起部与所相邻的树脂突起部之间的树脂切口部,
在所述树脂切口部配置有所述外部端子,所述外部端子的前端比所述树脂突起部的前端更突出,
在所述树脂突起部设置第2树脂突起部,所述第2树脂突起部被配置在所述外部端子与跟所述外部端子相邻的外部端子之间。
3.如权利要求1或2所述的半导体装置,其特征在于:所述外部端子的侧面与跟所述侧面对置的所述树脂切口部的内侧面分离。
4.如权利要求3所述的半导体装置,其特征在于:使所述树脂切口部的内侧面为锥形形状,所述内侧面与所述外部端子之间的间隙随着从所述外部端子的基部朝向前端而逐渐宽度变宽。
5.如权利要求3所述的半导体装置,其特征在于:使所述树脂切口部的内侧面为阶梯状,所述内侧面与所述外部端子之间的间隙随着从外部端子的基部朝向前端而逐渐宽度变宽。
6.如权利要求3所述的半导体装置,其特征在于:使所述树脂切口部的内侧面为圆弧状,所述内侧面与所述外部端子之间的间隙随着从外部端子的基部朝向前端而逐渐宽度变宽。
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