CN108630627A - 半导体封装及半导体封装的标记方法 - Google Patents

半导体封装及半导体封装的标记方法 Download PDF

Info

Publication number
CN108630627A
CN108630627A CN201710713264.5A CN201710713264A CN108630627A CN 108630627 A CN108630627 A CN 108630627A CN 201710713264 A CN201710713264 A CN 201710713264A CN 108630627 A CN108630627 A CN 108630627A
Authority
CN
China
Prior art keywords
film
semiconductor packages
identification
sealing material
screened
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710713264.5A
Other languages
English (en)
Inventor
高野勇佑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN108630627A publication Critical patent/CN108630627A/zh
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41MPRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
    • B41M5/00Duplicating or marking methods; Sheet materials for use therein
    • B41M5/26Thermography ; Marking by high energetic means, e.g. laser otherwise than by burning, and characterised by the material used
    • B41M5/262Thermography ; Marking by high energetic means, e.g. laser otherwise than by burning, and characterised by the material used recording or marking of inorganic surfaces or materials, e.g. glass, metal, or ceramics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02354Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light using a coherent radiation, e.g. a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54433Marks applied to semiconductor devices or parts containing identification or tracking information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Laminated Bodies (AREA)
  • Laser Beam Processing (AREA)

Abstract

本发明的实施方式提供一种视认性提高的半导体封装及半导体封装的标记方法。实施方式的半导体封装具备半导体元件、密封材料、屏蔽膜以及识别膜。所述密封材料设置在所述半导体元件的侧面上及上表面上。所述屏蔽膜设置在所述密封材料的侧面上及上表面上。所述识别膜设置在所述屏蔽膜的上表面上,具有含二价氧化钛的第1部分及含四价氧化钛的第2部分。

Description

半导体封装及半导体封装的标记方法
[相关申请]
本申请享有以日本专利申请2017-56365号(申请日:2017年3月22日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体封装及半导体封装的标记方法。
背景技术
在半导体封装中,为了降低EMI(Electro Magnetic Interference,电磁干扰)的影响,而在半导体元件之上隔着密封材料设置屏蔽膜。并且,为了识别半导体封装,而在半导体封装上形成标记。在对密封材料进行激光加工之后,沿着对密封材料加工而产生的凹凸形成屏蔽膜,由此形成标记。对于这种半导体封装,要求提高标记的视认性。
发明内容
本发明的实施方式提供一种视认性提高的半导体封装及半导体封装的标记方法。
根据本发明的实施方式,提供一种具备半导体元件、密封材料、屏蔽膜以及识别膜的半导体封装。所述密封材料设置在所述半导体元件的侧面上及上表面上。所述屏蔽膜设置在所述密封材料的侧面上及上表面上。所述识别膜设置在所述屏蔽膜的上表面上,具有含二价氧化钛的第1部分及含四价氧化钛的第2部分。
附图说明
图1(a)及(b)是表示实施方式的半导体封装的图。
图2(a)及(b)是表示实施方式的变化例的半导体封装的图。
图3是表示实施方式的半导体封装的标记方法的流程图。
具体实施方式
以下,一边参照附图,一边对本发明的各实施方式进行说明。
此外,附图为示意图或概念图,各部分的厚度与宽度的关系、部分间的大小的比率等未必与实物相同。而且,即便在表示相同部分的情况下,也有彼此的尺寸或比率根据附图而不同地表示的情况。
此外,在本案说明书及各图中,对与关于已出现过的图在上文叙述过的要素相同的要素标注相同的符号并适当省略详细说明。
(第1实施方式)
图1(a)及(b)是表示实施方式的半导体封装的图。
图2(a)及(b)是表示实施方式的变化例的半导体封装的图。
如图1(a)及(b)所示,在半导体封装1中设置有衬底10、半导体元件20、密封材料30、屏蔽膜40、保护膜50以及识别膜60。
衬底10例如为半导体衬底且包含硅(Si)。衬底10例如也可以包含金属。衬底10具有例如矩形状,且作为基底发挥功能。
半导体元件20设置在衬底10上。半导体元件20例如为设置在衬底10上的半导体芯片。
密封材料30以覆盖半导体元件20的侧面及上表面的方式设置在衬底10的上表面上。密封材料30例如包含树脂。作为形成密封材料30的树脂,可列举热硬化性树脂或热塑性树脂。密封材料30也可以由光硬化性树脂形成。
屏蔽膜40设置在衬底10的侧面上及密封材料30上。屏蔽膜40覆盖衬底10的侧面、密封材料30的侧面及上表面。通过像这样设置屏蔽膜40,半导体元件20的侧面及上表面被覆盖,从而能够降低EMI的影响。屏蔽膜40例如包含铜(Cu)。
保护膜50以覆盖侧面及上表面的方式设置在屏蔽膜40上。保护膜50例如包含铁(Fe)、铬(Cr)及镍(Ni)中的至少任一种。例如,保护膜50为不锈钢,且为铁(Fe)、铬(Cr)及镍(Ni)的合金或者铁(Fe)及铬(Cr)的合金。例如,保护膜50的厚度为300纳米以上。
如图1(a)所示,识别膜60设置在保护膜50的上表面上。识别膜60也能以覆盖侧面及上表面的方式设置在保护膜50上。识别膜60例如为包含氧化钛(TiO)的膜。当识别膜60为包含氧化钛的膜时,例如,以钛(Ti)为靶使用氧气(O2)通过溅镀法成膜于保护膜50。也可以通过将包含氧化钛的材料进行丝网印刷而成膜,还可以通过喷涂将包含氧化钛的材料涂膜。
如图1(b)所示,识别膜60具有第1部分60a及第2部分60b。第1部分60a是在保护膜50的上表面上形成识别膜60之后未进行激光照射的部分。另一方面,第2部分60b是在保护膜50的上表面上形成识别膜60之后进行了激光照射的部分。也就是说,第2部分60b是通过激光照射而被加工后的部分,相当于被标记的部分。
当识别膜60为包含氧化钛(TiO)的膜时,第1部分60a未被激光照射,因此包含二价氧化钛(TiO)。另一方面,第2部分60b被激光照射而包含四价氧化钛(TiO2)。第1部分60a(TiO)的颜色为黑色,第2部分60b(TiO2)的颜色为白色。也就是说,通过激光照射,识别膜60的一部分从黑色变化成白色。通过激光照射而进行由以下化学式(1)表示的反应。
2TiO+O2→2TiO2…(1)
作为激光照射的加工条件,激光例如为YAG(Yttrium Aluminum Garnet,钇-铝-石榴石)激光。所述化学式(1)表示的化学反应是在500℃到600℃的温度下进行,因此,激光输出就是所述化学式(1)表示的化学反应进行的程度的输出。例如,激光输出为5W。而且,500℃到600℃的温度是只要利用激光进行标记便能够达到的温度,使用半导体封装1的组装步骤或测试步骤为300℃左右,因此,在包含回焊处理等的组装步骤中,识别膜60不会变色,而能够确保被标记的部分(第2部分60b)的视认性。
识别膜60的厚度达到了在通过激光使氧化钛反应后能够识别黑色(第1部分60a)及白色(第2部分60b)的程度。如果除了识别标记以外,还作为用来降低EMI的影响的保护膜使用,那么识别膜60的厚度理想为0.1微米以上。
接下来,对半导体封装的变化例进行说明。
如图2(a)及(b)所示,在半导体封装2中设置有衬底10、半导体元件20、密封材料30、屏蔽膜40以及识别膜60。也就是说,相较于半导体封装1,本变化例的半导体封装2中未设置保护膜50。
如图2(a)所示,识别膜60以覆盖侧面及上表面的方式设置在屏蔽膜40上。当识别膜60为包含氧化钛的膜时,例如以钛为靶使用氧气通过溅镀法成膜于屏蔽膜40。
如图2(b)所示,识别膜60具有第1部分60a及第2部分60b。第1部分60a是在屏蔽膜40的上表面上形成识别膜60后未进行激光照射的部分。另一方面,第2部分60b是在屏蔽膜40的上表面上形成识别膜60后进行了激光照射的部分。也就是说,第2部分60b是通过激光照射而被加工后的部分,相当于被标记的部分。当识别膜60为包含氧化钛的膜时,通过激光照射,识别膜60的一部分从黑色变化为白色。
对半导体封装的标记方法进行说明。
图3是表示实施方式的半导体封装的标记方法的流程图。
如图3所示,准备配置有半导体元件20的衬底10(S110)。
接着,在半导体元件20上形成密封材料30(S120)。密封材料30例如包含树脂,且覆盖半导体元件20的侧面及上表面。
接着,在密封材料30上依次形成屏蔽膜40及保护膜50(S130)。屏蔽膜40覆盖密封材料30的侧面及上表面,保护膜50覆盖屏蔽膜40的侧面及上表面。
屏蔽膜40及保护膜50是由众所周知的方法成膜。例如,屏蔽膜40及保护膜50由溅镀法形成。此外,保护膜50也可以不形成在屏蔽膜40上。
接着,在保护膜50上形成识别膜60(S140)。识别膜60例如包含氧化钛,且覆盖保护膜50的上表面。例如,识别膜60由溅镀法形成。例如,在通过溅镀法形成屏蔽膜40、保护膜50及识别膜60的情况下,可以在相同的腔室内连续地形成。
接着,对识别膜60进行激光照射而加工(S150)。作为激光照射的加工条件,例如,激光为YAG激光,激光输出为5W。通过激光照射,识别膜60具有未被激光照射的第1部分60a及通过激光照射而被加工后的第2部分60b。第2部分60b相当于被标记的部分。
当识别膜60为包含氧化钛(TiO)的膜时,第1部分60a的颜色因未被激光照射而保持为黑色。另一方面,第2部分60b的颜色被激光照射而变为白色。
这样一来,通过利用激光照射使识别膜60的一部分从黑色变为白色,而对半导体封装1进行标记。
接下来,对本实施方式的效果进行说明。
半导体封装中存在如下情况,即,在对密封材料进行激光加工之后,沿着对密封材料加工而产生的凹凸形成屏蔽膜,由此形成标记。也就是说,通过使屏蔽膜追随于凹凸成膜,而出现阴影,从而视认标记。在像这样通过激光形成标记的情况下,考虑到热对半导体元件的影响,降低激光输出而形成标记。由此,密封材料中较浅地形成因激光产生的凹凸,如果在该浅凹凸中形成屏蔽膜,那么阴影也会变薄而导致视认性变差。
本实施方式的半导体封装1中,设置有具有通过激光照射而变色的部分(第2部分60b)的识别膜60。由此,能够确保半导体封装1的标记的视认性。
而且,在本实施方式中,在形成屏蔽膜40及保护膜50之后对识别膜60进行激光加工,因此,与由密封材料的凹凸形成标记的情况相比,降低了热对半导体元件的影响。而且,通过利用激光照射使识别膜60变色而形成标记,因此,与利用激光输出形成浅凹凸不同,能够确保标记的视认性。进而,能够使密封材料30变薄而减小半导体封装1整体的厚度。
而且,在本实施方式中,识别膜60例如在通过溅镀法形成之后被激光照射,因此,能够利用现有的设备容易地形成识别膜60。
如上所述,作为一例,对具有降低EMI的影响的构造的半导体封装1进行了说明,但并不限定于此。也就是说,半导体封装1中也可以不设置屏蔽膜40。半导体封装1的构造中,只要设置有具有第2部分60b的识别膜60即可。
已对本发明的若干实施方式进行了说明,但这些实施方式是作为示例而提出,并不意图限定发明的范围。这些新颖的实施方式能够以其它各种方式加以实施,且可在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中,并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1、2 半导体封装
10 衬底
20 半导体元件
30 密封材料
40 屏蔽膜
50 保护膜
60 识别膜
60a 第1部分
60b 第2部分

Claims (5)

1.一种半导体封装,其特征在于具备:
半导体元件;
密封材料,设置在所述半导体元件的侧面上及上表面上;
屏蔽膜,设置在所述密封材料的侧面上及上表面上;以及
识别膜,设置在所述屏蔽膜的上表面上,具有含二价氧化钛的第1部分及含四价氧化钛的第2部分。
2.根据权利要求1所述的半导体封装,其特征在于:
所述识别膜还设置在所述屏蔽膜的侧面上,含二价氧化钛的部分设置在所述屏蔽膜的侧面上的识别膜中。
3.根据权利要求1或2所述的半导体封装,其特征在于:
还具备设置在所述屏蔽膜及所述识别膜之间的保护膜。
4.一种半导体封装的标记方法,其特征在于具备如下步骤:
在配置于衬底的半导体元件上形成密封材料;
以覆盖所述半导体元件的方式在所述密封材料上形成屏蔽膜;
在所述屏蔽膜上形成含氧化钛的识别膜;以及
对所述识别膜照射激光,形成含二价氧化钛的第1部分及含四价氧化钛的第2部分。
5.根据权利要求4所述的半导体封装的标记方法,其特征在于:
还具备在所述屏蔽膜与所述识别膜之间形成保护膜的步骤。
CN201710713264.5A 2017-03-22 2017-08-18 半导体封装及半导体封装的标记方法 Pending CN108630627A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017056365A JP2018160527A (ja) 2017-03-22 2017-03-22 半導体パッケージ、及び、半導体パッケージのマーキング方法
JP2017-056365 2017-03-22

Publications (1)

Publication Number Publication Date
CN108630627A true CN108630627A (zh) 2018-10-09

Family

ID=63582910

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710713264.5A Pending CN108630627A (zh) 2017-03-22 2017-08-18 半导体封装及半导体封装的标记方法

Country Status (4)

Country Link
US (1) US10546818B2 (zh)
JP (1) JP2018160527A (zh)
CN (1) CN108630627A (zh)
TW (1) TWI686913B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326483A (zh) * 2018-12-17 2020-06-23 安世有限公司 半导体芯片级封装件和方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6775597B2 (ja) * 2016-11-11 2020-10-28 三菱電機株式会社 半導体装置およびその製造方法ならびに無線通信機器
US20190229064A1 (en) * 2018-01-24 2019-07-25 Powertech Technology Inc. Laser color marking method for a semiconductor package

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06100716A (ja) * 1992-02-26 1994-04-12 Sumitomo Electric Ind Ltd 目盛、模様、文字等を表示した弗素樹脂被覆物及びその製造方法
JP2002283729A (ja) * 2001-03-26 2002-10-03 Mitsubishi Materials Corp マーキング基材及びそれを用いた積層基材
JP2002329811A (ja) * 2001-04-26 2002-11-15 Fujitsu Ltd 半導体装置及びその製造方法
US6586057B1 (en) * 1999-09-29 2003-07-01 Fuji Photo Film Co., Ltd. Optical filter comprising transparent support and filter layer containing dye and binder polymer
CN1822361A (zh) * 2005-02-17 2006-08-23 台湾积体电路制造股份有限公司 造成半导体元件磁性敏感的磁屏蔽护罩
JP2006305926A (ja) * 2005-04-28 2006-11-09 Nippon Kararingu Kk レーザーマーキング用樹脂組成物及びレーザーマーキング方法
TW201128758A (en) * 2010-02-12 2011-08-16 Siliconware Precision Industries Co Ltd Quad flat non leaded package structure capable of preventing electromagnetic interference and method for forming the same
US8508023B1 (en) * 2010-06-17 2013-08-13 Amkor Technology, Inc. System and method for lowering contact resistance of the radio frequency (RF) shield to ground
CN103247604A (zh) * 2012-02-01 2013-08-14 三美电机株式会社 电子模块及其制造方法
TW201438889A (zh) * 2012-12-28 2014-10-16 Jx Nippon Mining & Metals Corp 附載體銅箔及使用其之印刷配線板、印刷電路板及覆銅積層板
US20160079178A1 (en) * 2014-09-17 2016-03-17 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
CN105900013A (zh) * 2014-02-05 2016-08-24 富士胶片株式会社 感活性光线性或感放射线性树脂组合物、感活性光线性或感放射线性膜、具备感活性光线性或感放射线性膜的空白掩模、光掩模、图案形成方法、电子器件的制造方法及电子器件
CN106409781A (zh) * 2015-07-31 2017-02-15 株式会社东芝 半导体装置及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000289128A (ja) 1999-04-09 2000-10-17 Nissei Electric Co Ltd マーキングチューブ成形体及びその製造方法
JP5318645B2 (ja) 2009-04-17 2013-10-16 日本カラリング株式会社 レーザーマーキング用熱可塑性樹脂組成物

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06100716A (ja) * 1992-02-26 1994-04-12 Sumitomo Electric Ind Ltd 目盛、模様、文字等を表示した弗素樹脂被覆物及びその製造方法
US6586057B1 (en) * 1999-09-29 2003-07-01 Fuji Photo Film Co., Ltd. Optical filter comprising transparent support and filter layer containing dye and binder polymer
JP2002283729A (ja) * 2001-03-26 2002-10-03 Mitsubishi Materials Corp マーキング基材及びそれを用いた積層基材
JP2002329811A (ja) * 2001-04-26 2002-11-15 Fujitsu Ltd 半導体装置及びその製造方法
CN1822361A (zh) * 2005-02-17 2006-08-23 台湾积体电路制造股份有限公司 造成半导体元件磁性敏感的磁屏蔽护罩
JP2006305926A (ja) * 2005-04-28 2006-11-09 Nippon Kararingu Kk レーザーマーキング用樹脂組成物及びレーザーマーキング方法
TW201128758A (en) * 2010-02-12 2011-08-16 Siliconware Precision Industries Co Ltd Quad flat non leaded package structure capable of preventing electromagnetic interference and method for forming the same
US8508023B1 (en) * 2010-06-17 2013-08-13 Amkor Technology, Inc. System and method for lowering contact resistance of the radio frequency (RF) shield to ground
CN103247604A (zh) * 2012-02-01 2013-08-14 三美电机株式会社 电子模块及其制造方法
TW201438889A (zh) * 2012-12-28 2014-10-16 Jx Nippon Mining & Metals Corp 附載體銅箔及使用其之印刷配線板、印刷電路板及覆銅積層板
CN105900013A (zh) * 2014-02-05 2016-08-24 富士胶片株式会社 感活性光线性或感放射线性树脂组合物、感活性光线性或感放射线性膜、具备感活性光线性或感放射线性膜的空白掩模、光掩模、图案形成方法、电子器件的制造方法及电子器件
US20160079178A1 (en) * 2014-09-17 2016-03-17 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
CN106409781A (zh) * 2015-07-31 2017-02-15 株式会社东芝 半导体装置及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326483A (zh) * 2018-12-17 2020-06-23 安世有限公司 半导体芯片级封装件和方法

Also Published As

Publication number Publication date
TWI686913B (zh) 2020-03-01
JP2018160527A (ja) 2018-10-11
TW201841332A (zh) 2018-11-16
US10546818B2 (en) 2020-01-28
US20180277488A1 (en) 2018-09-27

Similar Documents

Publication Publication Date Title
CN108630627A (zh) 半导体封装及半导体封装的标记方法
CN110619379B (zh) 金属卡及金属卡制造方法
TW201743344A (zh) 電子零件
CN101452825B (zh) 用于制造半导体器件的工艺
US20230031605A1 (en) Covers for electronic devices
CN107116949A (zh) 一种图案制备方法及电子设备
CN105718843A (zh) 指纹辨识装置及其制造方法
CN104255086A (zh) 基板的制造方法、基板以及掩蔽膜
US20190202228A1 (en) Method for forming and detecting security elements on the surface of a component or in a component, and system for detecting said security element
CN107527714B (zh) 带印字的电子部件及其制造方法
US20190229064A1 (en) Laser color marking method for a semiconductor package
US9486984B2 (en) Steel sheet and fabrication method thereof
WO2021006141A1 (ja) モジュールおよびその製造方法
US10115674B2 (en) Semiconductor device including electromagnetic interference (EMI) shielding layer and method for manufacturing the semiconductor device
CN107401554A (zh) 制造用于电机中的叠片叠层的方法
CN107229307A (zh) 一种移动终端的盖板及其制作方法、移动终端
US20220045013A1 (en) Module and method of manufacturing the same
US20220020697A1 (en) Module and method of manufacturing the same
KR20230014741A (ko) 착색된 콘택을 갖는 전자 칩 카드 모듈을 위한 전기 회로 및 그 제조 방법
JP4812461B2 (ja) 半導体装置およびその製造方法
KR20160052381A (ko) 기밀 밀봉용 리드 및 그 제조 방법, 그것을 사용한 전자 부품 수납 패키지
JP6560483B2 (ja) 非接触通信カード、転写フィルム
JPH0370115A (ja) 電子部品
CN106034382A (zh) 电路基板的制造方法及电路基板
JP2005325423A (ja) メッキ膜とメッキ部材及びその製造方法並びにメッキ膜の識別方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Tokyo

Applicant after: TOSHIBA MEMORY Corp.

Address before: Tokyo

Applicant before: Pangea Co.,Ltd.

Address after: Tokyo

Applicant after: Kaixia Co.,Ltd.

Address before: Tokyo

Applicant before: TOSHIBA MEMORY Corp.

CB02 Change of applicant information
TA01 Transfer of patent application right

Effective date of registration: 20220126

Address after: Tokyo

Applicant after: Pangea Co.,Ltd.

Address before: Tokyo

Applicant before: TOSHIBA MEMORY Corp.

TA01 Transfer of patent application right
RJ01 Rejection of invention patent application after publication

Application publication date: 20181009

RJ01 Rejection of invention patent application after publication