CN108630537A - 一种平坦化方法 - Google Patents

一种平坦化方法 Download PDF

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CN108630537A
CN108630537A CN201710180563.7A CN201710180563A CN108630537A CN 108630537 A CN108630537 A CN 108630537A CN 201710180563 A CN201710180563 A CN 201710180563A CN 108630537 A CN108630537 A CN 108630537A
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dielectric layer
manufacture craft
semiconductor structure
flattening method
mask layer
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CN108630537B (zh
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林仁杰
陈豊元
林文钦
黄祈纶
庄必泓
陈泰霖
陈筍弘
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种平坦化方法，包含提供基底，其上形成有一半导体结构。在基底上形成介电层，在介电层上形成掩模层。进行第一化学机械研磨制作工艺以移除半导体结构正上方的部分掩模层，形成开口暴露出部分介电层。进行一蚀刻制作工艺，自开口各向同性地移除部分介电层。移除掩模层后，对剩余的介电层进行第二化学机械研磨制作工艺。

Description

一种平坦化方法
技术领域
本发明涉及半导体制作工艺领域，特别涉及一种平坦化方法。
背景技术
动态随机存取存储器(dynamic random access memory,DRAM)属于一种挥发性存储器，包含由多个存储单元(memory cell)构成的阵列区(array area)以及控制电路所在的周边区(peripheral area)。一般而言，各存储单元是由一晶体管(transistor)连接一电容器(capacitor)的结构(1T1C)，通过电容存储电荷来达到存储数据的目的。
随着制作工艺世代的演进，为了缩小存储单元的尺寸而制作出具备更高集密度的芯片，存储器的结构已朝向三维(three-dimensional)发展，例如采用冠式电容结构(crown-type capacitor)，其存储单元的电容是以垂直的方向设置在晶体管上，不仅可大幅减少电容占据的平面面积，制作上也更具弹性，例如可简单通过增加电容的高度来增加电容的电极的接触面积而得到更大的电容量。
然而，冠式电容结构(crown-type capacitor)使得存储器的阵列区和周边区之间具有明显的阶梯差(step height)，造成后续平坦化制作工艺的控制更加困难。因此，本领域仍须要一种改良的平坦化制作工艺，可克服明显的阶梯差而得到一平坦的上表面。
发明内容
本发明目的在于提供一种改良的平坦化方法，可较准确控制而制作出理想的平坦上表面。
本发明提供的平坦化方法，包含下列步骤。首先，提供一基底，一半导体结构形成于该基底上。然后于基底上形成一介电层，其中该介电层覆盖该半导体结构的部分具有一第二表面，其余部分具有一第二表面。接着于该介电层上形成一掩模层，并进行一第一化学机械研磨制作工艺，以移除该半导体结构正上方的该掩模层而形成一开口，暴露出该介电层。进行一蚀刻制作工艺，自该开口移除该介电层至一第三表面。后续，移除该掩模层后，进行一第二化学机械研磨制作工艺。
附图说明
图1至图5为本发明第一实施例的平坦化方法的步骤剖面示意图；
图6为本发明第一实施例的一变化型的示意图；
图7至图10为本发明第二实施例的平坦化方法的步骤剖面示意图。
主要元件符号说明
10 基底 18 第一化学机械研磨制作工艺
12 半导体结构 22 蚀刻制作工艺
12a 顶面 24 移除制作工艺
14 介电层 26 第二化学机械研磨制作工艺
14a 第一表面 28 盖层
14b 第二表面 H 高度(厚度)
14c 第三表面 H1 阶梯差
16 掩模层 H2 阶梯差
16a 开口 H3 阶梯差
16b 末端
具体实施方式
请参考图1至图5为本发明第一实施例的步骤剖面示意图。
如图1所示，首先提供一基底10，一半导体结构12堆叠在基底10上。基底10例如是一动态随机存取存储器的基底，包含多个晶体管(图未示)以及多条交错的字符线(word-line,WL)和位线(bit-line,BL)形成其中。半导体结构12可以是由堆叠在阵列区正上方的冠式电容所构成，其高度(厚度)H例如介于1.5微米至2微米之间，或者可根据电容量的需求而具有更高的高度。本发明的平坦化方法也可用来对其他具有明显阶梯差的半导体元件表面的平坦化，并不限于实施例所述的存储器。
接着，在基底10上沉积一介电层14，然后于介电层14上形成掩模层16。介电层14的材料例如是氧化硅，厚度较佳大于半导体结构12的厚度，更佳约是半导体结构12厚度的两倍，例如介于3微米至4微米之间，以确保后续的平坦化制作工艺可具有足够的移除厚度。半导体结构12使得介电层14具有不平坦的表面形貌，包含覆盖在半导体结构12上、具有较高水平位置的第一顶面14a，以及覆盖在基底10上、具有较低水平位置的第二顶面14b。第一顶面14a与第二表面14b之间具有一阶梯差H1，大致上等于半导体结构的高度H。由于介电层14的厚度较佳大于半导体结构12的厚度，因此第二表面14b会高于半导体结构12的顶面12a。掩模层16共型地覆盖在介电层14上，材料较佳是与介电层14具有明显蚀刻选择性的材料，例如当介电层14为氧化硅时，掩模层16较佳选用氮化硅，但不限于此。根据本发明一实施例，掩模层16的厚度介于200埃至300埃之间。
如图2所示，接着较佳进行第一化学机械研磨制作工艺18，选择性移除位于半导体结构12正上方的部分掩模层16，但不移除其他区域的掩模层16，以仅于半导体结构12的正上方形成一开口16a，暴露出部分介电层14。本发明特征之一在于利用阶梯差H1，特别是对现有的平坦化制作工艺造成困难的明显阶梯差H1，使得位于半导体结构12正上方、覆盖在介电层14高地形区域上的掩模层16会在第一化学机械研磨制作工艺18中优先被移除，因此实现选择性移除部分掩模层16的目的。在其他实施例中，也可以选择以现有的曝光显影暨蚀刻制作工艺移除半导体结构12正上方的掩模层16。
如图3所示。接着，以掩模层16为蚀刻掩模进行蚀刻制作工艺22，自开口16a移除部分介电层14至一第三表面14c。蚀刻制作工艺22是对介电层14和掩模层16具有明显蚀刻选择性的蚀刻制作工艺，例如是以氢氟酸(HF)为主要蚀刻剂的湿蚀刻制作工艺，可以各向同性地将介电层14蚀刻至一预定厚度。根据本发明一实施例，第三表面14c会高于或等于第二表面14b，两者之间具有一阶梯差H2，例如介于500埃至2000埃之间。已知，现有技术若要对具有明显阶梯差的介电层进行平坦化，常额外形成光致抗蚀剂层覆盖住低地形区域的介电层后，再以干蚀刻制作工艺、各向异性地移除部分暴露出来的高地形区域的介电层。但是上述现有技术的方法，常在被蚀刻的区域周围，即在高地形区域和低地形区域之间形成明显的介电层凸柱，后续进行化学机械研磨制作工艺时，该介电层凸柱很容易被推倒而在研磨制作工艺中造成表面刮伤。本发明利用湿蚀刻制作工艺各向同性地移除部分介电层14，使得开口16a周围掩模层16的末端16b正下方的介电层14也会被侧向移除，并不会被末端16b遮蔽住而成为介电层凸柱，因此本发明的方法可降低表面刮伤的风险。根据本发明一优选实施例，第三表面14c大致上会是一平坦的表面，其面积会大于开口16a的面积。蚀刻制作工艺22后，掩模层16的末端16b会自第三表面14c的边缘凸出，并悬挂在第三表面14c的边缘。
如图4所示，接着进行一移除制作工艺24以全面性地移除掩模层16，暴露出第二表面14b以及剩余的第一顶面14a。值得注意的是，制作工艺至此，介电层14表面形貌的阶梯差已经由原本大致上等于半导体结构12高度H的明显阶梯差H1明显减少至阶梯差H2，例如由原本约是1.5至2微米的阶梯差H1减少至介于500埃至2000埃之间的阶梯差H2，几乎是减少了百分之90的高度，具体来说，是通过蚀刻制作工艺22(湿蚀刻制作工艺)而达成。移除制作工艺24可以是以磷酸(H3PO4)为主要蚀刻剂的湿蚀刻制作工艺，或者也可以是以含氟气体，例如CF3、C4F6、C4F8等有机氟化物为主要蚀刻剂的干蚀刻制作工艺。
在其他实施例中，例如当选用材质较不易对介电层14造成刮伤的材料做为掩模层16时，或者形成厚度较薄的掩模层16时，也可选择以接下来要进行的第二化学机械研磨制作工艺26(参考图5)同时移除掩模层16，即图3的蚀刻制作工艺22完成后就接着进行图5的第二化学机械研磨制作工艺26，并不须要进行图4所示的移除制作工艺24。
如图5所示。接着对介电层14进行第二化学机械研磨制作工艺26，以将第三表面14c、第二表面14b和剩余的第一顶面14a研磨至一平坦表面，但不暴露出半导体结构12。第二化学机械研磨制作工艺26后较佳是留下厚度为2500埃至3000埃的介电层14覆盖在半导体结构12的正上方。值得注意的是，进行第二化学机械研磨制作工艺26前，原本介电层14具有的微米等级的阶梯差H1，已经被减小至约剩下原本高度的百分之10左右的阶梯差H2，因此第二化学机械研磨制作工艺26可轻易地以较短的研磨时间以及较少的移除量，就达到消除阶梯差H2的目的，就得到平坦表面。
请参考图6，为前文所述第一实施例的一变化型，对应于图3所示步骤，不同的地方在于，蚀刻制作工艺22可将介电层14蚀刻至一低于第二表面14b的第三表面14c，但仍然高于半导体结构12的顶面12a，不暴露出半导体结构12。第三表面14c和第二表面14b之间同样具有阶梯差H2，较佳介于500埃至2000埃之间。如图6所示，开口16a周围的掩模层16末端16b正下方的介电层14同样被蚀刻制成22侧向移除掉。值得注意的是，图6中，介电层14的第一表面14a已经完全被蚀刻制作工艺22移除，因此后续是对第三表面14c和第二表面14b进行第二化学机械研磨制作工艺26直到得到平坦表面。
请参考图7至图10，为本发明第二实施例的步骤剖面示意图。为了简化说明，与第一实施例相同的材料层或相同的制作工艺步骤以相同的符号表示。与第一实施例主要不同处在于，第二实施例中介电层14沉积时的厚度是小于或等于半导体结构12的高度H。
如图7所示，首先提供一基底10，并于基底10上形成具有高度H的半导体结构12，再依序于基底10上沉积介电层14以及掩模层16。介电层14覆盖在半导体结构12上的部分具有第一表面14a，其余覆盖在基底10上的部分具有第二表面14b，第一表面14a高于第二表面14b，两者之间具有一阶梯差H1。第二实施例中的第二表面14b可等高于或低于半导体结构12的顶面12a。
如图8所示，接着进行第一化学机械研磨制作工艺18，选择性地移除半导体结构12正上方的掩模层16，形成开口16a，暴露出部分介电层14。接着进行蚀刻制作工艺22，自开口16a各向同性地移除部分介电层14至一第三表面14c，第三表面14c高于半导体结构12的顶面12a，更高于第二表面14b。半导体结构12并不会自第三表面14c暴露出来。第三表面14c与第二表面14b之间具有阶梯差H2。
如图9所示，接着蚀刻移除掩模层16，暴露出第二表面14b以及剩余的第一表面14a，然后在介电层14上形成一盖层28，材料例如是氧化硅。盖层28大致上会复制其下方介电层14的表面形貌，即覆盖在第三表面14c上与覆盖在第二表面14b上的部分会具有一阶梯差H3，大致上等于阶梯差H2。
如图10所示，接着对盖层28进行第二化学机械研磨制作工艺22以移除阶梯差H3而得到一平坦表面，并且达到一目标厚度，例如留下总厚度介于2500埃至3000埃之间的介电层14和盖层28，覆盖在半导体结构12顶面12a的正上方。
本发明利用介电层的大阶梯差，可以简单地仅用化学机械研磨制作工艺来选择性地移除部分掩模层，暴露部分介电层，然后再以剩余的掩模层为蚀刻掩模，进行湿蚀刻制作工艺各向同性地移除部分暴露的介电层，将上述大阶梯差降低至化学机械研磨制作工艺可轻易移除的高度，接着再进行另一次化学机械研磨制作工艺，去除剩余的阶梯差，得到平坦表面。现有技术的平坦化方法，通常需额外形成图案化光致抗蚀剂层以实现选择性移除的目的，或者额外设置研磨停止层并采用高选择性的化学机械研磨制作工艺。相较于现有技术的方法，本发明不仅具有较简化的制作工艺步骤，较好的平坦化效果，还可降低制作成本。
以上所述仅为本发明之优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种平坦化方法，包含:
提供一基底，一半导体结构形成于该基底上；
在基底上形成一介电层，该介电层覆盖该半导体结构的部分具有一第一表面，其余部分具有一第二表面；
在该介电层上形成一掩模层；
进行一第一化学机械研磨制作工艺，移除该半导体结构正上方的该掩模层以形成一开口，暴露出该介电层；
进行一蚀刻制作工艺，自该开口各向同性地移除该介电层至一第三表面；
移除该掩模层；以及
进行一第二化学机械研磨制作工艺。
2.如权利要求1所述的平坦化方法，其中该蚀刻制作工艺为湿蚀刻制作工艺。
3.如权利要求1所述的平坦化方法，其中该半导体结构并未自该第三表面暴露出来。
4.如权利要求1所述的平坦化方法，其中该第三表面的面积大于该开口的面积。
5.如权利要求1所述的平坦化方法，其中该蚀刻制作工艺后，该掩模层的一末端自该第三表面的边缘凸出，并悬挂在该第三表面的边缘。
6.如权利要求1所述的平坦化方法，其中该第一表面高于该第二表面，该第二表面高于该半导体结构的一顶面。
7.如权利要求6所述的平坦化方法，其中该第三表面高于该第二表面。
8.如权利要求6所述的平坦化方法，其中该第三表面低于该第二表面。
9.如权利要求1所述的平坦化方法，其中该第一表面高于该第二表面，该第二表面低于该半导体结构的顶面。
10.如权利要求9所述的平坦化方法，其中进行该第二化学机械研磨制作工艺之前，还包含于该介电层上形成一盖层。
11.如权利要求1所述的平坦化方法，其中是通过一移除制作工艺移除该掩模层。
12.如权利要求1所述的平坦化方法，其中是通过该第二化学机械研磨制作工艺移除该掩模层。
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