CN108535626B - Full-automatic test device and method for SOC single particle test - Google Patents

Full-automatic test device and method for SOC single particle test Download PDF

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Publication number
CN108535626B
CN108535626B CN201711477725.XA CN201711477725A CN108535626B CN 108535626 B CN108535626 B CN 108535626B CN 201711477725 A CN201711477725 A CN 201711477725A CN 108535626 B CN108535626 B CN 108535626B
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soc chip
soc
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power supply
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CN108535626A (en
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沈国琳
于立新
彭和平
庄伟�
亓洪亮
王舒敏
刘亚丽
尤利达
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

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Abstract

A full-automatic test device for SOC single-particle test comprises a host, an SOC test board and a programmable power supply; the SOC test board comprises a flash, a SOC chip to be tested and a power-on reset circuit; the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the instruction, and the SOC chip to be tested obtains a traversal result and then sends the traversal result to the host computer in a fixed period; the host receives and stores the traversal result sent by the SOC chip to be tested; meanwhile, the host monitors and stores the state of the traversal result sent by the SOC chip to be tested and the current of the programmable power supply, and is also used for controlling the power-off and power-on of the programmable power supply; and the host machine utilizes the traversal result sent by the SOC chip to be tested and the state of the traversal result sent by the SOC chip to be tested, and then completes the test of the SOC chip to be tested by adopting a statistical method. Meanwhile, the invention also comprises a full-automatic test method for SOC single event test.

Description

Full-automatic test device and method for SOC single particle test
Technical Field
The invention relates to a full-automatic testing device and method for SOC single event testing, and belongs to the technical field of computers.
Background
The space processor is affected by radiation, which may cause the memory content in the memory bank to suddenly change between "0" and "1", thereby causing the wrong logic state of the semiconductor circuit, affecting the function of the semiconductor device, commonly referred to as Single Event Upset (SEU), and also may cause the latch-up phenomenon that the parasitic thyristor inherent in the CMOS device is triggered to turn on, forming a low-impedance large-current path between the power supply and the ground. In order to test the operation state of the space processor in the space environment, the irradiation experiment is carried out on the ground surface as a necessary approach. The irradiation particle accelerator can send a large amount of particle (preset) radiation with different energies to a space processor to be tested in a short time, and further imitates the influence of the processor after long-time irradiation in a space environment in a short time. The machine of the particle accelerator needs to be reserved in advance, and the value is high. In the conventional method for testing the SOC, the test board is manually controlled to reload the program, so that on one hand, time is consumed, and on the other hand, if irradiation is continued in the process of downloading the program, statistical errors can be caused.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the full-automatic test device and method for SOC single event test overcome the defects of the prior art, can complete the automatic test of the tested SOC chip by constructing the SOC test board and combining the host, improve the test precision, shorten the test period, improve the test reliability, and greatly save manpower, material resources and time cost.
The purpose of the invention is realized by the following technical scheme:
a full-automatic test device for SOC single-particle test comprises a host, an SOC test board and a programmable power supply; the SOC test board comprises a flash, a SOC chip to be tested and a power-on reset circuit;
the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the instruction, and the SOC chip to be tested obtains a traversal result and then sends the traversal result to the host computer in a fixed period; the host receives and stores the traversal result sent by the SOC chip to be tested; meanwhile, the host monitors and stores the state of the traversal result sent by the SOC chip to be tested and the current of the programmable power supply, and is also used for controlling the power-off and power-on of the programmable power supply; the host machine utilizes the traversal result sent by the SOC chip to be tested and the state of the traversal result sent by the SOC chip to be tested, and then adopts a statistical method to complete the test of the SOC chip to be tested;
when the host does not receive the traversal result sent by the SOC chip to be tested in a fixed period, the host judges that the SOC chip to be tested has a crash failure mode; and then the host commands the programmable power supply to be powered up again, and when the SOC chip to be tested is powered up again, the power-on reset circuit controls the SOC chip to be tested to read the reset program in the flash, so that the storage area or the module in the SOC chip to be tested is initialized normally.
According to the full-automatic test device for the SOC single-particle test, the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the automatic control instruction or the manual control instruction.
In the fully-automatic test device for the SOC single-particle test, the traversal result sent by the tested SOC chip comprises the upset error mode generated by the tested SOC chip.
According to the full-automatic testing device for the SOC single-event test, the host monitors the current of the programmable power supply, and when the current of the programmable power supply is more than 2 times of the rated current of the SOC chip to be tested, the host controls the programmable power supply to be powered off.
According to the full-automatic test device for the SOC single-particle test, the tested SOC chip sends the traversal result to the host at a fixed period of 0.1-3 s.
According to the full-automatic testing device for the SOC single event test, when the host monitors the state that the tested SOC chip sends the traversal result and the current of the programmable power supply, the current abnormity priority of the programmable power supply is higher than the state fault mode that the tested SOC chip sends the traversal result, namely when the host judges that the current of the tested SOC chip is abnormal by monitoring the current of the programmable power supply, the programmable power supply is preferentially controlled to be powered off.
According to the full-automatic test device for the SOC single-event test, the SOC test board further comprises a power supply, the programmable power supply supplies power to other components of the SOC test board through the power supply, and the power supply is used for finishing voltage transformation output by the programmable power supply.
According to the full-automatic test device for the SOC single-particle test, the SOC test board further comprises a Max3232 module, and the Max3232 module is used for testing a serial port controller of the SOC chip to be tested; meanwhile, the Max3232 module is used for serial port communication between the SOC chip to be tested and the host.
A full-automatic test method for SOC single-particle test comprises the following steps:
selecting an automatic mode or a manual mode on a host to carry out SOC single-particle test;
step two, the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the instruction, and simultaneously monitors and stores the state of the traverse result sent by the SOC chip to be tested and the current of the programmable power supply;
thirdly, the host machine judges the current of the program control power supply; if the current is abnormal, the test is finished, otherwise, the step four is carried out;
step four, the host judges the state of the traversal result sent by the SOC chip to be tested; if the state is normal, the step two is carried out, the storage area or the module in the SOC chip to be tested is continuously traversed until the test is finished, and otherwise, the step five is carried out;
and step five, the host commands the programmable power supply to be powered up again, initializes the storage area or the module in the SOC chip to be tested, and then shifts to step two until the test is finished.
Compared with the prior art, the invention has the following beneficial effects:
(1) compared with the prior art, the device has the advantages that the operation of the test process is simple, the test result is obtained under the condition of less human intervention, the test efficiency is high, and the test period is short;
(2) the host of the device provides automatic protection for the SOC test board, if the current exceeds twice of the rated limit, the power is automatically cut off for alarming, and the SOC chip to be tested can be powered on after confirmation, so that the SOC chip to be tested is effectively protected;
(3) the device can greatly save the test time, the whole experiment process in the manual measurement mode in the prior art can be completed by at least two persons, and after the device and the method are adopted, the whole test can be completed by only monitoring the device by one person; the power-on operation is automatically carried out after the SOC test chip is automatically judged to be dead, and the process saves at least ten percent of time;
(4) the device can improve the measurement response precision, can automatically measure data in a period of 0.1s, is far less than the fastest manual 1s in the prior art, saves the test period, and simultaneously, can detect the data more quickly, thereby further improving the measurement precision.
Drawings
FIG. 1 is a schematic diagram of a fully automatic test device for SOC single event testing according to the present invention;
FIG. 2 is a flow chart of a fully automatic test method for SOC single event testing according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A full-automatic test device for SOC single-particle test comprises a remote monitor, a host, an SOC test board and a programmable power supply. The SOC test board comprises an MAC module, an sram module, a flash module, a Max3232 module, a DDR module, a SOC chip to be tested, a power supply module and a power-on reset circuit, and is shown in figure 1.
The SOC chip to be tested comprises a plurality of storage areas or modules; the SOC chip to be tested sequentially traverses a storage area or a module in the SOC chip to be tested according to the instruction of the host, and a program traversing the storage area or the module in the SOC chip to be tested is stored in the flash module; after the SOC chip receives the traversal command sent by the host, the SOC chip reads the traversal program from the flash module, and then the SOC chip sequentially traverses the storage area or the module in the SOC chip.
The SOC chip to be tested obtains the traversal result, and the SOC chip to be tested is sent to the host computer at a fixed period of 0.1-3 s through the serial port; in this embodiment, the SOC chip under test sends the traversal result to the host at a fixed period of 0.5s, where the traversal result includes a rollover error pattern occurring in a storage area or a module in the SOC chip under test.
The host is used for controlling the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested, the host can command the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through an automatic control instruction or a manual control instruction, and then the host receives and stores a traversal result sent by the SOC chip to be tested; meanwhile, the host monitors and stores the state of the traversal result sent by the SOC chip to be tested and the current of the programmable power supply, and controls the power-off and power-on of the programmable power supply. And the host completes the test of the SOC chip to be tested by adopting a statistical method according to the traversal result sent by the SOC chip to be tested and the state of the traversal result sent by the SOC chip to be tested.
Specifically, the host obtains a turnover error mode of the SOC chip from a traversal result sent by the SOC chip to be tested; the host judges whether the state of the traversal result sent by the SOC chip to be tested is normal, when the SOC chip to be tested sends the traversal result to the host through the serial port in a fixed period, the host judges that the SOC chip to be tested does not have a dead halt fault mode, when the host does not receive the traversal result sent by the SOC chip to be tested in the fixed period, the host judges that the SOC chip to be tested has the dead halt fault mode, in the embodiment, when the host does not receive the traversal result sent by the SOC chip to be tested in 1s, the host judges that the SOC chip to be tested has the dead halt fault mode.
The purpose of monitoring the current of the programmable power supply by the host computer is to judge whether the current of the SOC chip to be tested is abnormal, when the current of the programmable power supply is more than 2 times of the rated current of the SOC chip to be tested, the host computer judges that the current of the SOC chip to be tested is abnormal, the host computer controls the programmable power supply to be powered off, and the physical damage of the SOC chip to be tested caused by the abnormal current is avoided. In the process that the host monitors the state that the SOC chip to be tested sends the traversal result and the current of the programmable power supply, the priority of the current of the programmable power supply is higher than the state that the SOC chip to be tested sends the traversal result, namely when the host judges that the current of the SOC chip to be tested is abnormal by monitoring the current of the programmable power supply, the programmable power supply is directly controlled to be powered off.
When the host computer judges that the SOC chip to be tested has a crash failure mode, the host computer sends a command to the programmable power supply to command the programmable power supply to be powered off, then the host computer sends a command to the programmable power supply to command the programmable power supply to be powered on, and the programmable power supply is used for supplying power to the SOC test board. When the SOC chip to be tested is powered on again, the power-on reset circuit sends a power-on reset pulse to the SOC chip to be tested, and after the SOC chip to be tested receives the power-on reset pulse, the SOC chip to be tested reads a reset program in the flash so as to ensure that a storage area or a module in the SOC chip to be tested is initialized normally.
The remote monitor is used for monitoring a command sent by the host to the SOC chip to be tested, a traversal result sent to the host after the SOC chip to be tested traverses, the current of the program-controlled power supply monitored by the host, and the power failure of the program-controlled power supply controlled by the host, and meanwhile, the remote monitor can control the command sent by the host to the SOC chip to be tested and the power failure command of the program-controlled power supply controlled by the host. The remote monitor can be far away from the host, which is beneficial to realizing remote monitoring and control, and is convenient for equipment arrangement in the test process, and reduces the equipment arrangement near the test environment.
The power supply is used for finishing voltage conversion output by the program control power supply so as to meet the voltage requirement of normal work of other components in the SOC test boards such as the SOC chip to be tested. The program-controlled power supply has the function of multi-output of V1, V2, V3, V4 and the like, and can meet the voltage requirements of normal work of other components in a plurality of different SOC chips to be tested and SOC test boards when being matched with the power supply.
The MAC module is used for testing the Ethernet transmission controller of the SOC chip to be tested, and can measure each working mode of the Ethernet transmission controller.
The Max3232 module is used as a serial port module of the SOC test board and is used for testing whether a serial port controller of the SOC chip to be tested is normal or not on one hand; on the other hand, the Max3232 module is used for serial port communication between the SOC chip to be tested and the host, namely the host sends an instruction to the SOC chip to be tested through the Max3232 module, and the SOC chip to be tested sends a traversal result through the Max3232 module.
The DDR module is used for testing whether the DDR control module of the SOC chip to be tested is normal in function.
The sram module is used for testing whether the sram memory controller of the tested SOC chip is normal.
A full-automatic test method for SOC single event test is disclosed, as shown in FIG. 2, which is realized by using the full-automatic test of SOC single event test, and comprises the following steps:
selecting an automatic mode or a manual mode on a host to carry out SOC single-particle test;
step two, the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the instruction, and simultaneously monitors and stores the state of the traverse result sent by the SOC chip to be tested and the current of the programmable power supply;
thirdly, the host machine judges the current of the program control power supply; if the current is abnormal, the test is finished, otherwise, the step four is carried out;
step four, the host judges the state of the traversal result sent by the SOC chip to be tested; if the state is normal, the step two is carried out, the storage area or the module in the SOC chip to be tested is continuously traversed until the test is finished, and otherwise, the step five is carried out;
and step five, the host commands the programmable power supply to be powered up again, initializes the storage area or the module in the SOC chip to be tested, and then shifts to step two until the test is finished.
In the device and the operation process of the invention, the SOC test board is fixed in the particle emitter, the irradiation particles are adjusted to hit the SOC test chip to be tested by adjusting the position and the distance of the SOC test board, and simultaneously, the irradiation particles are prevented from influencing other circuits, and the programmable power supply and the host are connected with the SOC test board through data lines outside the experimental environment.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Claims (5)

1. A full-automatic testing arrangement of SOC single particle test which characterized in that: the system comprises a host, an SOC test board and a programmable power supply; the SOC test board comprises a flash, a SOC chip to be tested and a power-on reset circuit; the system also comprises a remote monitor;
the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the instruction, and the SOC chip to be tested obtains a traversal result and then sends the traversal result to the host computer in a fixed period; the host receives and stores the traversal result sent by the SOC chip to be tested; meanwhile, the host monitors and stores the state of the traversal result sent by the SOC chip to be tested and the current of the programmable power supply, and is also used for controlling the power-off and power-on of the programmable power supply; the host machine utilizes the traversal result sent by the SOC chip to be tested and the state of the traversal result sent by the SOC chip to be tested, and then adopts a statistical method to complete the test of the SOC chip to be tested;
when the host does not receive the traversal result sent by the SOC chip to be tested in a fixed period, the host judges that the SOC chip to be tested has a crash failure mode; then the host commands the program control power supply to be powered up again, and when the SOC chip to be tested is powered up again, the power-on reset circuit controls the SOC chip to be tested to read a reset program in the flash, so that a storage area or a module in the SOC chip to be tested is initialized normally;
the remote monitor is used for monitoring a command sent by the host to the SOC chip to be tested, a traversal result sent to the host after the SOC chip to be tested traverses, the current of the programmable power supply monitored by the host, and the power failure of the programmable power supply controlled by the host, and meanwhile, the remote monitor can control the command sent by the host to the SOC chip to be tested and the power failure command of the programmable power supply controlled by the host; the remote monitor is far away from the host computer, so that remote monitoring and control are realized, equipment arrangement in the test process is facilitated, and equipment arrangement near the test environment is reduced;
the SOC test board also comprises a power supply, the programmable power supply supplies power to other components of the SOC test board through the power supply, and the power supply is used for finishing voltage conversion output by the programmable power supply;
the traversal result sent by the SOC chip to be tested comprises a turnover error mode of the SOC chip to be tested;
the host monitors the current of the programmable power supply, and controls the programmable power supply to be powered off when the current of the programmable power supply is more than 2 times of the rated current of the SOC chip to be tested;
the host monitors the state of the tested SOC chip sending the traversal result and the current of the programmable power supply, the current abnormity priority of the programmable power supply is higher than the state fault mode of the tested SOC chip sending the traversal result, namely when the host judges that the current of the tested SOC chip is abnormal by monitoring the current of the programmable power supply, the programmable power supply is controlled to be powered off preferentially.
2. The fully automatic test device for single event testing of SOC of claim 1, wherein: and the host commands the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip through the automatic control instruction or the manual control instruction.
3. The fully automatic test device for single event testing of SOC of claim 1, wherein: and the SOC chip to be tested sends the traversal result to the host at a fixed period of 0.1 s-3 s.
4. The fully automatic test device for single event testing of SOC of any one of claims 1 to 3, wherein: the SOC test board further comprises a Max3232 module, and the Max3232 module is used for testing a serial port controller of the SOC chip to be tested; meanwhile, the Max3232 module is used for serial port communication between the SOC chip to be tested and the host.
5. A full-automatic test method for SOC single particle test is characterized in that: the fully automatic test device of claim 1, comprising the steps of:
selecting an automatic mode or a manual mode on a host to carry out SOC single-particle test;
step two, the host computer orders the SOC chip to be tested to sequentially traverse the storage area or the module in the SOC chip to be tested through the instruction, and simultaneously monitors and stores the state of the traverse result sent by the SOC chip to be tested and the current of the programmable power supply;
thirdly, the host machine judges the current of the program control power supply; if the current is abnormal, the test is finished, otherwise, the step four is carried out;
step four, the host judges the state of the traversal result sent by the SOC chip to be tested; if the state is normal, the step two is carried out, the storage area or the module in the SOC chip to be tested is continuously traversed until the test is finished, and otherwise, the step five is carried out;
and step five, the host commands the programmable power supply to be powered up again, initializes the storage area or the module in the SOC chip to be tested, and then shifts to step two until the test is finished.
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