CN109581185B - SoC chip laser simulation single particle irradiation detection and fault positioning method and system - Google Patents

SoC chip laser simulation single particle irradiation detection and fault positioning method and system Download PDF

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CN109581185B
CN109581185B CN201811368446.4A CN201811368446A CN109581185B CN 109581185 B CN109581185 B CN 109581185B CN 201811368446 A CN201811368446 A CN 201811368446A CN 109581185 B CN109581185 B CN 109581185B
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soc chip
soc
test
current
chip
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CN109581185A (en
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尤利达
陈雷
于立新
彭和平
庄伟�
张世远
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]

Abstract

The invention provides a method and a system for SoC laser simulation single particle irradiation detection and fault positioning, wherein the method comprises the following steps: (1) hollowing out a test area of a chip to be tested; (2) if the dynamic test is carried out, selecting a function test program of a certain module, starting the function test, and outputting a test result; (3) if the static test is carried out, the PLL clock bypasses, the clock signal input is stopped, and the state of the circuit is detected through the current change; (4) if the reset state test is carried out, the reset pin is connected to be low, the SoC chip is continuously in the reset state through the reset circuit, and the circuit state is detected by observing the current change and the frequency waveform of the phase-locked loop. The invention avoids the influence of larger laser spots on the non-test area and improves the test comprehensiveness and accuracy of the SoC chip.

Description

SoC chip laser simulation single particle irradiation detection and fault positioning method and system
Technical Field
The invention relates to the field of single particle effect test technology and method, in particular to a method for testing and detecting devices such as SoC chips and the like, finding problems and finding faults and positioning faults by laser simulation single particle effect irradiation.
Background
Spacecraft are exposed in outer space to the radiation of energetic particles such as the galaxy cosmic rays, the solar cosmic rays, the earth's radiation carrying particles and atmospheric neutrons. When the device is irradiated by high-energy particles, the single-particle effect is easy to occur. As chip fabrication processes and integration levels continue to increase, the feature sizes of semiconductor devices continue to shrink, and integrated circuits become more and more sensitive to spatial radiation effects. The research and analysis of the single event effect of the aerospace electronic device are carried out, and the method has important significance for improving the operation stability of the spacecraft and the reliability of the integrated circuit.
In order to ensure safe and reliable flight of the aerospace craft, it is important to perform ground single event effect simulation experiments on aerospace electronic devices so as to evaluate the single event effect resistance of the devices. The main means of ground simulation of the single event effect is a heavy ion acceleration experiment, but the accelerator resource is limited, the experiment cost is high, and the analysis and research of the internal structure of the device are difficult. In recent years, the laser simulation single-particle effect experiment is more and more emphasized as an effective supplement of the heavy ion experiment method.
The laser simulation single particle experiment does not need vacuum, the experiment cost is low, and the efficiency is high; the laser frequency is accurate and adjustable, a single pulse irradiation experiment can be realized, the accurate positioning of the single particle response details of a device is facilitated, and the effective analysis of the failure mechanism of a chip and the positioning of a failure part are facilitated; meanwhile, the device is safe and free of radiation, the device is subjected to plane scanning by using a precision mechanical platform, and a designated area can be selected for continuous scanning and single-point irradiation, so that the precise positioning of a weak link of the chip is realized, and the reinforcement design of the device is fed back and guided. However, the problem of multi-bit turning is easily caused due to the large laser spot, so that the turning section of the chip is large, and the turning characteristic of the chip is not easily reflected; and the laser is mostly pulse laser, and the laser frequency and the mechanical translation stage step distance need to coordinate mutually, otherwise may cause the phenomenon of repeated irradiation or missed irradiation.
The SoC is a system circuit integrating multiple functions, and from the functions and performance of the whole system, the integration of complex functions is realized on one chip by a design and verification method combining software and hardware. The SoC is used as a core component in an electronic system of the spacecraft and is a single event effect sensitive device, once the performance is unstable or fails due to the influence of radiation effect, the SoC can seriously threaten the operation of the spacecraft, so that the SoC is subjected to an irradiation simulation experiment to evaluate the performance of the single event radiation effect resistance, and is an important link of the radiation resistance reinforcement of the spacecraft.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method carries out comprehensive test on the working condition of the chip under the dynamic, static and reset states (called three states for short), realizes comprehensive and reasonable evaluation on the SoC single event effect, and is convenient to find the problem and accurately position the fault problem based on the test result by carrying out accurate hollow processing on the tested area.
The technical solution of the invention is as follows: the laser simulation single particle irradiation detection and fault positioning method for the SoC chip comprises the following steps in a reset mode:
(1-1) carrying out hole opening treatment on the back of the to-be-detected area of the SoC chip to expose a chip substrate;
(1-2) mounting the SoC chip with the hole on a test board, wherein the test board provides a configuration signal required by the SoC chip, so that the SoC chip can normally work after being electrified, the configuration signal comprises a power signal and a clock signal, and the clock signal is input to a PLL (phase locked loop) module of the SoC chip to generate a working clock of the SoC chip;
(1-3) grounding a reset pin of the chip to be tested, and then electrifying the SoC chip to start working;
(1-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
and (1-5) monitoring the waveform, the core current and the IO current of the SoC chip working clock, and when any one of the SoC chip working clock, the core current and the IO current is abnormal, determining that the area to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
The method further comprises the steps of in a static mode:
(2-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
(2-2) mounting the opened SoC chip on a test board, wherein the test board provides a configuration signal required by the SoC chip to be tested, so that the SoC chip can normally work after being electrified, and the configuration signal comprises a power supply signal;
(2-3) configuring a PLL bypass control signal of the SoC chip to be effective, connecting a clock input pin of the SoC chip to a high level, and then electrifying the SoC chip to start working;
(2-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
and (2-5) monitoring the core current and the IO current, and when any one of the core current and the IO current is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
The method further comprises the steps of in dynamic mode:
(3-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
(3-2) analyzing the internal structure of the SoC chip, and taking the functional module associated with the to-be-tested area of the SoC chip as a to-be-tested functional module;
(3-3) mounting the SoC chip to be tested on a test board, wherein the test board provides configuration signals necessary for enabling the SoC chip to be tested to normally work; the configuration signals comprise power signals, reset signals and clock signals;
(3-3) electrifying the SoC chip, and carrying out function test on the tested function module;
(3-4) aligning the back opening area of the SoC chip to be tested by adopting laser, and performing two-dimensional plane scanning irradiation;
and (3-5) monitoring the core current and the IO current, and when any one of the core current, the IO current and the function test result is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
The accuracy control of trompil is within 100 um.
The functional test steps are as follows:
(6.1) writing data or configuring initial values into all addresses of the tested functional module;
(6.2) traversing and reading back data of all addresses of the tested functional module and comparing the data with a written value or an initial value;
(6.3) when the comparison results are different, recording the condition that a single data bit is overturned;
and if the number of times of overturning of 1 data bit, 2 data bits or a plurality of data bits of the single data in the unit time exceeds a corresponding threshold, determining that the function test result is abnormal, otherwise, determining that the function test result is normal.
And if any one of the core current and the IO current is larger than the corresponding preset threshold, the core current and the IO current are considered to be abnormal.
And if the waveform amplitude and the frequency value deviation of the SoC chip working clock exceed the corresponding preset ranges, the SoC chip working clock is considered to be abnormal, otherwise, the SoC chip working clock is normal.
The other technical solution of the invention is as follows: SoC chip laser simulation single particle irradiation detection and fault location system, this system includes monitoring control equipment, SoC test panel, oscilloscope, programmable power supply and laser irradiator, wherein:
and the laser irradiator is used for providing a simulated single event effect irradiation environment and generating pulse laser to perform two-dimensional plane scanning on the selected area of the SoC chip.
The monitoring control equipment is used for burning and solidifying the compiled test program set to the SoC test board, selecting a corresponding functional test program according to an external input instruction to dynamically test the SoC chip in a dynamic test mode, receiving a functional test result sent by the SOC test board, collecting the current of the SOC test board, the core current of the SOC chip and the IO current sent by the programmable power supply, displaying the test result, the core current of the SOC chip and the IO current, and enabling an experimenter to judge a test condition by analyzing test data and current values and outputting waveforms so as to master an experimental process; once any one of the SOC test board current, the SOC chip kernel current and the IO current exceeds a corresponding set threshold, automatically alarming and cutting off a power supply to realize the automatic control of the on-off of the power supply;
the SOC test board completes the function test under the control of the function test program and sends the SOC test result to the monitoring control equipment;
and the program control power supply is used for providing a power supply for the SOC test board, detecting the current of the test board, the core current and the IO current of the SOC chip in real time and sending the current to the monitoring control equipment.
The SOC test board comprises an SOC chip, an SOC chip socket, an SRAM module, a PROM module, a reset module, a clock circuit, a power supply module and a communication module;
the SOC chip socket is matched with the pins of the SOC chip and is used for connecting the SOC chip and the SoC test board;
the PROM module is used for storing the function test program and loading the function test program into the SRAM module after being electrified;
the SRAM module loads a function test program stored in the PROM after being electrified;
the SOC chip reads and runs the test program in the SRAM module, and then sends a function test result obtained after the test program runs to the monitoring control equipment;
the reset module is connected with the pins of the SOC chip through a jumper wire and provides a reset signal for the SOC chip;
the clock circuit is connected with a PLL clock input pin of the SOC chip through a jumper wire and provides a clock signal for the SOC chip;
the power supply module is used for providing power supply for the SOC chip;
and the communication module is used for realizing data transmission between the SOC test board and the monitoring control equipment.
Compared with the prior art, the invention has the advantages that:
(1) the invention carries out back hole opening treatment on the test area of the chip to be tested, has high hole opening precision, effectively avoids the influence of larger laser spots on the non-test area, and improves the test and positioning precision.
(2) The invention carries out comprehensive function detection on the SoC circuit through three test modes of dynamic state, static state and reset state, enriches the experimental conditions and methods and has high experimental test coverage.
(3) Under the condition of dynamic test, the invention can purposefully select the module for testing according to the needs, is flexible and efficient, can observe the turnover error condition of the test chip in real time in the experimental process, and is convenient for analyzing the radiation resistance of different modules, thereby guiding the subsequent improved design of the SoC circuit.
(4) Under the condition of static test, the circuit has small static current and good stability, can avoid the continuous change of the current under the dynamic condition, can detect and find the tiny fluctuation of the current caused by laser irradiation in the experimental process, and accurately positions the condition of single particle latch.
(5) In the reset state, the invention ensures that the bidirectional pin of the chip has a stable input and output state by continuously and asynchronously resetting the chip, and prevents the bidirectional pin from influencing a test result due to the change of pin current caused by the change of the input and output state.
(6) The test board has the advantages that the test program of the test board is convenient to modify and debug, online downloading and programming are supported, serial port data and current detection values can be recorded and stored, and follow-up analysis and research are facilitated.
(7) The invention monitors the current and voltage in the irradiation process in real time, sets the upper limit threshold value of the current, automatically alarms once the upper limit threshold value is exceeded, avoids the omission of the latch-up phenomenon, and has the function of over-current-limiting automatic power-off at the same time, thereby preventing the chip from being damaged due to over-high current.
Drawings
FIG. 1 is a flowchart of a method for SoC laser simulation single particle irradiation detection and fault location according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a backside opening of a chip to be tested according to an embodiment of the invention;
fig. 3 is a schematic diagram of an SoC laser simulation single particle irradiation detection system according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, aiming at the difficulty of the testing technology of laser simulation single particle effect in the prior art, the invention provides a method for detecting laser simulation single particle irradiation and positioning faults of an SoC chip, which comprises three testing modes, namely a reset mode, a static mode and a dynamic mode, wherein the specific steps of each mode are as follows:
1. the steps in the reset mode:
(1-1) carrying out hole opening treatment on the back of the to-be-detected area of the SoC chip to expose a chip substrate;
the maximum scanning speed of the selected laser is 100um/s, the influence of the laser on a non-test area due to the process error of the hole opening is reduced, and the hole opening precision is best controlled within 100 um. When the area to be tested affects the bonding of the tube cores, the area to be tested can be divided into a plurality of sub-areas, and the plurality of SOC chip tests are respectively carried out on each sub-area to obtain a test result. As shown in fig. 1, when the region to be tested is the IO region of the chip, the IO region of the chip is located around, and all the IO regions are perforated, so that the dies cannot be bonded, the four chips are respectively hollowed out vertically and horizontally, the perforation processing can effectively avoid the laser spots from greatly affecting the non-test region, and the test and positioning accuracy is improved.
(1-2) mounting the SoC chip with the hole on a test board, wherein the test board provides a configuration signal required by the SoC chip, so that the SoC chip can normally work after being electrified, the configuration signal comprises a power signal and a clock signal, and the clock signal is input to a PLL (phase locked loop) module of the SoC chip to generate a working clock of the SoC chip;
(1-3) grounding a reset pin of the chip to be tested, and then electrifying the SoC chip to start working;
(1-4) mounting and fixing the test board on a laser test bed, and aligning laser to the hole opening area on the back of the SoC chip to perform two-dimensional plane scanning irradiation;
and (1-5) monitoring the waveform, the core current and the IO current of the SoC chip working clock, and when any one of the SoC chip working clock, the core current and the IO current is abnormal, determining that the area to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
And if any one of the core current and the IO current is larger than the corresponding preset threshold, the core current and the IO current are considered to be abnormal.
And if the waveform amplitude and the frequency value deviation of the SoC chip working clock exceed the corresponding preset ranges, the SoC chip working clock is considered to be abnormal, otherwise, the SoC chip working clock is normal.
2. The steps in the static mode:
(2-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
(2-2) mounting the SoC chip with the hole on a test board, wherein the test board provides a configuration signal required by the SoC chip to be tested, so that the SoC chip can normally work after being electrified, and the configuration signal comprises a power supply signal;
(2-3) connecting a clock input pin of the SoC chip to a high level, and then electrifying the SoC chip to start working;
(2-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
and (2-5) monitoring the core current and the IO current, and when any one of the core current and the IO current is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
And (4) judging the abnormity of the core current and the IO current by the same method as the judging method in the step (1-5).
3. The steps in dynamic mode:
(3-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
(3-2) analyzing the internal structure of the SoC chip, and taking the functional module associated with the to-be-tested area of the SoC chip as a to-be-tested functional module;
(3-3) mounting the SoC chip to be tested on a test board, wherein the test board provides configuration signals necessary for enabling the SoC chip to be tested to normally work; the configuration signals comprise power signals, reset signals and clock signals;
(3-3) electrifying the SoC chip, and carrying out function test on the tested function module;
for a memory module with a certain capacity capable of storing data, in order to detect that the memory module is knocked over in a laser simulation test, data in the memory module before and after laser irradiation needs to be directly compared, and the function test step can be as follows:
(3-3.1) writing data or configuring initial values into all addresses of the tested functional module;
(3-3.2) traversing and reading back the data of all the addresses of the tested functional module and comparing the data with the written value or the initial value;
(3-3.3) when the comparison results are different, recording the condition that a single data bit is overturned;
(3-4) aligning the back opening area of the SoC chip to be tested by adopting laser, and performing two-dimensional plane scanning irradiation;
and (3-5) monitoring the core current and the IO current, and when any one of the core current, the IO current and the function test result is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
Similarly, the method for judging the abnormity of the core current and the IO current is the same as the method for judging the abnormity of the core current and the IO current in the step (1-5). When the chip normally works, the current of each path is stabilized within a certain range, but the modes are different, and the fluctuation values of the core current and the IO current are different, so that the set threshold value is 1.5 times of the maximum value of the core current or the IO current under the working state corresponding to a certain mode, and once the threshold value exceeds the maximum value, the current is judged to be abnormal.
And (4) regarding the function test adopted in the step (3-3), if the number of times of overturning of 1 data bit, 2 data bits or a plurality of data bits of single data in unit time exceeds a corresponding threshold, the radiation resistance performance of the tested area is considered to be not satisfied. The laser irradiation was stopped, and the test was ended. Otherwise, the radiation resistance of the measured area is considered to meet the requirement.
The method effectively avoids the influence of larger laser spots on the non-test area, improves the test comprehensiveness and accuracy of the SoC chip, and facilitates accurate finding and positioning of the problems by analyzing test results in different states.
In order to meet the test universality in the three modes, the invention also provides a system for detecting the laser simulation single particle irradiation of the SoC chip and positioning the fault, which is used for carrying out the laser simulation single particle effect irradiation experiment on the SoC chip.
As shown in fig. 2, the SoC laser simulation single particle irradiation detection system is composed of a monitoring control device, an SoC test board, an oscilloscope, a programmable power supply and a laser irradiator.
The laser irradiator is used for providing a simulated single event effect irradiation environment and generating pulse laser to perform two-dimensional plane scanning on a selected area of the SoC chip;
the monitoring control equipment is used for burning and solidifying the compiled test program set to the SoC test board, dynamically testing the SoC chip by selecting a corresponding functional test program according to an external keying instruction (the keying instruction preferably adopts decimal numbers of 1-9) in a dynamic test mode, receiving a functional test result sent by the SOC test board, collecting SOC test board current, SOC chip core current and IO current sent by the programmable power supply, displaying the test result, the SOC chip core current and the IO current, and allowing an experimenter to judge a test condition by analyzing test data and current values and outputting waveforms so as to master an experimental process; once any one of the SOC test board current, the SOC chip kernel current and the IO current exceeds a corresponding set threshold, the automatic alarm is given and the power supply is cut off, so that the automatic control of the on-off of the power supply is realized.
The SOC test board completes the function test under the control of the function test program and sends the SOC test result to the monitoring control equipment;
and the program control power supply is used for providing a power supply for the SOC test board, detecting the current of the test board, the core current and the IO current of the SOC chip in real time and sending the current to the monitoring control equipment.
The SoC test board comprises an SOC chip, an SOC chip socket, an SRAM module, a PROM module, a reset module, a clock circuit, a power supply module and a communication module;
the SOC chip socket is matched with the pins of the SOC chip and is used for connecting the SOC chip and the SoC test board;
the PROM module is used for storing the function test program and loading the function test program into the SRAM module after being electrified;
the SRAM module loads a function test program stored in the PROM after being electrified;
the SOC reads and runs the test program in the SRAM module, and then sends a function test result obtained after the test program runs to the monitoring control equipment;
the reset module is connected with the pins of the SOC chip through a jumper wire and provides a reset signal for the SOC chip;
the clock circuit is connected with a PLL clock input pin of the SOC chip through a jumper wire and provides a clock signal for the SOC chip;
the power supply module is used for providing power supply for the SOC chip;
and the communication module is used for realizing data transmission between the SOC test board and the monitoring control equipment through the serial port.
The detection system is used for carrying out laser simulation single-particle effect irradiation experiments on the SoC chip, is convenient for mastering the test state of the chip in real time, and can test the working states of different regions and functional modules of the SoC.
By adopting the detection system and the detection method, the coverage rate of irradiation experiment test and the accuracy of fault location are improved through abundant experiment conditions and means, the influence of the state change of the chip on the experiment result is reduced, the micro fluctuation of the chip current in the experiment process is detected, and the radiation resistance is accurately evaluated, so that the subsequent improvement of the electric chip is guided.
The invention is not described in detail and is within the knowledge of a person skilled in the art.

Claims (8)

  1. The laser simulation single particle irradiation detection and fault positioning method for the SoC chip is characterized by comprising the following steps of:
    (1-1) carrying out hole opening treatment on the back of the to-be-detected area of the SoC chip to expose a chip substrate;
    (1-2) mounting the SoC chip with the hole on a test board, wherein the test board provides a configuration signal required by the SoC chip, so that the SoC chip can normally work after being electrified, the configuration signal comprises a power signal and a clock signal, and the clock signal is input to a PLL (phase locked loop) module of the SoC chip to generate a working clock of the SoC chip;
    (1-3) grounding a reset pin of the chip to be tested, and then electrifying the SoC chip to start working;
    (1-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
    (1-5) monitoring the waveform, the core current and the IO current of the SoC chip working clock, and when any one of the SoC chip working clock, the core current and the IO current is abnormal, determining that a region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test;
    the steps in the static mode:
    (2-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
    (2-2) mounting the opened SoC chip on a test board, wherein the test board provides a configuration signal required by the SoC chip to be tested, so that the SoC chip can normally work after being electrified, and the configuration signal comprises a power supply signal;
    (2-3) configuring a PLL bypass control signal of the SoC chip to be effective, connecting a clock input pin of the SoC chip to a high level, and then electrifying the SoC chip to start working;
    (2-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
    (2-5) monitoring the core current and the IO current, and when any one of the core current and the IO current is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test;
    the steps in dynamic mode:
    (3-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
    (3-2) analyzing the internal structure of the SoC chip, and taking the functional module associated with the to-be-tested area of the SoC chip as a to-be-tested functional module;
    (3-3) mounting the SoC chip to be tested on a test board, wherein the test board provides configuration signals necessary for enabling the SoC chip to be tested to normally work; the configuration signals comprise power signals, reset signals and clock signals;
    (3-3) electrifying the SoC chip, and carrying out function test on the tested function module;
    (3-4) aligning the back opening area of the SoC chip to be tested by adopting laser, and performing two-dimensional plane scanning irradiation;
    and (3-5) monitoring the core current and the IO current, and when any one of the core current, the IO current and the function test result is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
  2. 2. The SoC chip laser simulation single particle irradiation detection and fault location method according to claim 1, characterized in that the hole opening precision is controlled within 100 um.
  3. 3. The SoC chip laser simulation single particle irradiation detection and fault location method according to claim 1, characterized in that the functional test steps are:
    (6.1) writing data or configuring initial values into all addresses of the tested functional module;
    (6.2) traversing and reading back data of all addresses of the tested functional module and comparing the data with a written value or an initial value;
    and (6.3) when the comparison results are different, recording the condition that a single data bit is inverted.
  4. 4. The SoC chip laser simulation single particle irradiation detection and fault location method according to claim 3, wherein the number of times that a single data bit of 1, 2 or more data bits is or are flipped within a unit time exceeds a corresponding threshold, the functional test result is considered to be abnormal, otherwise, the functional test result is considered to be normal.
  5. 5. The SoC chip laser simulation single particle irradiation detection and fault location method according to claim 1, wherein any one of the core current and the IO current is greater than a corresponding preset threshold, and the core current and the IO current are considered to be abnormal.
  6. 6. The SoC chip laser simulation single particle irradiation detection and fault location method according to claim 1, wherein the deviation of the waveform amplitude and the frequency value of the SoC chip working clock exceeds a corresponding preset range, the SoC chip working clock is considered to be abnormal, otherwise, the SoC chip working clock is normal.
  7. The laser simulation single particle irradiation detection and fault positioning system for the SoC chip is characterized by comprising monitoring control equipment, a SoC test board, an oscilloscope, a programmable power supply and a laser irradiator, wherein:
    the laser irradiator is used for providing a simulated single event effect irradiation environment and generating pulse laser to perform two-dimensional plane scanning on a selected area of the SoC chip;
    the monitoring control equipment is used for burning and solidifying the compiled test program set to the SoC test board, selecting a corresponding functional test program according to an external input instruction to dynamically test the SoC chip in a dynamic test mode, receiving a functional test result sent by the SOC test board, collecting the current of the SOC test board, the core current of the SOC chip and the IO current sent by the programmable power supply, displaying the test result, the core current of the SOC chip and the IO current, and enabling an experimenter to judge a test condition by analyzing test data and current values and outputting waveforms so as to master an experimental process; once any one of the SOC test board current, the SOC chip kernel current and the IO current exceeds a corresponding set threshold, automatically alarming and cutting off a power supply to realize the automatic control of the on-off of the power supply;
    the SOC test board completes the function test under the control of the function test program and sends the SOC test result to the monitoring control equipment;
    the program control power supply is used for providing a power supply for the SOC test board, detecting the current of the test board, the core current of the SOC chip and the IO current in real time and sending the current to the monitoring control equipment;
    the steps in the reset mode:
    (1-1) carrying out hole opening treatment on the back of the to-be-detected area of the SoC chip to expose a chip substrate;
    (1-2) mounting the SoC chip with the hole on a test board, wherein the test board provides a configuration signal required by the SoC chip, so that the SoC chip can normally work after being electrified, the configuration signal comprises a power signal and a clock signal, and the clock signal is input to a PLL (phase locked loop) module of the SoC chip to generate a working clock of the SoC chip;
    (1-3) grounding a reset pin of the chip to be tested, and then electrifying the SoC chip to start working;
    (1-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
    (1-5) monitoring the waveform, the core current and the IO current of the SoC chip working clock, and when any one of the SoC chip working clock, the core current and the IO current is abnormal, determining that a region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test;
    the steps in the static mode:
    (2-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
    (2-2) mounting the opened SoC chip on a test board, wherein the test board provides a configuration signal required by the SoC chip to be tested, so that the SoC chip can normally work after being electrified, and the configuration signal comprises a power supply signal;
    (2-3) configuring a PLL bypass control signal of the SoC chip to be effective, connecting a clock input pin of the SoC chip to a high level, and then electrifying the SoC chip to start working;
    (2-4) aligning the hole opening area on the back of the SoC chip by adopting laser, and carrying out two-dimensional plane scanning irradiation;
    (2-5) monitoring the core current and the IO current, and when any one of the core current and the IO current is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test;
    the steps in dynamic mode:
    (3-1) carrying out hole opening treatment on the back of the to-be-detected region of the SoC chip to expose the chip substrate;
    (3-2) analyzing the internal structure of the SoC chip, and taking the functional module associated with the to-be-tested area of the SoC chip as a to-be-tested functional module;
    (3-3) mounting the SoC chip to be tested on a test board, wherein the test board provides configuration signals necessary for enabling the SoC chip to be tested to normally work; the configuration signals comprise power signals, reset signals and clock signals;
    (3-3) electrifying the SoC chip, and carrying out function test on the tested function module;
    (3-4) aligning the back opening area of the SoC chip to be tested by adopting laser, and performing two-dimensional plane scanning irradiation;
    and (3-5) monitoring the core current and the IO current, and when any one of the core current, the IO current and the function test result is abnormal, determining that the region to be tested of the SOC chip has a fault, stopping laser irradiation and finishing the test.
  8. 8. The system for detecting and locating the faults by irradiating the laser simulation single particles on the SoC chip according to claim 7, wherein the SOC test board comprises an SOC chip, an SOC chip socket, an SRAM module, a PROM module, a reset module, a clock circuit, a power supply module and a communication module;
    the SOC chip socket is matched with the pins of the SOC chip and is used for connecting the SOC chip and the SoC test board;
    the PROM module is used for storing the function test program and loading the function test program into the SRAM module after being electrified;
    the SRAM module loads a function test program stored in the PROM after being electrified;
    the SOC chip reads and runs the test program in the SRAM module, and then sends a function test result obtained after the test program runs to the monitoring control equipment;
    the reset module is connected with the pins of the SOC chip through a jumper wire and provides a reset signal for the SOC chip;
    the clock circuit is connected with a PLL clock input pin of the SOC chip through a jumper wire and provides a clock signal for the SOC chip;
    the power supply module is used for providing power supply for the SOC chip;
    and the communication module is used for realizing data transmission between the SOC test board and the monitoring control equipment.
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110221143A (en) * 2019-05-29 2019-09-10 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) A kind of measured device soft error discriminating method, device and computer equipment
CN110361618A (en) * 2019-08-07 2019-10-22 中国科学院新疆理化技术研究所 One kind being used for cmos image sensor single event latch-up effect test method
CN110456258B (en) * 2019-09-05 2021-12-31 上海航天计算机技术研究所 Device and method for testing single event effect resistance of flip chip
CN110972405B (en) * 2019-11-29 2021-04-09 苏州热工研究院有限公司 Method and device for preventing silver ion electromigration of nuclear-grade circuit board of nuclear power plant
CN111667877B (en) * 2020-04-28 2023-01-17 中国科学院微电子研究所 Memory test circuit, test system and test method
CN114910689B (en) * 2022-07-12 2022-09-30 沐曦集成电路(上海)有限公司 Real-time monitoring method for chip current

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101299446A (en) * 2008-05-30 2008-11-05 南开大学 Selenide forerunner thin film and method for producing film cell through rapid selenium vulcanizing thermal treatment
WO2007141796A3 (en) * 2006-06-09 2010-12-16 Quark Pharmaceuticals, Inc. Therapeutic uses of inhibitors of rtp801l
US8037383B2 (en) * 2004-02-06 2011-10-11 Texas Instruments Incorporated Gating circuitry coupling selected scan paths between I/O scan bus
CN103021469A (en) * 2012-11-30 2013-04-03 北京时代民芯科技有限公司 Universal single event effect detecting method of memory circuit
CN103744014A (en) * 2013-12-24 2014-04-23 北京微电子技术研究所 SRAM type FPGA single particle irradiation test system and method
CN105188934A (en) * 2012-12-07 2015-12-23 Isis创新有限公司 Droplet assembly by 3D printing
CN108171317A (en) * 2017-11-27 2018-06-15 北京时代民芯科技有限公司 A kind of data-reusing convolutional neural networks accelerator based on SOC
CN108226748A (en) * 2017-12-05 2018-06-29 上海精密计量测试研究所 For the single particle effect test method of SoC systems on chip
CN108535626A (en) * 2017-12-29 2018-09-14 北京时代民芯科技有限公司 A kind of full-automatic testing device and method of the test of SOC single-particles

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5227502B2 (en) * 2006-09-15 2013-07-03 株式会社半導体エネルギー研究所 Liquid crystal display device driving method, liquid crystal display device, and electronic apparatus
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8037383B2 (en) * 2004-02-06 2011-10-11 Texas Instruments Incorporated Gating circuitry coupling selected scan paths between I/O scan bus
WO2007141796A3 (en) * 2006-06-09 2010-12-16 Quark Pharmaceuticals, Inc. Therapeutic uses of inhibitors of rtp801l
CN101299446A (en) * 2008-05-30 2008-11-05 南开大学 Selenide forerunner thin film and method for producing film cell through rapid selenium vulcanizing thermal treatment
CN103021469A (en) * 2012-11-30 2013-04-03 北京时代民芯科技有限公司 Universal single event effect detecting method of memory circuit
CN105188934A (en) * 2012-12-07 2015-12-23 Isis创新有限公司 Droplet assembly by 3D printing
CN103744014A (en) * 2013-12-24 2014-04-23 北京微电子技术研究所 SRAM type FPGA single particle irradiation test system and method
CN108171317A (en) * 2017-11-27 2018-06-15 北京时代民芯科技有限公司 A kind of data-reusing convolutional neural networks accelerator based on SOC
CN108226748A (en) * 2017-12-05 2018-06-29 上海精密计量测试研究所 For the single particle effect test method of SoC systems on chip
CN108535626A (en) * 2017-12-29 2018-09-14 北京时代民芯科技有限公司 A kind of full-automatic testing device and method of the test of SOC single-particles

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