CN102981093A - Test system for central processing unit (CPU) module - Google Patents
Test system for central processing unit (CPU) module Download PDFInfo
- Publication number
- CN102981093A CN102981093A CN2012104630044A CN201210463004A CN102981093A CN 102981093 A CN102981093 A CN 102981093A CN 2012104630044 A CN2012104630044 A CN 2012104630044A CN 201210463004 A CN201210463004 A CN 201210463004A CN 102981093 A CN102981093 A CN 102981093A
- Authority
- CN
- China
- Prior art keywords
- cpu module
- test
- circuit
- power
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a test system for a central processing unit (CPU) module. The system comprises a computer test host and a test device of the CPU module, wherein the computer test host accesses a CPU state register on the to-be-tested CPU module and executes test programs due to the fact that a universal serial bus (USB) data line penetrates through the test device of the CPU module. The test device of the CPU module comprises a test interface of the CPU module, USB debugging sub-interface, a power control circuit, a USB main interface test circuit, an external expansion bus test circuit, an input/output (IO) test circuit, an Ethernet interface test circuit, and a clock backup power test circuit. The test system not only achieves a test for quality of the CPU module, but also can locate specific faulty lines and chips. By means of the power control circuit, delayed electrifying protection of the to-be-tested CUP module and a power short circuit test can be achieved, and therefore hot plugging in the test process is achieved. The whole test system is simple in structure and convenient to operate.
Description
Technical field
The present invention relates to a kind of test macro for the CPU module, belong to electronic products manufacturing technology field.
Background technology
After making sheet welding, need to carry out full test in the CPU module, the quality problems such as the CPU module of being produced to guarantee do not have short circuit, open circuit.The method of testing of existing CPU module, CPU module to be measured can only be inserted application apparatus after, carry out complete machine function and performance test.If complete machine breaks down, repair after the replacing CPU module, then confirm former CPU module damage.This method of testing, operating process is complicated, can not directly locate the quality problems such as faulty line concrete on the CPU module, chip damage, can't Welding Problems be repaired targetedly, and testing efficiency is low.Current C PU function is more and more stronger, and the CPU pin is many, CPU module complex circuit.Must design the special test system for the CPU module, realize fast and convenient measuring ability, accurately locate failure problems, thereby realize the Welding Problems reparation, solve fault.Simultaneously, cpu performance improves thereupon, and CPU has USB debugging interface built-in or that extend out, computer can be by the status register of this interface accessing CPU, control program loads and operation, is that project organization is simple, the novel C PU module test system of simple operation thus, and technical foundation is provided.
Summary of the invention
The purpose of this invention is to provide a kind of test macro for the CPU module, to solve at present since the CPU pin mainly with and the problem such as complex circuit, cause the test operation flow process complicated, can not directly locate the problems such as faulty line concrete on the CPU module.
The present invention provides a kind of test macro for the CPU module for solving the problems of the technologies described above, and this test macro comprises:
The computer test main frame, for the status register of accessing CPU on the CPU module to be measured, loading and the operation of control test procedure on CPU to be measured;
The CPU module test device is connected with described computer test main frame by the USB connecting line, is used to CPU module to be measured that the test circuit of power supply and expansion is provided;
CPU module testing interface is connected with CPU module to be measured with described CPU module test device, is used for the respective signal line of the signal wire on the CPU module test device and CPU module to be measured is coupled together;
Described CPU module test device comprises: USB debugs from interface, and the input of this interface links to each other with the USB interface of described computer test main frame by the USB connecting line, and output links to each other from mouth with the USB debugging of CPU module to be measured by CPU module testing interface; Power control circuit, the input of this power control circuit links to each other with the power signal line of described USB debugging from interface, output links to each other with the power signal line of CPU module to be measured by CPU module testing interface, and being used for realization provides working power to the protection of computer test main frame USB interface and for CPU module to be measured; USB main interface test circuit, extend out bus test circuit, IO test circuit and Ethernet interface test circuit, they are connected with each self-corresponding signal wire in the CPU module testing interface respectively, USB main interface test circuit, extend out bus test circuit, IO test circuit and Ethernet interface test circuit and are all powered by power control circuit.
Described power control circuit comprises power protecting circuit, DC power-switching circuit, time-delay power-supplying circuit and short-circuit alarming circuit; the power protecting circuit input end links to each other with the 5V power signal line from interface by the USB debugging; output connects the DC power-switching circuit; be converted to the working power voltage of CPU module to be measured by the DC power-switching circuit, described short-circuit alarming circuit is connected in parallel on the power signal line of CPU module testing interface input.
Described time-delay power-supplying circuit comprises timer control circuit and controlled power switch, the input end of timer control circuit links to each other with the output terminal of DC power-switching circuit, the output terminal of timer control circuit is used for linking to each other with the power supply of CPU module to be measured, and the control end of timer control circuit links to each other with an IO signal wire of CPU module testing interface.
Described Ethernet interface test circuit comprises network transformer and gate-controlled switch, the input end of network transformer links to each other with the ethernet signal end of CPU module testing interface, the transmitted signal end of network transformer and reception signal end link together by gate-controlled switch, and the control end of gate-controlled switch links to each other with an IO of CPU module testing interface.
Described USB main interface test circuit comprises a USB storage, and the signal wire of this USB storage is connected with USB master's mouth signal wire of CPU module testing interface, is used for realization to the test of the USB main interface function on the CPU module to be measured.
Described IO test circuit comprises working power, a pull-up resistor and N-1 current-limiting resistance, the output terminal of working power links to each other with the output terminal of DC power-switching circuit, the positive voltage signal end of working power links to each other through an IO signal wire of a pull-up resistor and CPU module testing interface, this IO signal wire is being connected with all the other N-1 IO signal wires of CPU module testing interface respectively through N-1 current-limiting resistance, and N is the number of the IO signal wire in the CPU module testing interface.
Also comprise clock back-up source test circuit in the described CPU module test device, the input end of this clock back-up source test circuit links to each other with the output terminal of DC power supply conversion, and output terminal is connected with the clock back-up source signal wire of CPU module testing interface.
The invention has the beneficial effects as follows: test macro of the present invention comprises computer test main frame and CPU module test device, and the computer test main frame is realized status register access and the test procedure of CPU on the CPU module to be measured are carried out through the CPU module test device by the usb data line; The CPU module test device by CPU module testing interface, USB debugging from interface, power control circuit, USB main interface test circuit, extend out bus test circuit, IO test circuit, Ethernet interface test circuit and clock back-up source test circuit and form.The present invention has not only realized the test to the CPU module quality, and can locate circuit and the chip position of concrete fault; Realized that by power control circuit electric protection and power supply short circuit detect in the time-delay of CPU module to be measured, thereby realized the warm swap of testing process; Simple in structure, the simple operation of whole proving installation.
Description of drawings
Fig. 1 is the structured flowchart that the present invention is directed to the test macro of CPU module;
Fig. 2 is the structured flowchart of the power control circuit in the embodiment of the invention;
Fig. 3 is the structured flowchart of IO test circuit in the embodiment of the invention;
Fig. 4 is the structural drawing of Ethernet interface test circuit in the embodiment of the invention;
Fig. 5 is for the test operation process flow diagram of the test macro of CPU module in the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is further described.
The general structure block diagram of the embodiment of the invention as shown in Figure 1, the test macro of this CPU module comprises computer test main frame and CPU module test device, wherein following interface and the electric circuit constitute of CPU module test device.
CPU module testing interface, debug from mouth signal wire, USB master's mouth signal wire, extend out bus signal line, IO signal wire, ethernet signal line, the corresponding connection of clock back-up source signal wire, and couple together by socket and CPU module respective signal line to be measured with power signal line, the USB of CPU module test device by patching pin.
The USB debugging connects the computer test main frame from interface by data line, and input connects computer test main frame USB interface, and output connects the USB debugging of CPU module to be measured from the mouth signal wire, in order to realize the debugging mode access to the CPU on the CPU module to be measured.Simultaneously, the 5V power signal line of USB interface, the power control circuit of access CPU module test device is for whole proving installation provides working power.
Power control circuit, as shown in Figure 2, by power protecting circuit, DC power-switching circuit, time-delay power-supplying circuit, short-circuit alarming the electric circuit constitute.From interface access 5V power signal line, output connects the DC power-switching circuit, in order to protect the power supply of CPU module to be measured by the USB debugging in the power protecting circuit input.The DC power-switching circuit adopts the DC-DC translation circuit, will from the 5V voltage signal of power protecting circuit input, be converted to the 3.3V working power voltage of CPU module to be measured.
Time-delay power-supplying circuit in the power control circuit forms based on timer and controlled power switch.The startup control signal of timer is connected with an IO signal wire IO1 of CPU module testing interface, and when CPU module to be measured was not connected with the CPU module testing interface of CPU module test device, the IO1 signal was invalid high level.When the IO1 signal was high level, timer did not start, and its output signal power ratio control switch disconnects, thereby to the power signal line Non voltage output of CPU module output to be measured.After CPU module to be measured was passed through CPU module testing interface and the CPU module test device is connected, before the CPU module loading program to be measured, IO1 kept low level.Thus, when the IO1 signal became low level from high level, timer will be through power ratio control switch conduction again after the time of setting, and the power signal line of CPU module testing interface is given CPU module for power supply to be measured.The time-delay of this section setting is used for realizing the hot plug of CPU module and CPU module test device, when having avoided interface not stablize, powers on for too early CPU module to be measured, causes the electrifying timing sequence mistake, the stability of impact test.
Time-delay power-supplying circuit in the power control circuit also is used for the clock back-up source of CPU module to be measured is tested.The computer test main frame can be controlled IO1 and switch to high level output by the status register of CPU on the CPU module to be measured is set, thereby initiatively cuts off CPU module for power supply to be measured by power switch.Because after the CPU module to be measured outage, IO1 recovers again low level, so timer will through time of setting conducting power switch again, power on to CPU module to be measured.CPU module power process to be measured if the clock back-up source is normal, does not then affect the continuation timing of clock.If open circuit fault appears in the clock back-up source, then timing resets.Thus, by the clock timing value of CPU module more to be measured before and after outage, can detect and judge the quality problems of clock back-up source part.
Short-circuit alarming circuit in the power control circuit also is connected on the power signal line of CPU module testing interface input.When the power signal line short circuit, will control the IO1 invalidating signal and cut off power supply, and trigger the hummer sounding alarm.
USB main interface test circuit, the USB storage of employing 1G, the signal wire of this USB storage is connected with USB master's mouth signal wire of CPU module testing interface.USB main interface on the CPU module to be measured is by writing the data with this USB storage of read access, the quality problems of check USB main interface.
Extend out the bus test circuit, adopt the SRAM memory circuit that expands to 32 bit address lines, 32 position datawires, the bus of this storer is connected with the bus signal line that extends out of CPU module testing interface.Extend out bus by writing the data with this storer of read access on the CPU module to be measured, check extends out the quality problems of bus.
The IO test circuit, circuit diagram as shown in Figure 3, this circuit is connected with the IO signal wire of CPU module testing interface, wherein 1 IO signal wire IO2 connects working power 3.3V voltage signal through 330 Ω pull-up resistors, and this IO signal wire connects respectively every IO signal wires such as PA0, PA1, PA2 through a current-limiting resistance 1k Ω simultaneously.By computer test host computer control CPU module produce the pps pulse per second signal of 1 second cycle, dutycycle 50% with the pulse control signal line, all IO are during as input, when pulse per second (PPS) when being high, all IO should input 1.When pulse per second (PPS) when low, all IO should input 0.Select successively an IO as output state x=1 or 0, remaining does input, and enables to draw, and checks all the other IO whether still to remain x.If all consistent, then detect normal.If there is inconsistent, detect to find that then IO cabling on the CPU module opens circuit or the open circuit conditions of power lead.
Ethernet interface test circuit, structural drawing as shown in Figure 4, this circuit is comprised of network transformer and gate-controlled switch.The input signal cable of network transformer is connected with the ethernet signal line of CPU module testing interface, in order to realize the output of RJ45 network interface signal driver.The transmitted signal line of network transformer output and reception signal wire link together by gate-controlled switch.The control end of gate-controlled switch is connected with an IO signal wire IO3 of CPU module testing interface.When the IO3 signal was effective, gate-controlled switch was closed, and this moment, the Ethernet interface transmitting-receiving of CPU module to be measured was closed, if trace routine is identical with the Ethernet receive data by the data that Ethernet sends, then detected correct.During the IO3 invalidating signal, gate-controlled switch disconnects, and this moment, Ethernet had receive data, then illustrates to have transceiving data line short trouble on the circuit board when sending data when trace routine by Ethernet.
Clock back-up source test circuit, this circuit input connects the output of DC power-switching circuit, and output connects the clock back-up source signal wire of CPU module testing interface.This main circuit provides the clock back-up source will for CPU module to be measured, cooperates the time-delay power-supplying circuit in the aforementioned power source control circuit, can realize the detection to clock chip and circuit on the CPU module to be measured.
Based on present embodiment for the test operation flow process of CPU module as shown in Figure 5, concrete testing procedure is as follows:
Step 1: connect CPU module test device and computer test main frame by the USB connecting line, the operation testing software;
Step 2: connect CPU module test device and CPU module to be measured by CPU module testing interface;
Step 3: wait for the CPU module delayed to be measured that the time-delay power-supplying circuit sets;
Step 4: whether ring by short-circuit alarming circuit judges hummer, if the expression of ringing has the power supply short circuit situation, can stop test; If hummer is not rung, then continue next step detection;
Step 5: control access and the program implementation of CPU status register on the CPU module to be measured by testing software, whether the work that detect the USB main interface, extends out bus, IO, Ethernet, clock and clock back-up source is normal;
Step 6: test finishes, and disconnects CPU module to be measured from CPU module testing interface.
Claims (7)
1. test macro for the CPU module, it is characterized in that: this test macro comprises:
The computer test main frame, for the status register of accessing CPU on the CPU module to be measured, loading and the operation of control test procedure on CPU to be measured;
The CPU module test device is connected with described computer test main frame by the USB connecting line, is used to CPU module to be measured that the test circuit of power supply and expansion is provided;
CPU module testing interface is connected with CPU module to be measured with described CPU module test device, is used for the respective signal line of the signal wire on the CPU module test device and CPU module to be measured is coupled together;
Described CPU module test device comprises: USB debugs from interface, and the input of this interface links to each other with the USB interface of described computer test main frame by the USB connecting line, and output links to each other from mouth with the USB debugging of CPU module to be measured by CPU module testing interface; Power control circuit, the input of this power control circuit links to each other with the power signal line of described USB debugging from interface, output links to each other with the power signal line of CPU module to be measured by CPU module testing interface, and being used for realization provides working power to the protection of computer test main frame USB interface and for CPU module to be measured; USB main interface test circuit, extend out bus test circuit, IO test circuit and Ethernet interface test circuit, they are connected with each self-corresponding signal wire in the CPU module testing interface respectively, USB main interface test circuit, extend out bus test circuit, IO test circuit and Ethernet interface test circuit and are all powered by power control circuit.
2. the test macro for the CPU module according to claim 1; it is characterized in that: described power control circuit comprises power protecting circuit, DC power-switching circuit, time-delay power-supplying circuit and short-circuit alarming circuit; the power protecting circuit input end links to each other with the 5V power signal line from interface by the USB debugging; output connects the DC power-switching circuit; be converted to the working power voltage of CPU module to be measured by the DC power-switching circuit, described short-circuit alarming circuit is connected in parallel on the power signal line of CPU module testing interface input.
3. the test macro for the CPU module according to claim 2, it is characterized in that: described time-delay power-supplying circuit comprises timer control circuit and controlled power switch, the input end of timer control circuit links to each other with the output terminal of DC power-switching circuit, the output terminal of timer control circuit is used for linking to each other with the power supply of CPU module to be measured, and the control end of timer control circuit links to each other with an IO signal wire of CPU module testing interface.
4. the test macro for the CPU module according to claim 3, it is characterized in that: described Ethernet interface test circuit comprises network transformer and gate-controlled switch, the input end of network transformer links to each other with the ethernet signal end of CPU module testing interface, the transmitted signal end of network transformer and reception signal end link together by gate-controlled switch, and the control end of gate-controlled switch links to each other with an IO of CPU module testing interface.
5. the test macro of CPU module according to claim 3, it is characterized in that: described USB main interface test circuit comprises a USB storage, the signal wire of this USB storage is connected with USB master's mouth signal wire of CPU module testing interface, is used for realization to the test of the USB main interface function on the CPU module to be measured.
6. the test macro of CPU module according to claim 3, it is characterized in that: described IO test circuit comprises working power, a pull-up resistor and N-1 current-limiting resistance, the output terminal of working power links to each other with the output terminal of DC power-switching circuit, the positive voltage signal end of working power links to each other through an IO signal wire of a pull-up resistor and CPU module testing interface, this IO signal wire is being connected with all the other N-1 IO signal wires of CPU module testing interface respectively through N-1 current-limiting resistance, and N is the number of the IO signal wire in the CPU module testing interface.
7. the test macro of CPU module according to claim 3, it is characterized in that: also comprise clock back-up source test circuit in the described CPU module test device, the input end of this clock back-up source test circuit links to each other with the output terminal of DC power supply conversion, and output terminal is connected with the clock back-up source signal wire of CPU module testing interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210463004.4A CN102981093B (en) | 2012-11-16 | 2012-11-16 | Test system for central processing unit (CPU) module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210463004.4A CN102981093B (en) | 2012-11-16 | 2012-11-16 | Test system for central processing unit (CPU) module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102981093A true CN102981093A (en) | 2013-03-20 |
| CN102981093B CN102981093B (en) | 2015-01-14 |
Family
ID=47855301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210463004.4A Active CN102981093B (en) | 2012-11-16 | 2012-11-16 | Test system for central processing unit (CPU) module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102981093B (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337846A (en) * | 2013-06-19 | 2013-10-02 | 深圳市元征科技股份有限公司 | Peripheral application circuit |
| CN103389438A (en) * | 2013-07-30 | 2013-11-13 | 天津七一二通信广播有限公司 | Welding detection system and welding detection method for circuit board with CPU |
| CN104297619A (en) * | 2014-10-13 | 2015-01-21 | 上海移为通信技术有限公司 | Testing device for chip input and output pin |
| CN104345857A (en) * | 2013-08-01 | 2015-02-11 | 鸿富锦精密电子(天津)有限公司 | Short-circuit protection circuit |
| CN104598350A (en) * | 2013-10-31 | 2015-05-06 | 上海华虹集成电路有限责任公司 | Contact-type CPU chip production testing method |
| CN105808392A (en) * | 2014-12-29 | 2016-07-27 | 比亚迪股份有限公司 | One-chip microcomputer, method and device for tracking and positioning error in operation process of one-chip microcomputer |
| CN106771984A (en) * | 2017-02-20 | 2017-05-31 | 华东师范大学 | A kind of high speed circuit board intelligent test device |
| CN106841843A (en) * | 2016-12-13 | 2017-06-13 | 硅谷数模半导体（北京）有限公司 | State simulation circuit and USB C interface method of testings |
| CN107515341A (en) * | 2017-09-11 | 2017-12-26 | 歌尔科技有限公司 | A kind of test board |
| CN108089073A (en) * | 2016-11-22 | 2018-05-29 | 技嘉科技股份有限公司 | Measuring fixture and the method for switching test system state |
| CN108280004A (en) * | 2018-01-22 | 2018-07-13 | 郑州云海信息技术有限公司 | A kind of SXM2 GPU link tests board and test method |
| CN109787358A (en) * | 2019-01-18 | 2019-05-21 | 南京深科博业电气股份有限公司 | Self-powered intelligent comprehensive protection location based on Micro USB |
| CN110798370A (en) * | 2018-08-02 | 2020-02-14 | 中国长城科技集团股份有限公司 | Bus protocol debugging method and device based on universal interface and terminal equipment |
| CN114441992A (en) * | 2021-12-29 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Test fixture, test device and test method for transmission cable line sequence |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4433413A (en) * | 1981-10-22 | 1984-02-21 | Siemens Corporation | Built-in apparatus and method for testing a microprocessor system |
| JPS6195456A (en) * | 1984-10-17 | 1986-05-14 | Nippon Radiator Co Ltd | Testing device of microcomputer |
| US5787270A (en) * | 1995-11-15 | 1998-07-28 | Advanced Micro Devices | Method and apparatus for intrusive testing of the performance-enhancing features of an advanced microprocessor |
| US20050172172A1 (en) * | 2004-01-15 | 2005-08-04 | International Business Machines Corporation | Processor error detection |
| CN1667581A (en) * | 2004-03-08 | 2005-09-14 | 鸿富锦精密工业（深圳）有限公司 | Motherboard function test board |
| CN1818883A (en) * | 2005-02-07 | 2006-08-16 | 中国科学院计算技术研究所 | Tester for MIPS processor |
| CN101221525A (en) * | 2007-01-08 | 2008-07-16 | 上海杰得微电子有限公司 | Testing and developing device of multimedia application processor |
| CN102346701A (en) * | 2010-08-02 | 2012-02-08 | 英业达股份有限公司 | Power supply test system for CPU (Central Processing Unit) |
-
2012
- 2012-11-16 CN CN201210463004.4A patent/CN102981093B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4433413A (en) * | 1981-10-22 | 1984-02-21 | Siemens Corporation | Built-in apparatus and method for testing a microprocessor system |
| JPS6195456A (en) * | 1984-10-17 | 1986-05-14 | Nippon Radiator Co Ltd | Testing device of microcomputer |
| US5787270A (en) * | 1995-11-15 | 1998-07-28 | Advanced Micro Devices | Method and apparatus for intrusive testing of the performance-enhancing features of an advanced microprocessor |
| US20050172172A1 (en) * | 2004-01-15 | 2005-08-04 | International Business Machines Corporation | Processor error detection |
| CN1667581A (en) * | 2004-03-08 | 2005-09-14 | 鸿富锦精密工业（深圳）有限公司 | Motherboard function test board |
| CN1818883A (en) * | 2005-02-07 | 2006-08-16 | 中国科学院计算技术研究所 | Tester for MIPS processor |
| CN101221525A (en) * | 2007-01-08 | 2008-07-16 | 上海杰得微电子有限公司 | Testing and developing device of multimedia application processor |
| CN102346701A (en) * | 2010-08-02 | 2012-02-08 | 英业达股份有限公司 | Power supply test system for CPU (Central Processing Unit) |
Non-Patent Citations (2)
| Title |
|---|
| 关国梁 等: "微处理器测试系统设计", 《小型微型计算机系统》, vol. 24, no. 8, 31 August 2003 (2003-08-31), pages 1555 - 1558 * |
| 张厚明: "集成电路制造厂的CPU测试", 《微电子学与计算机》, no. 12, 31 December 1986 (1986-12-31), pages 19 - 23 * |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337846A (en) * | 2013-06-19 | 2013-10-02 | 深圳市元征科技股份有限公司 | Peripheral application circuit |
| CN103389438A (en) * | 2013-07-30 | 2013-11-13 | 天津七一二通信广播有限公司 | Welding detection system and welding detection method for circuit board with CPU |
| CN103389438B (en) * | 2013-07-30 | 2015-11-25 | 天津七一二通信广播有限公司 | A kind of for the welding detection system with cpu pcb and method |
| CN104345857A (en) * | 2013-08-01 | 2015-02-11 | 鸿富锦精密电子(天津)有限公司 | Short-circuit protection circuit |
| CN104598350A (en) * | 2013-10-31 | 2015-05-06 | 上海华虹集成电路有限责任公司 | Contact-type CPU chip production testing method |
| CN104598350B (en) * | 2013-10-31 | 2016-08-17 | 上海华虹集成电路有限责任公司 | Contact type CPU chip production method of testing |
| CN104297619B (en) * | 2014-10-13 | 2017-01-18 | 上海移为通信技术股份有限公司 | Testing device for chip input and output pin |
| CN104297619A (en) * | 2014-10-13 | 2015-01-21 | 上海移为通信技术有限公司 | Testing device for chip input and output pin |
| CN105808392B (en) * | 2014-12-29 | 2019-09-13 | 比亚迪股份有限公司 | Wrong tracking positioning method and device in single-chip microcontroller and its operation |
| CN105808392A (en) * | 2014-12-29 | 2016-07-27 | 比亚迪股份有限公司 | One-chip microcomputer, method and device for tracking and positioning error in operation process of one-chip microcomputer |
| CN108089073A (en) * | 2016-11-22 | 2018-05-29 | 技嘉科技股份有限公司 | Measuring fixture and the method for switching test system state |
| CN108089073B (en) * | 2016-11-22 | 2020-03-10 | 技嘉科技股份有限公司 | Measuring tool and method for switching state of device to be measured |
| CN106841843A (en) * | 2016-12-13 | 2017-06-13 | 硅谷数模半导体（北京）有限公司 | State simulation circuit and USB C interface method of testings |
| CN106771984A (en) * | 2017-02-20 | 2017-05-31 | 华东师范大学 | A kind of high speed circuit board intelligent test device |
| CN107515341A (en) * | 2017-09-11 | 2017-12-26 | 歌尔科技有限公司 | A kind of test board |
| CN107515341B (en) * | 2017-09-11 | 2024-04-02 | 歌尔科技有限公司 | Test board |
| CN108280004A (en) * | 2018-01-22 | 2018-07-13 | 郑州云海信息技术有限公司 | A kind of SXM2 GPU link tests board and test method |
| CN108280004B (en) * | 2018-01-22 | 2021-10-29 | 郑州云海信息技术有限公司 | SXM2 GPU link test board card and test method |
| CN110798370A (en) * | 2018-08-02 | 2020-02-14 | 中国长城科技集团股份有限公司 | Bus protocol debugging method and device based on universal interface and terminal equipment |
| CN109787358A (en) * | 2019-01-18 | 2019-05-21 | 南京深科博业电气股份有限公司 | Self-powered intelligent comprehensive protection location based on Micro USB |
| CN114441992A (en) * | 2021-12-29 | 2022-05-06 | 苏州浪潮智能科技有限公司 | Test fixture, test device and test method for transmission cable line sequence |
| CN114441992B (en) * | 2021-12-29 | 2024-01-26 | 苏州浪潮智能科技有限公司 | Test fixture, test device and test method for cable sequence of transmission line |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102981093B (en) | 2015-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102981093B (en) | Test system for central processing unit (CPU) module | |
| CN102401879B (en) | The method of testing of the USB function of chip, Test Host and test macro | |
| CN107153591B (en) | Detection method and device for power supply architecture of memory | |
| TWI449936B (en) | Testing device for main board | |
| CN102929755B (en) | Fault detection method of CPU (Central Processing Unit) module address and data bus | |
| CN104346254A (en) | I<2>C bus monitoring device | |
| CN206673990U (en) | A kind of detecting system of communication message | |
| CN105259863A (en) | PLC warm backup redundancy method and system | |
| CN103699112A (en) | Aviation electronic self-detection verification equipment based on IO (Input/Output) signal failure simulation, and verification method of equipment | |
| CN105185415A (en) | Method and device for testing EEPROM of I2C | |
| CN106226679A (en) | For detecting frock and the method for testing thereof of embedded pos payment terminal mainboard | |
| CN104459386A (en) | Tester for USB data line | |
| CN104331061A (en) | Test method and test device of core board of distribution network terminal device | |
| CN105354157A (en) | Method, device and system for configuring IIC (Inter-Integrated Circuit) device | |
| CN105445604A (en) | USB 3.1 C type cable automatic test method | |
| CN108802627A (en) | Test method, device, system and readable storage medium storing program for executing independently-powered BBU | |
| CN211148838U (en) | Air conditioner internal unit testing device | |
| CN101793934B (en) | Universal anti-drawing test equipment and test method thereof | |
| CN103149468A (en) | Electron component parameter testing device | |
| WO2023184830A1 (en) | Control circuit, method, and apparatus for backup battery unit, and storage system | |
| CN107918069B (en) | Power failure test system and method | |
| CN113806148B (en) | Quick peripheral component interconnect socket detection system | |
| CN204117136U (en) | Processor module pick-up unit and system | |
| CN104134464A (en) | System and method for testing address line | |
| CN103531002B (en) | A kind of remote debugging method based on TD-SCDMA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |