CN108336059A - 用于集成电路失效保护熔丝封装的方法及设备 - Google Patents

用于集成电路失效保护熔丝封装的方法及设备 Download PDF

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CN108336059A
CN108336059A CN201711452772.9A CN201711452772A CN108336059A CN 108336059 A CN108336059 A CN 108336059A CN 201711452772 A CN201711452772 A CN 201711452772A CN 108336059 A CN108336059 A CN 108336059A
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fuse element
integrated circuit
cavity
terminal
circuit die
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CN108336059B (zh
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B·J·马莱
史蒂夫·库默尔
B·S·库克
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Texas Instruments Inc
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Abstract

本发明涉及用于集成电路失效保护熔丝封装的方法及设备。在所描述的实例中，一种设备(图1A，100)包含：集成电路裸片(116)，其具有多个端子；所述集成电路裸片(116)位于具有用于外部连接的引线(112)的引线框的裸片垫部分(118)上，所述引线(112)中的至少一些具有电耦合到所述集成电路裸片(116)的至少一个端子的内部部分；熔丝元件(120)，其耦合在所述引线框(112)的所述引线中的一者与从所述集成电路裸片(116)的所述多个端子选择的至少一个端子之间；及囊封材料(110)，其围绕所述集成电路裸片及所述引线框以形成包含所述集成电路裸片及所述熔丝元件的封装集成电路，且在所述囊封材料中具有围绕所述熔丝元件(120)的腔体(122)使得所述熔丝元件与所述囊封材料间隔开。

Description

用于集成电路失效保护熔丝封装的方法及设备
技术领域
本发明通常涉及集成电路封装，且更具体来说，涉及一种用于具有失效保护熔丝及电弧抑制的封装中的集成电路的方法及设备。
背景技术
在2016年8月26日申请的标题为“浮动裸片封装(FLOATING DIE PACKAGE)”、发明人为本杰明·斯达森·库克(Benjamin Stassen Cook)的共同拥有的第15/248,151号美国专利申请案(‘151申请案)描述了一种集成电路封装，其具有形成在模制封装内的腔体，所述腔体通过升华且使用牺牲材料来形成，所述申请案的全部内容特此以引用方式全部并入本文中。
熔丝是电路中的保护元件，其通过在某些条件下产生开路来操作。熔丝的用途根据应用而不同。在一些情况下，熔丝用作可编程元件来重新配置逻辑或存储器电路。更传统地，熔丝产生故障保护电路元件以保护电气系统免受可能损害系统内的布线或其它组件的过电流条件的影响。在过电流条件期间，熔丝可逆地或不可逆地被物理地改变以断开电路。在系统其它地方发生永久性损坏之前，开路会使电流停止流动。
常规的熔丝由金属丝构成，所述金属丝在预定量的电流流过其之后熔化并产生开路。熔线具有由熔化的牺牲部分(例如焊料或小直径导线)连接的金属或导电组件。也可使用具有小横截面的导电迹线。当电流通过熔丝元件时产生开路，从而致使熔丝元件加热到足以使熔丝元件熔化或“熔断”的程度。在熔化阶段期间，当电流开始被中断并形成开路时，可形成使熔丝材料的一部分汽化的电弧。电弧将会不断增长，从而消耗及汽化熔丝元件，直到距离变得太长而不能维持电弧且电流停止流动。在一些模制集成电路封装中，如果封装中包含熔丝，那么可发生模具化合物的碳化，且模具化合物中的细丝或填充物可能成为继续载送电流的导电路径。
在熔丝熔断时汽化的熔丝材料沉积在局部区域中，且存在产生次级导电路径的可能性。为了容纳汽化的材料并防止在电弧后发生电传导，传统的熔丝被囊封在围绕熔丝元件的不导电的玻璃小瓶中。在较高电流的熔丝中，熔丝元件被容纳在用石英砂填充的不导电陶瓷容器内。在玻璃小瓶的情况下，汽化的熔丝材料被玻璃容纳，其中一些汽化的熔丝材料涂布玻璃，然而汽化的材料如此广泛分散使得不会形成次级导电路径。在填充砂的熔丝容器的情况下，汽化的熔丝材料分散在砂中，且来自熔融电弧的热量熔化砂，从而形成防止电流流动的玻璃。
随着集成电路使用的不断增加，熔丝的小型化在努力减小产品尺寸及成本但仍然保护电路方面起着一部分作用。更高电流的熔丝会导致更高的温度及次级导电路径再生的额外机会。集成电路上的熔丝由于小几何形状及形成熔丝所需的多级掩模所导致的成本而对电流容量具有上限。为了获得更高电流的熔丝，熔丝元件有时被移动到安装IC的PCB处，或放置在集成电路裸片之外，但仍位于封装内部。从PCB的元件产生熔丝的缺点是：当被熔断时，整个PCB可能需要更换，导致修理成本过高。更实际的解决方案是在封装内形成熔丝，使得在熔丝熔断的情况下只需要更换封装部分。在使用半导体功率装置的应用中，常见的过应力失效模式是短路装置(例如，电流路径接地)。由于过电压、ESD冲击、超过装置的安全操作条件或装置的制造缺陷，形成功率开关的MOSFET装置有时会在具有到接地的路径的短路状态下失效。这些故障模式需要熔丝元件来保护系统。
例如被囊封在IC封装中的接合线等的芯片上熔丝元件或熔线将通常在过电流事件期间形成次级导电路径。次级导电路径可在高电流过热电弧扩大且燃烧周围的模具化合物以形成碳化的导电路径之后形成。次级导电路径维持电弧，直到装置充分燃烧以熄灭电弧。在电弧被熄灭之前，可能会对装置造成灾难性的损坏，且通常会损坏上面安装了所述装置的印刷电路板。仍然需要一种用于集成电路封装的改进的熔丝设备，其能够中断高电流、形成次级导电路径的概率较低，且装配在半导体封装内。
发明内容
在所描述的实例中，一种设备包含：集成电路裸片，其具有多个端子；所述集成电路裸片位于具有用于外部连接的引线的引线框的裸片垫部分上，所述引线中的至少一些具有电耦合到所述集成电路裸片的至少一个端子的内部部分；熔丝元件，其耦合在所述引线框的所述引线中的一者与从所述集成电路裸片的所述多个端子中选择的至少一个端子之间；及囊封材料，其围绕所述集成电路裸片及所述引线框以形成包含所述集成电路裸片及所述熔丝元件的封装集成电路，且在所述囊封材料中具有围绕所述熔丝元件的腔体使得所述熔丝元件与所述囊封材料间隔开。
附图说明
图1A及1B分别展示了具有带熔丝元件的实例实施例腔体的囊封半导体封装装置的俯视图及截面图。
图2是用于形成图1的封装装置的方法实施例的流程图。
图3A及3B展示了说明实例实施例中的电弧如何被熄灭的两个截面图。
图4是展示了说明使用并入实施例的低侧驱动器FET装置的应用的电路图。
图5A及5B分别是在IC封装中包括功率FET的实例实施例的俯视图及截面图。
具体实施方式
除非另有指示，否则不同附图中的对应数字及符号通常指代对应部分。图式并不一定按比例绘制。术语“耦合”可包含利用中间元件进行的连接，且在“耦合”的任何元件之间可存在额外元件及各种连接。
如上所述，在熔丝熔断后防止形成次级导电路径是制造高可靠性失效保护熔丝的关键因素。实例实施例使用例如‘151申请案中教示的升华过程来在囊封材料中围绕半导体封装内的熔丝元件形成腔体。熔丝元件可被称为“熔线”。在过电流条件导致熔丝元件熔化或“熔断”的事件期间，熔丝元件或熔线将分离以形成开路。通过升华过程产生的腔体将使得在过电流事件期间发生的高电流电弧能够自身熄灭而不会进一步损坏集成电路封装或系统，且防止形成次级导电路径。
‘151申请案中的一个实例使用可升华牺牲囊封剂材料(SSEM)，其可在模制过程期间通过相变升华过程移除。在‘151申请案的实施例中，在模制过程已经完成之后，升华形成腔体以允许裸片在不受引线框约束的情况下“浮动”，仅由接合线固定。在实例实施例中，升华技术以不同的方式使用以在半导体封装内形成腔体，其中例如导线或成形金属带等熔丝元件被容纳在腔体中。产生通风孔以允许牺牲性升华材料在组装封装IC期间以气相离开腔体。在本申请案的实施例中，通风孔也可在其中熔丝材料在分离之前加热的过电流事件期间用作压力释放口。在形成替代实施例的另一布置中，SSEM材料被保持在围绕熔丝元件的腔体中，且在过电流事件期间由于熔丝元件中的温度升高而升华，且随后作为气体从封装中排出。
图1A及1B分别展示了包含具有熔丝元件的腔体的实例实施例中的囊封半导体封装装置的俯视图及截面图。图1B是沿着图1A的俯视图100中的剖面线1B-1B'截取的。在封装装置的俯视图100及横截面102中，展示了具有引线112的引线框及裸片垫及散热器118。集成电路(例如功率IC)116安装在散热器118上。接合线114将功率IC 116连接到八条独立引线112中的七条，且例如接合线120等熔丝元件附接到第八条引线。整个组合件使用模具化合物110进行封装。如‘151申请案所教示，通过升华形成腔体122，其具有通风孔124，所述通风孔124是通过作为薄膜126的通风孔盖密封。腔体122围绕熔丝元件或接合线120。在替代实施例中，熔丝元件可为导电金属带或金属导体的变薄部分，所述金属导体经布置以在过电流条件下熔化。此实例实施例经布置成功率IC 116与熔丝元件120一起布置在由升华过程产生的腔体122内。
图2是用于形成图1的封装装置的方法实施例的流程图。在图2中，方法200从步骤210开始，在步骤210中，将裸片安装到引线框的裸片垫并将接合线附接在裸片与引线框之间。可使用多个过程来实现步骤210中概述的状态。在步骤212处，将SSEM施加到形成与图1中所示的腔体形状122类似的区域的组合件，其中例如接合线或金属带等的熔丝元件被SSEM围绕。囊封剂可为在预期封装处理温度(例如模具固化温度或焊料回流温度)以外在升华条件的多元醇材料。SSEM可被加热并作为挤出粒施加，或可溶解在合适的溶剂中且使用选择性地施加SSEM的注射器分配系统作为液体或凝胶施加。在SSEM已经被施加到适当的位置之后，所述方法过渡到步骤214。在步骤214处，在一或多个步骤中将SSEM固化。在接下来的步骤216中，将模具化合物施加在包含SSEM的引线框组合件上方，从而留下一或多个针孔通风孔以提供SSEM与外部环境之间的路径。在一种方法中，转移模具与环氧树脂一起使用，将环氧树脂加热到液态且然后在压力下迫使其进入模具。还可使用其它囊封技术。通风孔为气态SSEM在后续处理步骤中的逸出提供了路径。在步骤218中，在一或多个步骤中将模具化合物固化。在接下来的步骤220中，将相变过程施加到组合件，且SSEM由于相变过程而变成气体222。气态SSEM通过一或多个通风孔逸出到周围的大气中。通风孔可像针孔一样小，或可为更大的直径。在SSEM先前驻留的囊封封装中留下腔体且所述腔体以周围大气填充。在最后步骤224中，通过与封装处理兼容的过程(例如丝网印刷或B膜)用通风孔盖材料覆盖通风孔。任何额外的封装处理步骤(例如，单体化、引线修整及成形、标记)已完成，且最终的封装集成电路已准备就绪可供使用。
图3A及3B展示了说明包含容纳熔丝元件的封装的实例实施例中的电弧如何熄灭的两个截面图。在图3A中，封装装置的横截面300展示了包含引线312的引线框及裸片垫及散热器318。集成电路316(例如功率IC)安装在散热器318上。虽然在此实例实施例中IC316是功率IC，但是也可使用其它装置类型。接合线314将功率IC 316连接到个别引线312，且熔丝元件(在此实例中为接合线320)附接到引线312。整个组合件被覆盖在模具化合物310中。腔体322围绕熔丝元件、接合线320及通风孔324。薄膜326覆盖通风孔324。在替代布置中，熔丝元件320可由不同尺寸的接合线形成，其中熔丝部分的尺寸小于其余部分的尺寸。在额外布置中，熔丝元件可为熔线，其包含导电金属部分，其中焊料或其它牺牲导电材料连结导电金属部分，当焊料熔化时，熔线在过电流情况下断开。在额外的布置中，熔丝元件可为具有经设计以在过电流事件中熔化及断开的较薄部分的金属导体。
图3A描绘了导致高电流(被示为350)的故障期间的功率IC 316。接合线320或其它熔丝元件将加热并熔化，这开始形成开路。电弧352将立即形成以允许电流继续流动。参考图3B，在横截面302中，现在标记为354的电弧将随着例如接合线320等的熔丝元件被几千度的电弧温度汽化而继续增长。由电弧产生的升温导致腔体322内部的压力积聚，直到通风孔盖326失效且过热的汽化的接合线气体从通风孔(在图3B中示为356)排出。压力的释放导致电弧熄灭，且在腔体内部留下少量汽化的接合线材料的情况下，重新形成次级导电路径的可能性非常低。
图4是展示了说明使用并入实施例的低侧驱动器FET装置的应用的电路图。在图4中，电路400包含耦合到标记为+Vsupply的电源的负载401。响应于用于低侧驱动器FET集成电路装置403的栅极端子GATE上的控制电压，低侧驱动器FET装置403将接地端子耦合到负载401。在此实例中，低侧驱动器FET的漏极端子DRAIN耦合到负载装置。在实例中，负载可包含耦合到低侧驱动器FET集成电路403的电阻及电感电路元件。熔丝元件424被示为在低侧驱动器FET 403的封装内。晶体管416串联连接在漏极端子与接地之间，在用于将负载与熔丝元件424串联耦合的漏极端子与FET 416的漏极之间具有电流传导路径，所述电流传导路径包含晶体管416的源极且串联路径延伸到接地端子。在特定实例中，低侧驱动器FET 416可为高电压低导通电阻FET，例如由本申请案的所有者德州仪器公司供应的NexFETTM装置。适用于特定应用的其它FET装置也可与所述实施例一起使用。在图4中，FET处于负载耦合到正电源且FET集成电路403耦合在负载及接地端子之间的“源极向下”或“低侧”配置。在替代布置中，FET可以“高侧”配置耦合，其中负载耦合到接地端子，且FET介于正电源与负载之间以形成额外的实施例。在实施例中，熔丝元件424与FET的电流传导路径串联。在过电流情况下，熔丝元件424将断开，从而产生开路并保护负载免受损坏。
图5A及5B分别是在IC封装中包括功率FET的实例实施例的俯视图及截面图，所述IC封装在通过使用SSEM过程形成的腔体中具有熔丝元件。在图5A中，集成电路功率FET装置503的俯视图包含围绕组合件的封装505。封装505可包含例如环氧树脂等模塑化合物510，且可包含各种填充材料、导热材料、阻燃剂及用于IC封装的其它已知材料。封装505包含引线框517、安装在引线框517上的功率集成电路裸片516、围绕金属夹部分520中的熔丝元件529的腔体522、从腔体522垂直延伸到封装505的上表面的通风孔524，及通风孔524上方的通风孔盖526。
图5B是沿着图5A中的剖面线5B-5B'截取的截面图。在图5B中，端子512通过导电裸片附接材料514A耦合到FET装置516的源极。此实例中的FET装置是垂直FET，例如(例如)来自德州仪器公司的NexFETTM装置。在垂直FET装置中，集成电路裸片的半导体衬底形成可在集成电路裸片的底表面处接触的源极接点。另一裸片附接部分514B形成与FET516的漏极接点。导电金属夹520在上裸片附接垫514B处接触垂直FET装置的漏极。导电金属夹520包含形成熔丝元件的具有较小横截面的部分529。可使用集成电路组合件中使用的金属，例如铜及其合金、铝及其合金、金及其它导体。在实施例中，金属夹520的熔丝元件部分529位于腔体522中且与形成封装505的模具化合物材料的剩余部分间隔开。引线框517的端子513通过金属夹520及熔丝元件529耦合到FET装置516的漏极。裸片附接部分514C将作为引线框517的部分提供的端子513耦合到导电金属夹520，且然后耦合到FET装置516。栅极端子515(引线框517的另一部分)通过接合线521耦合到FET装置516。如图5A中所见，熔丝元件529可采用各种形状，且如果需要，可为蜿蜒的、卷绕的，或形成为其它形状以使得变窄的部分变长。
在操作中，在负载、FET中的短路故障或另一事件导致过电流之后，熔丝元件529将熔化以产生开路。电弧将立即形成并开始汽化并消耗熔丝元件529。在空隙522围绕熔丝元件529的布置中，热空气将通过通风孔524排出，吹走通风孔盖526。压力的突然释放将会导致电弧熄灭。在腔体内部将留下少量汽化的接合线材料，因此重新形成次级导电路径的可能性非常低。允许汽化的接合线材料离开通风孔，这阻止了导电材料随后在腔体中沉积，使得不会形成次级导电路径。在额外替代方案中，吸气材料可被包含在腔体中以收集汽化的熔丝元件材料，以进一步防止形成次级导电路径。
可形成用于实施例中的熔丝元件的许多形状的熔丝已经被设计出且是可用的，且上文展示的熔丝元件是帮助描述及说明实例实施例的操作的说明性实例。由熔化的材料(例如焊料)连结的导体形成的熔线可用作熔丝元件。可使用具有形成熔丝元件的较小横截面部分的导线连接件。如上所述，可使用具有将引线框端子耦合到集成电路的端子的具有第一厚度或宽度的导电金属夹或带，其中金属夹的较小横截面的部分形成熔丝元件。这些替代方案形成在所附权利要求书的范围内的额外实施例。
修改在所描述的实例实施例中是可行的，并且其它实施例在权利要求书的范围内是可行的。

Claims (20)

1.一种设备，其包括：
集成电路裸片，其具有多个端子；
具有裸片垫部分的引线框，所述集成电路裸片位于所述裸片垫部分上且附接到所述裸片垫部分；
所述引线框具有用于外部连接的引线，所述引线中的至少一些具有电耦合到从所述集成电路裸片的所述多个端子选择的至少一个端子的内部部分；
熔丝元件，其耦合在所述引线框的所述引线中的一者与从所述集成电路裸片的所述多个端子选择的至少一个端子之间；及
囊封材料，其围绕所述集成电路裸片及所述引线框以形成包含所述集成电路裸片及所述熔丝元件的封装集成电路，且在所述囊封材料中具有围绕所述熔丝元件的腔体使得所述熔丝元件与所述囊封材料间隔开。
2.根据权利要求1所述的设备，其中所述腔体是所述囊封材料中围绕所述熔丝元件的空隙。
3.根据权利要求2所述的设备，且其进一步包含从所述腔体延伸到所述囊封材料的外表面的通风孔。
4.根据权利要求3所述的设备，且其进一步包含覆盖所述囊封材料的外表面处的所述通气孔的盖材料。
5.根据权利要求4所述的设备，其中所述盖材料经布置以响应于所述腔体中的气体压力而从所述通风孔吹离。
6.根据权利要求1所述的设备，其中所述腔体包含围绕所述熔丝元件的可升华牺牲囊封剂材料SSEM。
7.根据权利要求1所述的设备，其中所述熔丝元件是用于在过电流条件下形成开路的熔线。
8.根据权利要求1所述的设备，其中所述熔丝元件是用于在过电流条件下形成开路的接合线。
9.根据权利要求1所述的设备，其中所述熔丝元件是由金属夹的具有第一厚度的第一部分形成，所述金属夹的第二部分具有大于所述第一厚度的第二厚度。
10.根据权利要求1所述的设备，其中所述熔丝元件是第一直径的导线，所述导线耦合到大于所述第一直径的第二直径的接合线部分。
11.根据权利要求1所述的设备，其中所述集成电路裸片包含晶体管，且所述熔丝元件串联耦合在所述集成电路裸片的端子与所述引线框的引线之间。
12.根据权利要求1所述的设备，其中所述熔丝元件经配置以在过电流事件期间加热并燃烧，且所述熔丝元件随后形成开路。
13.一种方法，其包括：
将集成电路裸片附接到引线框的裸片垫部分，所述集成电路裸片具有多个端子；
将所述引线框的端子电耦合到所述集成电路裸片的输入及输出端子中的至少一者；
将熔丝元件耦合在所述集成电路裸片的端子与所述引线框的所述端子中的选定者之间以在所述引线框的所述端子与所述集成电路裸片之间形成串联电流路径；
施加牺牲可升华囊封材料SSEM以围绕熔丝元件；
固化所述SSEM；
囊封所述集成电路裸片、所述引线框及所述SSEM以形成囊封材料的集成电路封装，所述SSEM在所述囊封材料中形成腔体，所述熔丝元件位于所述腔体中且与所述囊封材料间隔开；
在所述囊封材料中形成延伸到容纳所述SSEM的所述腔体的通风孔；及
施加相变过程以使所述SSEM气化并允许所述SSEM通过所述通风孔逸出。
14.根据权利要求13所述的方法，且其进一步包含用经配置以响应于所述腔体中的气体压力而吹走的材料来覆盖所述通风孔。
15.根据权利要求13所述的方法，且其进一步包含将电源与所述熔丝元件及所述集成电路串联耦合；且在过电流情况下，燃烧所述熔丝元件，来自所述燃烧的熔丝元件的热量在所述腔体中产生热空气，所述热空气通过所述通风孔排出。
16.根据权利要求15所述的方法，其中所述燃烧的熔丝元件被汽化，且所述汽化的熔丝元件材料通过所述通风孔离开所述集成电路封装。
17.根据权利要求13所述的方法，且其进一步包含将电源与所述熔丝元件及所述集成电路串联耦合；且在过电流情况下，燃烧所述熔丝元件，来自所述熔丝元件的热量气化所述腔体中的所述SSEM，所述SSEM通过所述通风孔排出。
18.一种具有过电流保护的功率集成电路，其包括：
集成电路裸片，其包含安置在引线框的部分上并具有源极端子、栅极端子及漏极端子的FET；
接合线，其将所述引线框的外部端子耦合到所述集成电路裸片的所述源极端子、漏极端子及栅极端子中的至少一者；
熔丝元件，其串联耦合在所述引线框的外部端子与所述集成电路裸片的所述源极端子及所述漏极端子中的至少一者之间；
囊封材料，其围绕所述集成电路裸片及所述引线框以形成封装集成电路，所述囊封材料通过所述囊封材料中的腔体与所述熔丝元件间隔开，所述熔丝元件被所述腔体围绕；及
通风孔，其从所述封装集成电路的外表面延伸到所述腔体且被通风孔盖材料覆盖，所述通风孔盖材料经配置以成响应于所述腔体中的压力而从所述通风孔吹走。
19.根据权利要求18所述的功率集成电路，其中所述腔体包含容纳空气的空隙。
20.根据权利要求18所述的功率集成电路，其中所述腔体包含围绕所述熔丝元件的牺牲可升华囊封材料SSEM。
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