CN108242436A - 共接触部半导体器件封装 - Google Patents

共接触部半导体器件封装 Download PDF

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Publication number
CN108242436A
CN108242436A CN201711374979.9A CN201711374979A CN108242436A CN 108242436 A CN108242436 A CN 108242436A CN 201711374979 A CN201711374979 A CN 201711374979A CN 108242436 A CN108242436 A CN 108242436A
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Prior art keywords
conductive clip
transistor
vertical
contact
semiconductor packages
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Granted
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CN201711374979.9A
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CN108242436B (zh
Inventor
赵应山
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Infineon Science And Technology Americas
Infineon Technologies North America Corp
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Infineon Science And Technology Americas
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Abstract

本发明涉及一种共接触部半导体器件封装。具体而言，一种半导体器件封装，包括导电夹，所述导电夹具有凹部并且被配置为沿着限定所述凹部的边界的第一表面和第二表面安装到衬底，并且所述半导体器件封装包括至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述凹部内，使得漏极接触部或源极接触部耦合到所述导电夹，并且使得栅极接触部和源极接触部或漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的相同长轴延伸。

Description

共接触部半导体器件封装
技术领域
本公开内容涉及共接触部半导体器件封装。
背景技术
表面安装技术是一种电子设备的生产方法，涉及将无源或有源部件(例如被实现为封装器件的那些)附接到例如印刷电路板。这样的部件可以被焊接到印刷电路板以建立与安装到所述印刷电路板的其它部件的连接。
发明内容
本公开内容涉及共接触部半导体器件封装。短语“共接触部”旨在表达：相同类型的至少两个器件以相同的取向耦合到半导体器件封装的一部分，使得器件的第一侧上的相似接触部耦合到半导体器件封装的所述部分，并且使得器件的第二侧上的相似接触部延伸而被暴露并以特定取向对齐。
因此，根据本公开内容的一方面，半导体器件封装可以包括或包含：导电夹(conductive clip)，所述导电夹包括凹部并且被配置为沿着限定凹部的边界的第一表面和第二表面安装到衬底；以及至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在凹部内，使得漏极或源极接触部耦合到导电夹，并且使得栅极接触部和源极或漏极接触部延伸而在凹部内被暴露并且沿着导电夹的相同长轴延伸。
这样的实施方式代表典范转移(paradigm shift)，因为例如在半导体器件封装并入在半桥电路中时，导电夹可以用作半桥电路的电源节点，而衬底上的导电迹线或焊盘可以用作半桥电路的开关节点。另外，可以实现制造相关的益处，因为垂直沟道晶体管的取向有助于在将半导体器件封装表面安装到衬底的过程期间的半导体器件封装与衬底之间的配准，并且可以实现性能相关的益处，因为半导体器件封装本身不会使垂直沟道晶体管的器件级特性退化。
附图说明
图1示出了根据本公开内容的半桥电路的示意性框图。
图2示出了根据本公开内容的第一半导体管芯的透视图。
图3示出了根据本公开内容的第二半导体管芯的透视图。
图4示出了根据本公开内容的第一共接触部半导体器件封装的截面视图。
图5示出了图4的半导体器件封装的底视图。
图6示出了根据本公开内容的第二共接触部半导体器件封装的截面视图。
图7示出了图6的半导体器件封装的底视图。
图8示出了使用图4-5的封装而实现的图1的半桥电路的底视图。
图9示出了使用图6-7的封装而实现的图1的半桥电路的底视图。
图10示出了图8或图9的半桥电路的顶视图。
图11示出了根据本公开内容的示例性方法的流程图。
具体实施方式
本公开内容涉及共接触部半导体器件封装。短语“共接触部”旨在表达：相同类型的至少两个器件以相同的取向耦合到半导体器件封装的一部分，使得器件的第一侧上的相似接触部耦合到半导体器件封装的所述部分，并且使得器件的第二侧上的相似接触部延伸而被暴露并以特定取向对齐。因此，根据本公开内容的一方面，半导体器件封装可以包括或包含：导电夹，所述导电夹包括凹部并且被配置为沿着限定凹部的边界的第一表面和第二表面安装到衬底；以及至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在凹部内，使得漏极或源极接触部耦合到导电夹，并且使得栅极接触部和源极或漏极接触部延伸而在凹部内被暴露并且沿着导电夹的相同长轴延伸。这样的实施方式代表典范转移，因为例如在半导体器件封装并入在半桥电路中时，导电夹可以用作半桥电路的电源节点，而衬底上的导电迹线或焊盘可以用作半桥电路的开关节点。尽管未被如此限制，但可以通过结合附图所提供的以下讨论来获得对本公开内容的各个方面的理解。
例如，图1示出了根据本公开内容的半桥电路100的示意性框图。具体而言，半桥电路100包括第一共接触部半导体器件封装102(在下文中称为“第一封装102”)以及第二共接触部半导体器件封装104(在下文中称为“第二封装104”)。第一封装102是共漏极半导体器件封装的示例，其中多个高侧晶体管108A-C(统称为“高侧晶体管108”)中对应的一个晶体管的漏极接触部106A-C(统称为“漏极接触部106”)耦合到第一封装102的导电夹110。导电夹110进而耦合到电源电压节点112。高侧晶体管108的示例在图2中示出。导电夹110的示例在图4-7中示出。相比之下，第二封装104是共源极半导体器件封装的示例，其中多个低侧晶体管116A-C(统称为“低侧晶体管116”)中对应的一个晶体管的源极接触部114A-C(统称为“源极接触部114”)耦合到第二封装104的导电夹118。导电夹118进而耦合到参考电压节点120。低侧晶体管116的示例在图3中示出。导电夹118的示例在图4-7中示出。
在图1的示例中，高侧晶体管108A和低侧晶体管116A以共源共栅布置进行连接并且一起限定第一半桥电路，其中高侧晶体管108A的源极接触部耦合到低侧晶体管116A的漏极接触部以限定第一开关节点122A。另外，高侧晶体管108A的栅极接触部耦合到第一高侧输入节点124A，并且低侧晶体管116A的栅极接触部耦合到第一低侧输入节点126A。如技术人员将理解的，响应于分别经由第一高侧输入节点124A和第一低侧输入节点126A而供应到高侧晶体管108A和低侧晶体管116A的栅极接触部的定时信号，在第一开关节点122A处形成电压波形，该电压波形(近似地)在电源电压节点112处的电压电平与参考电压节点120处的电压电平之间切换幅值。
在图1的示例中，高侧晶体管108B和低侧晶体管116B以共源共栅布置进行连接并且一起限定第二半桥电路，其中高侧晶体管108B的源极接触部耦合到低侧晶体管116B的漏极接触部以限定第二开关节点122B。另外，高侧晶体管108B的栅极接触部耦合到第二高侧输入节点124B，并且低侧晶体管116B的栅极接触部耦合到第二低侧输入节点126B。如技术人员将理解的，响应于分别经由第二高侧输入节点124B和第二低侧输入节点126B而供应到高侧晶体管108B和低侧晶体管116B的栅极接触部的定时信号，在第二开关节点122B处形成方波电压波形，该方波电压波形(近似地)在电源电压节点112处的电压电平与参考电压节点120处的电压电平之间切换幅值。
在图1的示例中，高侧晶体管108C和低侧晶体管116C以共源共栅布置进行连接并且一起限定第三半桥电路，其中高侧晶体管108C的源极接触部耦合到低侧晶体管116C的漏极接触部以限定第三开关节点122C。另外，高侧晶体管108C的栅极接触部耦合到第三高侧输入节点124C，并且低侧晶体管116C的栅极接触部耦合到第三低侧输入节点126C。如技术人员将理解的，响应于分别经由第三高侧输入节点124C和第三低侧输入节点126C而供应到高侧晶体管108C和低侧晶体管116C的栅极接触部的定时信号，在第三开关节点122C处形成方波电压波形，该方波电压波形(近似地)在电源电压节点112处的电压电平与参考电压节点120处的电压电平之间切换幅值。
因此，尽管本公开内容未被如此限制，但图1的半桥电路100是三相半桥电路的示例。作为示例，三相半桥电路可以用于三相电源或电机控制解决方案中或用作三相电源或电机控制解决方案的一部分。因此。可以考虑的是，图1的高侧晶体管108和图1的低侧晶体管116可以被实现为多端子功率半导体器件，所述多端子功率半导体器件为开关并且具有实施方式专用的类型。
例如，高侧晶体管108的任何特定实例和低侧晶体管116的任何特定实例可以被实现为IGBT(绝缘栅双极型晶体管)功率晶体管。另外或替代地，高侧晶体管108的任何特定实例和低侧晶体管116的任何特定实例可以被实现为垂直n沟道或p沟道MOSFET(金属氧化物半导体场效应晶体管)功率晶体管。另外或替代地，高侧晶体管108的任何特定实例和低侧晶体管116的任何特定实例可以被实现为垂直n沟道或p沟道FINFET(鳍式场效应晶体管)功率晶体管，其中前述功率晶体管类型中的任一种都是由德国Infineon Technologies ofNeubiberg制造并出售的。在这些和其它示例中，高侧晶体管108的任何特定实例和低侧晶体管116的任何特定实例可以由半导体管芯形成或被形成为半导体管芯。
图2示出了根据本公开内容的第一半导体管芯200的透视图。具体而言，图2示出了集成在第一半导体管芯200内或被形成为第一半导体管芯200的高侧晶体管108的单个实例。尽管如此，如以下结合图4-7所讨论的，高侧晶体管108的多于单个实例可以集成在第一半导体管芯200内或被形成为第一半导体管芯200。然而，在图2的示例中，源极(发射极)接触部202和栅极接触部204布置在半导体管芯200的正面206上，而漏极(集电极)接触部208布置在半导体管芯200的背面210上。如上所述，高侧晶体管108可以对应于多端子功率半导体器件，所述多端子功率半导体器件为开关并且具有实施方式专用的类型。因此，在如以上结合图1所讨论的由高侧晶体管108和低侧晶体管116限定的半桥电路的切换期间，响应于跨源极(发射极)接触部202和漏极(集电极)接触部208供应的适当电压以及供应到栅极接触部204的适当电压，电流在源极(发射极)接触部202与漏极(集电极)接触部208之间流动。
图3示出了根据本公开内容的第三半导体管芯300的透视图。具体而言，图3示出了集成在第三半导体管芯300内或被形成为第三半导体管芯300的低侧晶体管116的单个实例。尽管如此，如以下结合图4-7所讨论的，低侧晶体管116的多于单个实例可以集成在第三半导体管芯300内或被形成为第三半导体管芯300。然而，在图3的示例中，漏极(集电极)接触部302和栅极接触部304布置在第二半导体管芯300的正面306上，而源极(发射极)接触部308布置在第二半导体管芯300的背面310上。如上所述，低侧晶体管116可以对应于多端子功率半导体器件，所述多端子功率半导体器件为开关并且具有实施方式专用的类型。因此，在如以上结合图1所讨论的由高侧晶体管108和低侧晶体管116限定的半桥电路的切换期间，响应于跨漏极(集电极)接触部302和源极(发射极)接触部308供应的适当电压以及供应到栅极接触部304的适当电压，电流在漏极(集电极)接触部302与源极(发射极)接触部308之间流动。
如上所述，高侧晶体管108的单个实例可以集成在第一半导体管芯200内或被形成为第一半导体管芯200，并且低侧晶体管116的单个实例可以集成在第三半导体管芯300内或被形成为第三半导体管芯300。图4-5示出了第一共接触部半导体器件封装400(在下文中称为“封装400”)，封装400包括耦合到导电夹404的半导体管芯402的多个不同实例，其中，由于图2的第一半导体管芯200和图3的第二半导体管芯300的结构配置的相似性，半导体管芯402可以对应于第一半导体管芯200和第二半导体管芯300中的任一个。类似地，导电夹404可以对应于图1的导电夹110和导电夹118中的任一个。引申开来，图4-5的封装400可以对应于图1的第一封装102和第二封装104中的任一个。因此，参考图4-5的封装400所提供的讨论可等效适用于如图1中所示的第一封装102和第二封装104中的每一个。
具体而言，图4示出了根据本公开内容的封装400的截面视图，并且图5示出了图4的封装400的底视图。被安装到衬底802的图4-5的封装400的示例性视图在图8-10中的至少一个中示出。如上所述，封装400包括导电夹404。导电夹404包括凹部406(参见图4)并且被配置为沿着限定凹部406的边界的第一表面408和第二表面410安装到衬底802。在该示例中，仅仅为了与本公开内容的三相半桥电路示例相一致而示出的半导体管芯402的三个实例中的每一个以相同的取向安装在凹部406内，使得漏极或源极接触部412耦合到导电夹404，并且使得栅极接触部414和源极或漏极接触部416延伸而在凹部406内被暴露并且沿着导电夹404的相同长轴X延伸(参见图5)。在一些示例中，尽管不需要，但导电粘合剂418位于漏极或源极接触部412与导电夹404之间。在一些示例中，尽管不需要，但导电接触部420被置于栅极接触部414上并且导电接触部422被置于源极或漏极接触部416上以有助于表面安装过程，其中封装400被安装到衬底802。如图4-5中所示的这样的实施方式(其中，栅极接触部414和源极或漏极接触部416延伸而在凹部406内被暴露并且沿着如图5中所示的导电夹404的长轴X对齐)有利地便于与衬底上的导电迹线或焊盘精确地配准(参见图8-10)。
如上所述，高侧晶体管108的多于单个实例可以集成在第一半导体管芯200内或被形成为第一半导体管芯200，并且低侧晶体管116的多于单个实例可以集成在第三半导体管芯300内或被形成为第三半导体管芯300。图6-7示出了第二共接触部半导体器件封装600(在下文中称为“封装600”)，封装600包括集成在单个公共半导体管芯603内或被形成为单个公共半导体管芯603的半导体管芯602的多个不同实例。在该示例中，半导体管芯603耦合到导电夹604，其中，由于图2的第一半导体管芯200和图3的第二半导体管芯300的结构配置的相似性，半导体管芯602可以对应于第一半导体管芯200和第二半导体管芯300中的任一个。类似地，导电夹604可以对应于图1的导电夹110和导电夹118中的任一个。引申开来，图6-7的封装600可以对应于图1的第一封装102和第二封装104中的任一个。因此，参考图6-7的封装600所提供的以下讨论可等效适用于如图1中所示的封装102和封装104中的每一个。
具体而言，图6示出了根据本公开内容的封装600的截面视图，并且图7示出了图6的封装600的底视图。被安装到衬底902的图6-7的封装600的示例性视图在图8-10中的至少一个中示出。如上所述，封装600包括导电夹604。导电夹604包括凹部606(参见图6)并且被配置为沿着限定凹部606的边界的第一表面608和第二表面610安装到衬底902。在该示例中，仅仅为了与本公开内容的三相半桥电路示例相一致而示出的半导体管芯602的三个实例中的每一个——等效地，半导体管芯603——以相同的取向安装在凹部606内，使得漏极或源极接触部612耦合到导电夹604，并且使得栅极接触部614和源极或漏极接触部616延伸而在凹部606内被暴露并且沿着导电夹604的相同长轴X延伸(参见图6)。在一些示例中，尽管不需要，但导电粘合剂618位于漏极或源极接触部612与导电夹604之间。在一些示例中，尽管不需要，但导电接触部620被置于栅极接触部614上并且导电接触部622被置于源极或漏极接触部616上以有助于表面安装过程，其中封装600被安装到衬底902。如图6-7中所示的这样的实施方式(其中，栅极接触部614和源极或漏极接触部616延伸而在凹部606内被暴露并且沿着如图7中所示的导电夹604的长轴X对齐)有利地便于与衬底上的导电迹线或焊盘精确地配准(参见图8-10)。
如上所述，被安装到衬底802的图4-5的封装400的示例性视图在图8-10中的至少一个中示出。另外，参考图4-5的封装400所提供的讨论可等效适用于如图1中所示的第一封装102和第二封装104中的每一个。图8具体而言示出了使用图4-5的封装400(等效地使用图1的第一封装102，以及使用图1的第二封装104，其中，第一封装102包括用于半桥电路100的高侧转换的高侧晶体管108A-C，第二封装104包括用于半桥电路100的低侧转换的低侧晶体管116A-C)实现的图1的半桥电路100的底视图。图10示出了图8的半桥电路100的顶视图。
图8的“底视图”视角和图10的“顶视图”如图4中所示，其中在图8和图10中，第一封装102的实例和第二封装104的实例被示出为安装到衬底802以限定图1的半桥电路100。更具体地，并且共同参考图1、4、8和10，第一封装102的实例被安装到衬底802，使得第一封装102的导电夹404的第一表面408和第二表面410中的每一个(参见图4)接触沉积在衬底802的顶表面806上的第一接触部焊盘或迹线804A-B(统称为“迹线804”)中对应的一个(参见图8)。在该示例中，第一接触部焊盘或迹线804A-B中的每一个进而耦合到电源电压节点112(参见图1和图8)。类似地，第二封装104的实例被安装到衬底802，使得第二封装104的导电夹404的第一表面408和第二表面410中的每一个接触沉积在衬底802的顶表面806上的第二接触部焊盘或迹线806A-B(统称为“迹线806”)中对应的一个。在该示例中，第二接触部焊盘或迹线806A-B中的每一个进而耦合到电源电压节点112(参见图1和图8)。以这种方式，导电夹404(或等效地，“CAN 404”)可以用作半桥电路100的电源节点。
此外，第一封装102被安装到衬底802，使得第一封装102的导电接触部420的每个实例(其进而置于高侧晶体管108的对应实例的栅极接触部414上(参见图1；图4))接触沉积在衬底802的顶表面806上的第三接触部焊盘或迹线808A-C(统称为“迹线808”)中对应的实例(参见图8)。在该示例中，第三接触部焊盘或迹线808A-C中的每一个进而耦合到高侧输入节点124A-C中对应的一个(参见图1)。类似地，第二封装104被安装到衬底802，使得第二封装104的导电接触部420的每个实例(其进而置于低侧晶体管116的对应实例的栅极接触部414上(参见图1；图4))接触沉积在衬底802的顶表面806上的第四接触部焊盘或迹线810A-C(统称为“迹线810”)中对应的实例(参见图8)。在该示例中，第四接触部焊盘或迹线810A-C中的每一个进而耦合到低侧输入节点126A-C中对应的一个(参见图1)。
此外，第一封装102被安装到衬底802，使得第一封装102的导电接触部422的每个实例(其进而置于高侧晶体管108的对应实例的漏极接触部106上(参见图1；图4))接触沉积在衬底802的顶表面806上的第五接触部焊盘或迹线812A-C中对应的实例(参见图8)。类似地，第二封装104被安装到衬底802，使得第二封装104的导电接触部422的每个实例(其进而置于低侧晶体管116的对应实例的源极接触部114上(参见图1；图4))接触沉积在衬底802的顶表面806上的第五接触部焊盘或迹线812A-C(统称为“迹线812”)中对应的实例(参见图8)。在该示例中，第五接触部焊盘或迹线812A-C中的每一个进而耦合到开关节点122A-C中对应的一个(参见图1)。以这种方式，衬底802上的导电迹线或焊盘可以用作半桥电路100的开关节点。
如上所述，被安装到衬底902的图6-7的封装600的示例性视图在图8-10中的至少一个中示出。另外，参考图6-7的封装600所提供的讨论可等效适用于如图1中所示的第一封装102和第二封装104中的每一个。图9具体而言示出了使用图6-7的封装600(等效地使用图1的第一封装102，以及使用图1的第二封装104，其中，第一封装102包括用于半桥电路100的高侧转换的高侧晶体管108A-C，第二封装104包括用于半桥电路100的低侧转换的低侧晶体管116A-C)实现的图1的半桥电路100的底视图。图10示出了图9的半桥电路100的顶视图。
图9的“底视图”视角和图10的“顶视图”如图6中所示，其中在图9和图10中，第一封装102的实例和第二封装104的实例被示出为安装到衬底902以限定图1的半桥电路100。更具体地，并且共同参考图1、6、9和10，第一封装102的实例被安装到衬底902，使得第一封装102的导电夹404的第一表面408和第二表面410中的每一个(参见图6)接触沉积在衬底902的顶表面906上的第一接触部焊盘或迹线804A-B(统称为“迹线804”)中对应的一个(参见图9)。在该示例中，第一接触部焊盘或迹线804A-B中的每一个进而耦合到电源电压节点112(参见图1和图9)。类似地，第二封装104的实例被安装到衬底902，使得第二封装104的导电夹404的第一表面408和第二表面410中的每一个接触沉积在衬底902的顶表面906上的第二接触部焊盘或迹线806A-B(统称为“迹线806”)中对应的一个。在该示例中，第二接触部焊盘或迹线806A-B中的每一个进而耦合到电源电压节点112(参见图1和图9)。以这种方式，导电夹404(或等效地，“CAN 404”)可以用作半桥电路100的电源节点。
此外，第一封装102被安装到衬底902，使得第一封装102的导电接触部420的每个实例(其进而置于高侧晶体管108的对应实例的栅极接触部414上(参见图1；图6))接触沉积在衬底902的顶表面906上的第三接触部焊盘或迹线808A-C(统称为“迹线808”)中对应的实例(参见图9)。在该示例中，第三接触部焊盘或迹线808A-C中的每一个进而耦合到高侧输入节点124A-C中对应的一个(参见图1)。类似地，第二封装104被安装到衬底902，使得第二封装104的导电接触部420的每个实例(其进而置于低侧晶体管116的对应实例的栅极接触部414上(参见图1；图6))接触沉积在衬底902的顶表面906上的第四接触部焊盘或迹线810A-C(统称为“迹线810”)中对应的实例(参见图9)。在该示例中，第四接触部焊盘或迹线810A-C中的每一个进而耦合到低侧输入节点126A-C中对应的一个(参见图1)。
此外，第一封装102被安装到衬底902，使得第一封装102的导电接触部422的每个实例(其进而置于高侧晶体管108的对应实例的漏极接触部106上(参见图1；图6))接触沉积在衬底902的顶表面906上的第五接触部焊盘或迹线812A-C中对应的实例(参见图9)。类似地，第二封装104被安装到衬底902，使得第二封装104的导电接触部422的每个实例(其进而置于低侧晶体管116的对应实例的源极接触部114上(参见图1；图6))接触沉积在衬底902的顶表面906上的第五接触部焊盘或迹线812A-C(统称为“迹线812”)中对应的实例(参见图9)。在该示例中，第五接触部焊盘或迹线812A-C中的每一个进而耦合到开关节点122A-C中对应的一个(参见图1)。以这种方式，衬底902上的导电迹线或焊盘可以用作半桥电路100的开关节点。
图11示出了根据本公开内容的用于限定图1的半桥电路100的示例性方法1100。示例性方法1100包括以下步骤：从根据本公开内容的原理配置和/或布置的共接触部半导体器件封装的集合中选择(1102)共漏极半导体器件封装。结合图1、2和4-7在上文示出并讨论了这样的共漏极半导体器件封装的示例。示例性方法1100进一步包括以下步骤：将共漏极半导体器件封装与衬底上的对应特征对齐或配准(1104)，以及随后将共漏极半导体器件封装表面安装(1106)在衬底上。例如，参考图8，共漏极半导体器件封装102可以与迹线804A-B中的一个或两个对齐，使得导电夹404的第一表面408和第二表面410中的每一个表面在x和y两个方向上精确地以迹线804A-B中对应的一个迹线为中心或沿着迹线804A-B中对应的一个迹线。有利地，通过这样做，导电接触部420和导电接触部422的每个实例引申开来与迹线808和迹线812中对应的一个迹线精确地对齐或配准。如上所述，这是因为栅极接触部414(如耦合到导电接触部420)和漏极接触部416(如耦合到导电接触部422)延伸而在凹部406内被暴露并且沿着导电夹404的长轴X对齐(参见图4-5)。共漏极半导体器件封装102继而可以迅速地表面安装到衬底802，使得在迹线804、808和812与共漏极半导体器件封装102中的对应元件之间建立机械连接和电连接。
示例性方法1100进一步包括以下步骤：从根据本公开内容的原理配置和/或布置的共接触部半导体器件封装的集合中选择(1108)共源极半导体器件封装。结合图1、3和4-7在上文示出并讨论了这样的共源极半导体器件封装的示例。示例性方法1100进一步包括以下步骤：将共源极半导体器件封装与衬底上的对应特征对齐或配准(1110)，以及随后将共源极半导体器件封装表面安装(1112)在衬底上。例如，参考图9，共源极半导体器件封装104可以与迹线806A-B中的一个或两个对齐，使得导电夹404的第一表面408和第二表面410中的每一个表面在x和y两个方向上精确地以迹线806A-B中对应的一个迹线为中心或沿着迹线806A-B中对应的一个迹线。有利地，通过这样做，导电接触部420和导电接触部422的每个实例引申开来与迹线810和迹线812中对应的一个迹线精确地对齐或配准。如上所述，这是因为栅极接触部414(如耦合到导电接触部420)和漏极接触部416(如耦合到导电接触部422)延伸而在凹部406内被暴露并且沿着导电夹404的长轴X对齐(参见图6-7)。共源极半导体器件封装104继而可以迅速地表面安装到衬底802，使得在迹线806、810和812与共源极半导体器件封装104中的对应元件之间建立机械连接和电连接。
示例性方法1100代表典范转移，因为例如在半导体器件封装102、104并入在半桥电路中时，导电夹110、118可以用作半桥电路的电源节点，而衬底802、902上的导电迹线或焊盘812可以用作半桥电路的开关节点。另外，可以实现制造相关的益处，因为第一半导体管芯200或第二半导体管芯300的垂直沟道晶体管的取向有助于在将半导体器件封装102、104表面安装到衬底802、902的过程期间的半导体器件封装102、104与衬底802、902之间的配准。另外，可以实现性能相关的益处，因为半导体器件封装102、104本身不会使第一半导体管芯200或第二半导体管芯300的垂直沟道晶体管的器件级特性退化。这是因为第一半导体管芯200或第二半导体管芯300的开关节点接触部不与半导体器件封装102、104本身的任何外部或不必要的封装元件(例如，引线框、桥接引线键合、导电夹等)串联连接。替代地，开关节点接触部直接(或在一些示例中经由接触部422或622)连接到衬底上802、902上的焊盘或迹线812。
另外，以下有编号的示例展示了本公开内容的一个或多个方面。
示例1：一种半导体器件封装，包括：导电夹，所述导电夹包括凹部并且被配置为沿着限定所述凹部的边界的第一表面和第二表面安装到衬底；以及至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述凹部内，使得漏极接触部或源极接触部耦合到所述导电夹，并且使得栅极接触部和源极接触部或漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的相同长轴延伸。
示例2：根据示例1所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述漏极接触部电耦合到所述导电夹，并且所述栅极接触部和所述源极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸。
示例3：根据示例1-2中的任一项所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述源极接触部电耦合到所述导电夹，并且所述栅极接触部和所述漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸。
示例4：根据示例1-3中的任一项所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管是不同的半导体管芯。
示例5：根据示例1-4中的任一项所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管集成在公共半导体管芯内。
示例6：一种系统，包括：第一半导体封装，所述第一半导体封装包括第一导电夹和第一多个晶体管，其中：所述第一导电夹包括凹部并且被配置为沿着所述第一导电夹的限定所述凹部的边界的第一表面和第二表面安装到衬底；并且所述第一多个晶体管包括至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述第一导电夹的所述凹部内，使得漏极接触部耦合到所述第一导电夹，并且使得栅极接触部和源极接触部延伸而在所述凹部内被暴露并且沿着所述第一导电夹的相同长轴延伸；以及第二半导体封装，所述第二半导体封装包括第二导电夹和第二多个晶体管，其中：所述第二导电夹包括凹部并且被配置为沿着所述第二导电夹的限定所述凹部的边界的第一表面和第二表面安装到所述衬底；并且所述第二多个晶体管包括至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述第二导电夹的所述凹部内，使得源极接触部耦合到所述第二导电夹，并且使得栅极接触部和漏极接触部延伸而在所述凹部内被暴露并且沿着所述第二导电夹的相同长轴延伸。
示例7：根据示例6所述的系统，其中，所述第一多个晶体管中的每一个晶体管是不同的半导体管芯。
示例8：根据示例6-7中的任一项所述的系统，其中，所述第一多个晶体管集成在公共半导体管芯内。
示例9：根据示例6-8中的任一项所述的系统，其中，所述第二多个晶体管中的每一个晶体管是不同的半导体管芯。
示例10：根据示例6-9中的任一项所述的系统，其中，所述第二多个晶体管集成在公共半导体管芯内。
示例11：根据示例6-10中的任一项所述的系统，其中，所述第一多个晶体管中的每一个晶体管是垂直n沟道功率晶体管。
示例12：根据示例6-11中的任一项所述的系统，其中，所述第一多个晶体管中的每一个晶体管是垂直p沟道功率晶体管。
示例13：根据示例6-12中的任一项所述的系统，其中，所述第二多个晶体管中的每一个晶体管是垂直n沟道功率晶体管。
示例14：根据示例6-13中的任一项所述的系统，其中，所述第二多个晶体管中的每一个晶体管是垂直p沟道功率晶体管。
示例15：根据示例6-14中的任一项所述的系统，其中，所述第一多个晶体管中的每一个晶体管是垂直的基于鳍状物的多栅极晶体管。
示例16：根据示例6-15中的任一项所述的系统，其中，所述第二多个晶体管中的每一个晶体管是垂直的基于鳍状物的多栅极晶体管。
示例17：根据示例6-16中的任一项所述的系统，进一步包括印刷电路板，其中，所述第一半导体封装和所述第二半导体封装作为多相桥式电路的部分而被安装到所述印刷电路板。
示例18：一种方法，包括：以相同的取向将相同类型的至少两个垂直沟道晶体管安装到被配置为沿着限定凹部的第一表面和第二表面安装到衬底的导电夹的所述凹部，使得漏极接触部或源极接触部耦合到所述导电夹，并且使得栅极接触部和源极接触部或漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的相同长轴延伸。
示例19：根据示例18所述的方法，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述漏极接触部电耦合到所述导电夹，并且所述栅极接触部和所述源极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸，并且所述方法进一步包括：将所述导电夹安装到所述衬底；以及将所述导电夹耦合到被配置为驱动多相电机的半桥电路的接地参考节点。
示例20：根据示例19-20中的任一项所述的方法，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述源极接触部电耦合到所述导电夹，并且所述栅极接触部和所述漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸，并且所述方法进一步包括：将所述导电夹安装到所述衬底；以及将所述导电夹耦合到被配置为驱动多相电机的半桥电路的电池电源节点。
已经描述了本公开内容的各种示例。考虑到所述系统、操作或功能的任何组合。这些和其它示例处于以下权利要求的范围内。

Claims (20)

1.一种半导体器件封装，包括：
导电夹，所述导电夹包括凹部并且被配置为沿着限定所述凹部的边界的第一表面和第二表面安装到衬底；以及
至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述凹部内，使得漏极接触部或源极接触部耦合到所述导电夹，并且使得栅极接触部和源极接触部或漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的相同长轴延伸。
2.根据权利要求1所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述漏极接触部电耦合到所述导电夹，并且所述栅极接触部和所述源极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸。
3.根据权利要求1所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述源极接触部电耦合到所述导电夹，并且所述栅极接触部和所述漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸。
4.根据权利要求1所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管是不同的半导体管芯。
5.根据权利要求1所述的半导体器件封装，其中，所述至少两个垂直沟道晶体管集成在公共半导体管芯内。
6.一种系统，包括：
第一半导体封装，所述第一半导体封装包括第一导电夹和第一多个晶体管，其中：
所述第一导电夹包括凹部并且被配置为沿着所述第一导电夹的限定所述凹部的边界的第一表面和第二表面安装到衬底；并且
所述第一多个晶体管包括至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述第一导电夹的所述凹部内，使得漏极接触部耦合到所述第一导电夹，并且使得栅极接触部和源极接触部延伸而在所述凹部内被暴露并且沿着所述第一导电夹的相同长轴延伸；以及
第二半导体封装，所述第二半导体封装包括第二导电夹和第二多个晶体管，其中：
所述第二导电夹包括凹部并且被配置为沿着所述第二导电夹的限定所述凹部的边界的第一表面和第二表面安装到所述衬底；并且
所述第二多个晶体管包括至少两个垂直沟道晶体管，所述至少两个垂直沟道晶体管具有相同的类型并且以相同的取向安装在所述第二导电夹的所述凹部内，使得源极接触部耦合到所述第二导电夹，并且使得栅极接触部和漏极接触部延伸而在所述凹部内被暴露并且沿着所述第二导电夹的相同长轴延伸。
7.根据权利要求6所述的系统，其中，所述第一多个晶体管中的每一个晶体管是不同的半导体管芯。
8.根据权利要求6所述的系统，其中，所述第一多个晶体管集成在公共半导体管芯内。
9.根据权利要求6所述的系统，其中，所述第二多个晶体管中的每一个晶体管是不同的半导体管芯。
10.根据权利要求6所述的系统，其中，所述第二多个晶体管集成在公共半导体管芯内。
11.根据权利要求6所述的系统，其中，所述第一多个晶体管中的每一个晶体管是垂直n沟道功率晶体管。
12.根据权利要求6所述的系统，其中，所述第一多个晶体管中的每一个晶体管是垂直p沟道功率晶体管。
13.根据权利要求6所述的系统，其中，所述第二多个晶体管中的每一个晶体管是垂直n沟道功率晶体管。
14.根据权利要求6所述的系统，其中，所述第二多个晶体管中的每一个晶体管是垂直p沟道功率晶体管。
15.根据权利要求6所述的系统，其中，所述第一多个晶体管中的每一个晶体管是垂直的基于鳍状物的多栅极晶体管。
16.根据权利要求6所述的系统，其中，所述第二多个晶体管中的每一个晶体管是垂直的基于鳍状物的多栅极晶体管。
17.根据权利要求6所述的系统，进一步包括印刷电路板，其中，所述第一半导体封装和所述第二半导体封装作为多相桥式电路的部分被安装到所述印刷电路板。
18.一种方法，包括：
以相同的取向将相同类型的至少两个垂直沟道晶体管安装到被配置为沿着限定凹部的边界的第一表面和第二表面安装到衬底的导电夹的所述凹部，使得漏极接触部或源极接触部耦合到所述导电夹，并且使得栅极接触部和源极接触部或漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的相同长轴延伸。
19.根据权利要求18所述的方法，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述漏极接触部电耦合到所述导电夹，并且所述栅极接触部和所述源极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸，并且所述方法进一步包括：
将所述导电夹安装到所述衬底；以及
将所述导电夹耦合到被配置为驱动多相电机的半桥电路的接地参考节点。
20.根据权利要求18所述的方法，其中，所述至少两个垂直沟道晶体管中的每一个垂直沟道晶体管的所述源极接触部电耦合到所述导电夹，并且所述栅极接触部和所述漏极接触部延伸而在所述凹部内被暴露并且沿着所述导电夹的所述相同长轴延伸，并且所述方法进一步包括：
将所述导电夹安装到所述衬底；以及
将所述导电夹耦合到被配置为驱动多相电机的半桥电路的电池电源节点。
CN201711374979.9A 2016-12-23 2017-12-19 共接触部半导体器件封装 Active CN108242436B (zh)

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3385981A1 (en) * 2017-04-04 2018-10-10 Nexperia B.V. Power apparatus
US10784213B2 (en) * 2018-01-26 2020-09-22 Hong Kong Applied Science and Technology Research Institute Company Limited Power device package
EP3633715A1 (en) * 2018-10-02 2020-04-08 Infineon Technologies Austria AG Multi-clip structure for die bonding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929519A (en) * 1989-12-22 1999-07-27 Hitchi, Ltd. Semiconductor module including switching device chips and diode chips
CN1613148A (zh) * 2002-01-18 2005-05-04 国际整流器公司 带有共封装管芯的半导体器件
CN102097346A (zh) * 2009-10-29 2011-06-15 万国半导体股份有限公司 功率半导体封装

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3374491B2 (ja) * 1993-12-24 2003-02-04 株式会社デンソー 車両用発電電動装置
JP3365250B2 (ja) * 1997-04-28 2003-01-08 関西日本電気株式会社 ステッピングモータ駆動装置
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US7573107B2 (en) * 2004-09-23 2009-08-11 International Rectifier Corporation Power module
US8089147B2 (en) * 2005-11-02 2012-01-03 International Rectifier Corporation IMS formed as can for semiconductor housing
US7832925B2 (en) * 2007-12-05 2010-11-16 International Business Machines Corporation Apparatus and method for simulating heated airflow exhaust of an electronics subsystem, electronics rack or row of electronics racks
US8860194B2 (en) * 2012-11-01 2014-10-14 International Rectifier Corporation Buck converter power package
US8880929B2 (en) * 2012-11-19 2014-11-04 Blackfire Research Corporation Indirect clock measuring and media adjustment
US9425296B2 (en) * 2013-09-09 2016-08-23 Qualcomm Incorporated Vertical tunnel field effect transistor
US9541639B2 (en) * 2014-03-05 2017-01-10 Delphi Technologies, Inc. MIMO antenna with elevation detection
US20160336324A1 (en) * 2015-05-15 2016-11-17 Qualcomm Incorporated Tunnel field effect transistor and method of making the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929519A (en) * 1989-12-22 1999-07-27 Hitchi, Ltd. Semiconductor module including switching device chips and diode chips
CN1613148A (zh) * 2002-01-18 2005-05-04 国际整流器公司 带有共封装管芯的半导体器件
CN102097346A (zh) * 2009-10-29 2011-06-15 万国半导体股份有限公司 功率半导体封装

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