CN108155908A - A kind of fuse of digital analog converter trims test method - Google Patents
A kind of fuse of digital analog converter trims test method Download PDFInfo
- Publication number
- CN108155908A CN108155908A CN201711362385.6A CN201711362385A CN108155908A CN 108155908 A CN108155908 A CN 108155908A CN 201711362385 A CN201711362385 A CN 201711362385A CN 108155908 A CN108155908 A CN 108155908A
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- fuse
- trims
- test
- circuit
- trimming
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/109—Measuring or testing for dc performance, i.e. static testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
- H03M1/1076—Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of fuses of digital analog converter to trim test method, and circuit original state (before trimming) parameter testing trims an output voltage test statistics and trims code calculating, fuse programming and trim rear precision test.Low level accuracy test trims an output voltage test statistics and trims code calculating.Low 7 precision are tested first and judge whether the chips are overriding chip according to the precision result of low level；If low level meets required precision, according to operating condition and the temporal characteristics that an output voltage is tested are trimmed, a progress voltage sample is trimmed, and calculate average output voltage to test circuit, ensures to trim the stability of an output voltage；Output voltage sampled result completion according to trimming a little trims the calculating of code.
Description
Technical field
The invention belongs to IC testing method field, specifically based on Teradyne Inc. of U.S. J750 integrated circuits
Test system and UF190R probe stations, the fuse for developing digital analog converter trim test method design, meet the essence of such circuit
Degree demand.
Background technology
Digital analog converter is widely used in all kinds of electricity in the fields such as radio, radar, digital communication, observing and controlling, instrument and meter
In sub-circuit.Such device parameters is accurately tested, not only ensure that the quality of product, is also digital analog converter
Circuit design provide data supporting.With the rapid development of electronic technology, digital analog converter is also towards high-speed, high precision side
To continuous development, what it is with this development trend is that requirement to its test method and means of testing is higher and higher.Therefore, it explores
High precision digital-to-analog converter measuring technology has a very important significance.
For the higher circuit of precision, it can not ensure accuracy requirement in circuit design stage, it is necessary to be packaged into finished product electricity
Fuse is carried out before road to trim, it is made to meet required precision.The invention can be adapted for certain 12 overriding d convertor circuit
Fuse trim and test.
Invention content
For above-mentioned technical deficiency, the purpose of the present invention is certain 12 Wei Ke Xiu tune voltage outputs analog-digital chip is carried out
Fuse trims test method design, to reach the requirement for improving chip precision.
The technical solution adopted by the present invention to solve the technical problems is：A kind of fuse of d convertor circuit trims survey
Method for testing includes the following steps：
1) input condition of each signal is set, and resolution chart is worked out according to sequential, zero point error, gain is carried out to circuit
Error static parameter test；
2) chip output voltage when test circuit switch is individually opened, is recorded as B0~B12；If B1~B7 respectively with
The difference of B0, which is respectively less than, sets voltage value, then the chip meets fuse and trims condition, carries out next step；Otherwise it is unsatisfactory for repairing
Tune condition is denoted as unqualified chip；
3) by B8~B12 compared with corresponding theoretical value and calculating difference, and its minimum value is sought；Using the minimum value as base
Point, by it is other everybody mathematic interpolation is carried out with the basic point, obtain the opposite amount of trimming；Post-layout simulation results exhibit according to circuit is repaiied to opposite
Tune amount is encoded, and is searched closest to the corresponding coding of relative variation calculated above, positioning needs the fuse position trimmed；
According to the position for treating scorification silk, fuse programming work is completed.
The post-layout simulation results exhibit according to circuit encodes the opposite amount of trimming, and searches closest to calculated above opposite
The corresponding coding of variable quantity, positioning needs the fuse position trimmed, according to the position for treating scorification silk；Complete fuse programming saddlebag
Include following steps：
It obtains corresponding trimming code according to emulation table；
Code will be trimmed first is converted to binary form, the as value of b5-b0；
Then one for " 1 " of numerical value in b5-b0 is selected, according to the correspondence of the input and output of decoder, is found out
Position of the a2-a0 numerical value for " 1 " is carried out power on operation by the information of corresponding a2-a0 according to the information, and fuse corresponding in this way is just
It blows；It is all blown until by fuse of the numerical value in b5-b0 for " 1 ".
Test is trimmed for 12 Wei Ke Xiu tune voltage output analog-digital chips.
The invention has the advantages that and advantage：
1. the present invention trims test method for the fuse of digital analog converter, there is performance stabilization, trim precision height, reliability
The features such as strong；.
2. the present invention trims the test program design phase in fuse, the variation of resistance after every fuse programming is fully considered,
Optimization trims algorithm, ensures the controllability and traceability of every fuse programming.
Description of the drawings
Fig. 1 is that circuit fuse trims the block diagram designed with parameter testing；
Fig. 2 is the timing waveform between each signal of circuit；
Fig. 3 is that circuit fuse trims process flow diagram flow chart.
Specific embodiment
With reference to embodiment, the present invention is described in further detail.
As shown in figure 3, the present invention with Mr. Yu 12 can Xiu tune voltage output analog-digital chips trim test, ensure electric
The required precision on road.Circuit original state (before trimming) parameter testing, trim an output voltage test statistics and trim code calculate,
Fuse programming and trim rear precision test.Low level accuracy test trims an output voltage test statistics and trims code calculating.First
Low 7 precision are tested and judge whether the chips are overriding chip according to the precision result of low level；If low level is expired
According to operating condition and the temporal characteristics that an output voltage is tested are trimmed, a progress is trimmed to test circuit for sufficient required precision
Voltage sample, and average output voltage is calculated, ensure to trim the stability of an output voltage；Output voltage according to trimming a little is adopted
Sample result is completed to trim the calculating of code.
The establishment of fuse programming program.The calculating knot of code is put in order and trimmed according to the resistance value of fuse during circuit design
Fruit will trim a yard median (binary system) and trim the one-to-one correspondence of fuse progress of position, and result is " 1 " in number of bits
Fuse is into powering on programming.
Circuit trims the test of rear key parameter, according to the operating condition and temporal characteristics of overriding circuit, test circuit
Integral nonlinearity and differential nonlinearity parameter judge the precision of chip whether is improved after trimming.
In the wafer stage of certain 12 circuit, using Teradyne Inc. of the U.S. J750 integrated circuit test systems and
UF190R probe stations are to circuit progress fuse trims test program design, fuse trims pcb board G- Design.Scheme implement include with
Lower step：
The letters such as the electric current flowed into when the chip design layout and supply voltage, programming fuse that are provided according to circuit design side
Breath selects suitable integrated circuit test system, formulates wafer scale and trims testing scheme, Design PCB fuse trims circuit board figure；
The test program design phase is trimmed in fuse, fully considers the variation of resistance after every fuse programming, optimization trims algorithm, ensures
The controllability and traceability of every fuse programming；Carry out test pair to the dominant static parameter of chip respectively before and after trimming
Than analysis is facilitated to trim the variation of front and rear precision.
Network entirely is trimmed by trimming power supply control, and when the circuit is operating, the main power source power supply of circuit trims power supply and do not supply
Electricity；When needing to trim, the main power source of circuit is not powered, and needs programming by trimming power supply power supply, and by control logic gating
Fuse opens the way switch, and the electric current for having about 200mA or so flows through fuse and blown.Control logic is by PCB fuses
The relay control on circuit board is trimmed, avoids accidentally programming that chip functions is caused to fail.
The design for trimming algorithm is developed using the VBT scripts that J750 integrated circuit test systems carry at random.
Input condition setting supply voltage, reference voltage, the data terminal recommended according to device in the J750 integrated circuit test systems
Incoming level etc. works out corresponding resolution chart according to the sequence diagram of circuit, ensures that device is in running order, using J750 collection
Into the output voltage of the BPMU measuring units test critical data transfer point of circuit test system, judge whether that satisfaction trims item
Part trims condition if met, powers on the fuse of programming corresponding points；Complete fuse programming work.
After the completion of trimming, the key parameter of the chips is tested again, whether verification precision meets handbook requirement.
It is as shown in Figure 1 that the fuse of digital analog converter trims test method design frame chart.Entire test design includes two portions
Point：First, front and rear progress functional parameter test is trimmed to circuit according to the operating conditions such as supply voltage, benchmark as defined in handbook；
Second is that circuit trim network carry out fuse trim algorithm design, the circuit function for trimming network be in resistor matching precision not
Reach 12 precision by adjusting resistance values in the case of enough.
According to the operating condition of circuit, the input condition of each signal, and root are set in J750 integrated circuit test systems
Resolution chart is worked out according to the input timing of Fig. 2, zero point error, gain error static parameter test are carried out to circuit.The static state is joined
Number test design mainly uses the MSO modules of J750, according to the information such as working frequency setting test machine specified in circuit handbook
Sample rate and hits, sampling test is carried out to resolution chart, using the method for mathematical statistics, to sampled data according to correlation
Formula counting circuit trim before zero point error, gain error, judge whether chip meets the condition of trimming；If it is unsatisfactory for repairing
Tune condition, it is unqualified chip to judge this chips.
For the chip of test passes before trimming, the logical construction of network is trimmed according to circuit, test circuit switch is independent
Output voltage during unlatching, is recorded as B0~B12.If B1~B7 is less than the voltage value of 1LSB with the difference of B0 respectively, then
The chips meet fuse and trim condition, can carry out fuse and trim；Otherwise this chips is unsatisfactory for trimming condition, is denoted as and does not conform to
Lattice chip.
By B8~B12 compared with corresponding theoretical value and calculating difference, and seek its minimum value.Using the minimum value as basic point,
By it is other everybody mathematic interpolation is carried out with the basic point, calculate relative variation.Post-layout simulation results exhibit according to circuit is repaiied to opposite
Tune amount is encoded, and is searched closest to the corresponding coding of relative variation calculated above, positioning needs the fuse position trimmed.
The power supply of disconnecting circuit work starts the power supply that fuse trims program, according to the position for treating scorification silk, opens on pcb board successively
Corresponding relay completes everybody fuse programming work.
Finally integral nonlinearity and differential nonlinearity parameter are tested according to test method before trimming, verify circuit
Whether precision meets handbook requirement.
Wherein, the opposite amount of trimming is encoded according to the post-layout simulation results exhibit of circuit, searched closest to phase calculated above
The corresponding coding to variable quantity, positioning need the fuse position trimmed specific as follows：
Each fuse of bit8-bit12 is trimmed in network all comprising 6 fuses (b5-b0), and selection powers on programming which root
Fuse is realized by a 3-6 decoding circuit.The decoder input be a2, a1, a0 respectively, export for b5, b4, b3,
b2、b1、b0.Correspondence between them is as shown in table 1.
1 3-6 decoder truth tables of table
Method be according to emulation table obtain it is corresponding trim code, code will be trimmed first and be converted to binary form, as b5-
The value of b0；Then one for " 1 " of numerical value in b5-b0 is selected, the information of corresponding a2-a0 is found out according to upper table, according to should
Position of the a2-a0 numerical value for " 1 " is carried out power on operation by numerical information, and fuse corresponding so is just blown.Repeat work above
Make, all blown until by fuse of the numerical value in b5-b0 for " 1 ".
The programming fuse that powers on of other can be completed using same method to work.
Claims (3)
1. a kind of fuse of d convertor circuit trims test method, which is characterized in that includes the following steps：
1) chip output voltage when test circuit switch is individually opened, is recorded as B0~B12；If B1~B7 is respectively with B0's
Difference is less than setting voltage value, then the chip meets fuse and trims condition, carries out next step；Otherwise it is unsatisfactory for trimming item
Part is denoted as unqualified chip；
2) by B8~B12 compared with corresponding theoretical value and calculating difference, and its minimum value is sought；It, will using the minimum value as basic point
Other everybody carries out mathematic interpolation with the basic point, obtains the opposite amount of trimming；Post-layout simulation results exhibit according to circuit is to the opposite amount of trimming
It is encoded, is searched closest to the corresponding coding of relative variation calculated above, positioning needs the fuse position trimmed；According to
It treats the position of scorification silk, completes fuse programming work.
2. a kind of fuse of d convertor circuit according to claim 1 trims test method, which is characterized in that described
Post-layout simulation results exhibit according to circuit encodes the opposite amount of trimming, and searches corresponding closest to relative variation calculated above
Coding, positioning needs the fuse position trimmed, according to the position for treating scorification silk；Fuse programming work is completed to include the following steps：
It obtains corresponding trimming code according to emulation table；
Code will be trimmed first is converted to binary form, the as value of b5-b0；
Then one for " 1 " of numerical value in b5-b0 is selected, according to the correspondence of the input and output of decoder, finds out correspondence
A2-a0 information, position of the a2-a0 numerical value for " 1 " is subjected to power on operation according to the information, fuse corresponding so just blows
；It is all blown until by fuse of the numerical value in b5-b0 for " 1 ".
3. a kind of fuse of d convertor circuit according to claim 1 trims test method, which is characterized in that is used for
12 Wei Ke Xiu tune voltage output analog-digital chips trim test.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711362385.6A CN108155908A (en) | 2017-12-18 | 2017-12-18 | A kind of fuse of digital analog converter trims test method |
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| CN201711362385.6A CN108155908A (en) | 2017-12-18 | 2017-12-18 | A kind of fuse of digital analog converter trims test method |
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| CN108155908A true CN108155908A (en) | 2018-06-12 |
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Cited By (4)
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| CN112650639A (en) * | 2020-12-18 | 2021-04-13 | 中国电子科技集团公司第四十七研究所 | Trimming system capable of achieving automatic trimming of sensor |
| CN113410156A (en) * | 2021-08-20 | 2021-09-17 | 上海芯龙半导体技术股份有限公司南京分公司 | Trimming method of wafer |
| CN114002588A (en) * | 2022-01-04 | 2022-02-01 | 苏州贝克微电子股份有限公司 | High-precision semiconductor chip trimming test method |
| CN115148270A (en) * | 2022-09-05 | 2022-10-04 | 江苏万邦微电子有限公司 | ID coding fuse array fusing method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112650639A (en) * | 2020-12-18 | 2021-04-13 | 中国电子科技集团公司第四十七研究所 | Trimming system capable of achieving automatic trimming of sensor |
| CN113410156A (en) * | 2021-08-20 | 2021-09-17 | 上海芯龙半导体技术股份有限公司南京分公司 | Trimming method of wafer |
| CN114002588A (en) * | 2022-01-04 | 2022-02-01 | 苏州贝克微电子股份有限公司 | High-precision semiconductor chip trimming test method |
| CN114002588B (en) * | 2022-01-04 | 2022-04-29 | 苏州贝克微电子股份有限公司 | High-precision semiconductor chip trimming test method |
| CN115148270A (en) * | 2022-09-05 | 2022-10-04 | 江苏万邦微电子有限公司 | ID coding fuse array fusing method |
| CN115148270B (en) * | 2022-09-05 | 2022-12-09 | 江苏万邦微电子有限公司 | ID coding fuse array fusing method |
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Application publication date: 20180612 |