CN115148270A - ID coding fuse array fusing method - Google Patents
ID coding fuse array fusing method Download PDFInfo
- Publication number
- CN115148270A CN115148270A CN202211076146.5A CN202211076146A CN115148270A CN 115148270 A CN115148270 A CN 115148270A CN 202211076146 A CN202211076146 A CN 202211076146A CN 115148270 A CN115148270 A CN 115148270A
- Authority
- CN
- China
- Prior art keywords
- fuse
- code
- test
- parameters
- burned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses an ID coding fuse array fusing method, which comprises the following steps: (10) pre-fusing parameter testing: testing chip parameters, and removing chips with unqualified parameters; (20) code introduction: retrieving the previously written codes from the TXT file and importing the codes into the test code; (30) run test code burn fuses: and running the test code, and when the digital channel corresponding to the fuse to be burned is high voltage, driving the relay by the driver to switch on the fuse corresponding to the code and burn the fuse. The ID coding fuse array fusing method successfully realizes the fusing of the multi-bit fuse array by utilizing the digital channel of the automatic test equipment; meanwhile, the serial number function of the chip is realized by a method of storing the number data in an external TXT file.
Description
Technical Field
The invention belongs to the technical field of semiconductor device production test, and particularly relates to an ID coding fuse array fusing method.
Background
In the process of large scale integrated circuit production, it is often necessary to perform fine tuning on electrical parameters such as voltage, current, etc. in the circuit by blowing a designated fuse, so as to obtain more accurate electrical parameter output.
The multi-channel TR component is usually provided with a beam control chip with a read-back ID coding function. In order to avoid the defects of unstable data, erasability and the like existing in a common data storage mode and ensure the stability and reliability of ID codes, the beam control chip with the read-back ID coding function mostly adopts a fuse array to represent coding, namely, stable and reliable ID codes are endowed to the beam control chip by burning fuses.
The conventional chip fuse burning method, as described in the chinese invention patent "method for monitoring fuse burning achievement rate in chip test" (application No. 201510790708.6, published 2016.04.06), includes:
step S1, establishing a fuse truth table, wherein the fuse truth table comprises the corresponding relation between each reference voltage measured value range of a chip and a fuse needing to be blown; a reference voltage standard value is also set in the fuse truth table; a reference voltage lowest reference value and a reference voltage highest reference value are set in the fuse truth table;
s2, testing one chip, and monitoring a reference voltage measured value of the chip; when the measured value of the reference voltage is less than or equal to the lowest reference value of the reference voltage or more than or equal to the highest reference value of the reference voltage, directly judging that the current chip is a bad chip; when the lowest reference value of the reference voltage is less than the measured value of the reference voltage and less than the highest reference value of the reference voltage, continuing the subsequent steps;
step S3, the reference voltage measured value falls into a specific reference voltage measured value range, if the reference voltage measured value falls into a reference voltage target range in which the reference voltage standard value is located, the chip is qualified, and if the reference voltage measured value is outside the reference voltage target range, each fuse of the chip corresponding to the specific reference voltage measured value range is blown according to the corresponding relation between each reference voltage measured value range and the fuse needing to be blown in the fuse truth table;
step S4, measuring the reference voltage measured value of the chip again, and if the obtained reference voltage measured value is within a reference voltage target range of the reference voltage standard value, the chip successfully burns the fuse, and the next chip test or other item tests are executed; otherwise, judging that the fuse wire of the corresponding section is not blown according to the actual variation of the reference voltage for blowing the fuse wire of each section and the theoretical variation of the reference voltage, and returning to the step S3 to perform the process of blowing the fuse wire again.
The fuse burning process is usually completed by adopting an automatic testing device in combination with a relay and a capacitor. When the fuse wire and the capacitor are disconnected by the relay, the capacitor is charged; when the fuse wire is connected with the capacitor by the relay, the capacitor discharges to the fuse wire to generate an instant large current, the fuse wire heats and vaporizes, and the fuse wire is blown. One fuse corresponds to one relay. Since such beam control chips with read-back ID encoding function represent an encoding fuse array of often 30 bits or more, ATE equipment usually provides only a few relay channels, even some digital automated test equipment is not equipped with relay channels at all. And other parameter tests of the chip can occupy some control resources. Especially, in the multi-SITE test, the number of channels is even less than the requirement.
Meanwhile, according to the conventional fuse burning method for the parameter fuse, a target fuse to be burned is determined according to a fuse table after a parameter to be adjusted is measured, a set fuse combination needs to be obtained in the process of burning the ID fuse array, wherein the set fuse combination comprises information such as batch number, date number, particle number and the like, the information such as batch date and the like is used as a prefix of unified number of each batch, the qualified chips of the whole batch of wafers need to be numbered one by one through the particle number, and the conventional fuse burning method obviously cannot meet the requirement of automatic continuous production.
In summary, the prior art has the following problems: it is difficult to provide burn-in and serial numbering services for multi-bit ID-coded fuse arrays due to the limited access of automated test equipment.
Disclosure of Invention
The invention aims to provide an ID coding fuse array fusing method, which utilizes a digital channel of automatic test equipment to successfully realize the fusing of a multi-bit fuse array; meanwhile, the serial number function of the chip is realized by a method of storing the number data in an external TXT file.
The technical solution for realizing the purpose of the invention is as follows:
an ID coding fuse array burning method comprises the following steps:
(10) Testing parameters before fusing: testing chip parameters, and removing chips with unqualified parameters;
(20) Code import: retrieving the previously written codes from the TXT file and importing the codes into the test code;
(30) And (3) burning a fuse wire by running a test code: and running the test code, and when the digital channel corresponding to the fuse to be burned is high voltage, driving the relay by the driver to switch on the fuse corresponding to the code and burn the fuse.
Preferably, the step of (30) running the test code to burn the fuse comprises:
(31) Importing a test code: converting decimal codes in the TXT file into test codes of a binary tester, and importing the test codes into a memory of the tester;
(32) Digital channel matching: matching the digital channels of the tester with the fuses one by one, so that the digital channel corresponding to the fuse to be burned is high voltage, and the digital channel corresponding to the fuse not to be burned is low voltage;
(33) Fusing a fuse wire: the driver drives the relay to switch on the fuse corresponding to the code, and the fuse to be burned is burned.
Compared with the prior art, the invention has the following remarkable advantages:
1. the required relay control channels are few: the invention adopts a running test code mode to burn the fuse, solves the problem of insufficient relay control channels, uses a digital channel to replace the relay control channel to give out signals (the number of digital channels of a common tester reaches 128 or even 512), and drives the relay through a driver. Compared with the prior art, the method has higher efficiency, so that the test time is greatly shortened.
2. The test production continuity is good: the invention writes the code in the TXT file, and after extracting and using, 1 is added for storing again. This method allows for better continuity in test production than writing the initial code into the program, and does not require the program to be changed and compiled each time.
The invention is described in further detail below with reference to the figures and the detailed description.
Drawings
FIG. 1 is a flowchart illustrating an embodiment of a method for fusing an ID encoded fuse array according to the present invention.
FIG. 2 is a flow chart of the step of melting the fuse with the running test code of FIG. 1.
FIG. 3 is a flowchart of another embodiment of a method for fusing an ID encoded fuse array according to the present invention.
FIG. 4 is a flowchart of another embodiment of a method for burning an ID encoded fuse array according to the present invention.
Detailed Description
As shown in FIG. 1, the ID coding fuse array fusing method of the present invention comprises the following steps:
(10) Testing parameters before fusing: testing chip parameters, and removing chips with unqualified parameters;
(20) Code import: retrieving the previously written code from the TXT file and importing the code to the test code;
(30) And (3) burning a fuse wire by running a test code: and running the test code, and when the digital channel corresponding to the fuse to be burned is high voltage, driving the relay by the driver to switch on the fuse corresponding to the code and burn the fuse.
The digital channel voltage corresponding to the fuse wire which does not need to be fused is low, and no influence is caused.
Preferably, as shown in fig. 2, the step of (30) running the test code to burn the fuse includes:
(31) Test code import: decimal codes in the TXT file are converted into test codes of a binary tester and are led into a memory of the tester;
(32) Digital channel matching: matching the digital channels of the tester with the fuses one by one, so that the digital channel corresponding to the fuse to be burned is high voltage, and the digital channel corresponding to the fuse not to be burned is low voltage;
(33) Fusing a fuse wire: the driver drives the relay to switch on the fuse corresponding to the code, and the fuse to be burned is burned.
The invention adopts the mode of running the test code to burn the fuse wire, uses the digital channel to replace the relay control channel to give a signal, and then drives the relay through the driver, thereby effectively solving the problem of insufficient relay control channel. Compared with the prior art, the method has higher efficiency, so that the test time is greatly shortened.
As an improvement, as shown in FIG. 3, the ID coding fuse array fusing method of the invention comprises the following steps:
(10) Testing parameters before fusing: testing chip parameters, and removing chips with unqualified parameters;
(20) Code import: retrieving the previously written code from the TXT file and importing the code to the test code;
(30) Running a test code to burn a fuse: the test code is run, when the digital channel corresponding to the fuse to be burned is high voltage, the driver drives the relay to switch on the fuse corresponding to the code, and the fuse is burned;
preferably, as shown in fig. 2, the step of (30) running the test code to burn the fuse includes:
(31) Test code import: decimal codes in the TXT file are converted into test codes of a binary tester and are led into a memory of the tester;
(32) Digital channel matching: matching the digital channels of the testing machine with the fuses one by one, so that the digital channel corresponding to the fuse to be burned is high voltage, and the digital channel corresponding to the fuse which is not burned is low voltage;
(33) Fusing a fuse: and the driver drives the relay to switch on the fuse corresponding to the code and fuse the to-be-burned fuse.
(40) Fuse coding comparison: and reading back the code of the burnt fuse, comparing the code with the code retrieved from the TXT file, judging that the burning is successful if the code is consistent with the code retrieved from the TXT file, adding 1 to the code, storing the code back into the TXT file, and judging that the burning is failed if the code is inconsistent with the code, and performing failure treatment on the chip.
As a further improvement, as shown in FIG. 4, the ID coding fuse array fusing method of the present invention comprises the following steps:
(10) Testing parameters before fusing: testing chip parameters, and removing chips with unqualified parameters;
(20) Code import: retrieving the previously written codes from the TXT file and importing the codes into the test code;
(30) Running a test code to burn a fuse: running test codes, when the digital channel corresponding to the fuse to be burned is high voltage, a driver is used for driving a relay, the fuse corresponding to the code is switched on, and the fuse is burned;
preferably, as shown in fig. 2, the step of (30) running the test code to burn the fuse includes:
(31) Test code import: converting decimal codes in the TXT file into test codes of a binary tester, and importing the test codes into a memory of the tester;
(32) Digital channel matching: matching the digital channels of the tester with the fuses one by one, so that the digital channel corresponding to the fuse to be burned is high voltage, and the digital channel corresponding to the fuse not to be burned is low voltage;
(33) Fusing a fuse: the driver drives the relay to switch on the fuse corresponding to the code, and the fuse to be burned is burned.
(40) Fuse coding comparison: reading back the code of the burnt fuse, comparing the code with the code retrieved from the TXT file, if the code is consistent with the code retrieved from the TXT file, judging that the burning is successful, adding 1 to the code, storing the code back into the TXT file, if the code is inconsistent with the code retrieved from the TXT file, judging that the burning is failed, and performing failure treatment on the chip;
(50) And (3) testing parameters after fusing: and testing the parameters of the chip after the fuse wire is burned, and if the parameters do not exceed the standard, the product is qualified.
The invention writes the code in TXT file, and after extracting and using, adds 1 to restore. This method allows for better continuity in test production than writing the initial code into the program, and does not require the program to be changed and compiled each time.
Claims (5)
1. An ID coding fuse array fusing method is characterized by comprising the following steps:
(10) Testing parameters before fusing: testing chip parameters, and removing chips with unqualified parameters;
(20) Code import: retrieving the previously written code from the TXT file and importing the code to the test code;
(30) And (3) burning a fuse wire by running a test code: and running the test code, and when the digital channel corresponding to the fuse to be burned is high voltage, driving the relay by the driver to switch on the fuse corresponding to the code and burn the fuse.
2. The ID-coded fuse array blowing method of claim 1, wherein the (30) run test code fuse blowing step includes:
(31) Importing a test code: converting decimal codes in the TXT file into test codes of a binary tester, and importing the test codes into a memory of the tester;
(32) Digital channel matching: matching the digital channels of the tester with the fuses one by one, so that the digital channel corresponding to the fuse to be burned is high voltage, and the digital channel corresponding to the fuse not to be burned is low voltage;
(33) Fusing a fuse: and the driver drives the relay to switch on the fuse corresponding to the code and fuse the to-be-burned fuse.
3. The method of claim 1 or 2, further comprising the following steps after the step of (30) running the test code to burn the fuse:
(40) Fuse coding comparison: and reading back the code of the burnt fuse, comparing the code with the code retrieved from the TXT file, judging that the burning is successful if the code is consistent with the code retrieved from the TXT file, adding 1 to the code, storing the code back into the TXT file, and judging that the burning is failed if the code is inconsistent with the code, and performing failure treatment on the chip.
4. The method of claim 3, further comprising the following steps after the fuse code comparison step (40):
(50) And (3) testing parameters after fusing: and testing the parameters of the chip after the fuse wire is burned, and if the parameters do not exceed the standard, the product is qualified.
5. The method of claim 1 or 2, further comprising the following steps after the step of (30) running the test code to burn the fuse:
(50) And (3) testing parameters after fusing: and testing the parameters of the chip after the fuse wire is burned, and if the parameters do not exceed the standard, the product is qualified.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211076146.5A CN115148270B (en) | 2022-09-05 | 2022-09-05 | ID coding fuse array fusing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211076146.5A CN115148270B (en) | 2022-09-05 | 2022-09-05 | ID coding fuse array fusing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115148270A true CN115148270A (en) | 2022-10-04 |
| CN115148270B CN115148270B (en) | 2022-12-09 |
Family
ID=83415568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211076146.5A Active CN115148270B (en) | 2022-09-05 | 2022-09-05 | ID coding fuse array fusing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115148270B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679367A (en) * | 2016-01-14 | 2016-06-15 | 中国电子科技集团公司第五十八研究所 | Programmer for MTM anti-fuse PROM |
| CN108155908A (en) * | 2017-12-18 | 2018-06-12 | 中国电子科技集团公司第四十七研究所 | A kind of fuse of digital analog converter trims test method |
| CN109450433A (en) * | 2018-08-02 | 2019-03-08 | 上海芯哲微电子科技股份有限公司 | A kind of two-way integrated circuit trims device |
-
2022
- 2022-09-05 CN CN202211076146.5A patent/CN115148270B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679367A (en) * | 2016-01-14 | 2016-06-15 | 中国电子科技集团公司第五十八研究所 | Programmer for MTM anti-fuse PROM |
| CN108155908A (en) * | 2017-12-18 | 2018-06-12 | 中国电子科技集团公司第四十七研究所 | A kind of fuse of digital analog converter trims test method |
| CN109450433A (en) * | 2018-08-02 | 2019-03-08 | 上海芯哲微电子科技股份有限公司 | A kind of two-way integrated circuit trims device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115148270B (en) | 2022-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6940781B2 (en) | Semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory | |
| US7237158B2 (en) | Intelligent binning for electrically repairable semiconductor chips | |
| US7781890B2 (en) | Structure and method for parallel testing of dies on a semiconductor wafer | |
| US6943575B2 (en) | Method, circuit and system for determining burn-in reliability from wafer level burn-in | |
| US6789224B2 (en) | Method and apparatus for testing semiconductor devices | |
| US5142541A (en) | Error-bit generating circuit for use in a non-volatile semiconductor memory device | |
| KR20020005960A (en) | Semiconductor integrated circuit | |
| US5764650A (en) | Intelligent binning for electrically repairable semiconductor chips | |
| US20070094555A1 (en) | Component testing and recovery | |
| US6600686B2 (en) | Apparatus for recognizing chip identification and semiconductor device comprising the apparatus | |
| US6175529B1 (en) | Semiconductor integrated circuit device and method for manufacturing the same | |
| US7325182B2 (en) | Method and circuit arrangement for testing electrical modules | |
| CN115148270B (en) | ID coding fuse array fusing method | |
| US4544882A (en) | Apparatus for testing an integrated circuit chip without concern as to which of the chip's terminals are inputs or outputs | |
| JP2007310989A (en) | Semiconductor storage device and testing method therefor | |
| CN103366827A (en) | Storage device and method for testing storage device through testing machine | |
| JPH01502534A (en) | 3-state circuit test equipment | |
| US7284168B2 (en) | Method and system for testing RAM redundant integrated circuits | |
| US20090094494A1 (en) | Semiconductor integrated circuit and method of testing same | |
| TW497243B (en) | Integrated circuit with a test driver and test facility for testing an integrated circuit | |
| CN111025197A (en) | Test circuit and test method for E-fuse fusing characteristic | |
| JP2007010605A (en) | Testing device and testing method | |
| KR100443508B1 (en) | A semiconductor memory module | |
| US7159157B2 (en) | Apparatus and method for testing a device for storing data | |
| CN115963377A (en) | Test trimming circuit and chip to be trimmed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |