CN108155232B - 高电子迁移率晶体管器件 - Google Patents
高电子迁移率晶体管器件 Download PDFInfo
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- CN108155232B CN108155232B CN201711261540.5A CN201711261540A CN108155232B CN 108155232 B CN108155232 B CN 108155232B CN 201711261540 A CN201711261540 A CN 201711261540A CN 108155232 B CN108155232 B CN 108155232B
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- 239000007943 implant Substances 0.000 claims description 32
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 30
- 229910052733 gallium Inorganic materials 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 239000011737 fluorine Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 4
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims 6
- 229910002601 GaN Inorganic materials 0.000 claims 4
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims 2
- 239000012212 insulator Substances 0.000 description 20
- 238000000034 method Methods 0.000 description 14
- 239000002019 doping agent Substances 0.000 description 12
- 229910002704 AlGaN Inorganic materials 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical group [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005389 semiconductor device fabrication Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
本发明公开了高电子迁移率晶体管器件。一种器件包括第一高电子迁移率晶体管(HEMT)和第二HEMT。第一HEMT包括第一栅极、耦合到第一栅极的源极以及耦合到第一栅极的漏极。第二HEMT包括耦合到源极和漏极的第二栅极。第二HEMT具有比第一HEMT更低的阈值电压。
Description
相关美国申请
本申请要求由A.Shibib等人于2016年12月2日提交的标题为“GaN中的伪肖特基结构及其制造方法(Psuedo-Schottky Structure in GaN and Method ofManufacturing)”、序列号为62/429,627的美国临时申请的优先权,并在此通过引用整体并入本文。
背景技术
高电子迁移率晶体管(HEMT)是场效应晶体管(FET),其结合具有不同带隙的两种材料之间的结作为沟道而不是掺杂区域,如对于金属氧化物半导体FET(MOSFET)的典型情况。HEMT的特征在于低导通电阻、高击穿电压和低开关损耗,使其成为例如无线通信系统中优异的功率器件(例如功率放大器)。
特别地,在硅衬底上使用氮化镓(GaN)和铝GaN(AlGaN)的HEMT是高效的,因此不仅在无线通信系统中,而且在许多其他应用(包括例如电压转换器)中非常有用。
尽管基于GaN的器件通常不具有pn结,并且与传统的硅基功率晶体管相比通常具有快速反向恢复,但是当以反向模式(当漏极-源极电压Vds变负时)操作GaN HEMT时,仍然有显著的开关损耗。取决于反向峰值电流,反向导通模式电压可以远高于2伏特,例如达到4伏特或更高,从而导致功率损耗和降低效率。
发明内容
根据本发明的实施例通过减少HEMT器件的反向恢复时间来减少开关损耗并且提高效率,从而也提高器件的开关速度。在这些实施例中,这是采用包括主器件和基本上与主器件平行设置在单个集成电路或芯片上的附加低反向电压器件器件的结构来实现的。
在一个实施例中,为了实现低反向电压,低阈值电压(Vth)HEMT与芯片上的主HEMT连接。在这样的实施例中,低Vth HEMT与主HEMT完全集成。也就是说,主HEMT和低Vth HEMT以这样的方式连接,例如,低Vth HEMT的漏极电连接到单独的栅极,低Vth HEMT的漏极和栅极都电连接到主HEMT的源极,而低Vth HEMT的源极电连接到主HEMT的漏极。因此,主HEMT具有一个栅极,低Vth HEMT具有另一个栅极,并且主HEMT和低Vth HEMT共享相同的源极和相同的漏极。公开的是用于实现包括主HEMT和集成的低Vth HEMT的器件结构的不同配置。
在根据本发明的实施例中,低Vth HEMT既不会影响整个器件的泄漏,也不会由于低Vth HEMT电连接到源极电势而由耦合到栅极区域的漏极而触发。低Vth HEMT仅在反向操作模式下被激活。值得注意的是,低Vth HEMT不会干扰主HEMT的功能。
本领域技术人员在阅读了在各个附图中示出的以下详细描述之后,将认识到根据本发明的实施例的这些和其他目标与优势。
附图说明
并入本说明书中并构成本说明书的一部分的附图示出了本发明的实施例,并且与说明书一起用于解释本发明的原理。相似的数字在整个附图和说明书中表示相似的元件。图形可能不是按比例绘制的。
图1示出了根据本发明的实施例中的高电子迁移率晶体管(HEMT)器件的结构的一部分。
图2A、2B和2C示出了根据本发明的实施例中的包括主HEMT和低阈值电压(Vth)HEMT的HEMT器件。
图3A和3B示出了根据本发明的实施例中的包括主HEMT和低Vth HEMT的HEMT器件。
图3C和3D示出了根据本发明的实施例中的形成包括主HEMT和低Vth HEMT的HEMT器件。
图4A和4B示出了根据本发明的实施例中的包括主HEMT和低Vth HEMT的HEMT器件。
图5A和5B示出了根据本发明的实施例中的包括主HEMT和低Vth HEMT的HEMT器件。
图6是根据本发明的实施例中的用于制造HEMT器件的方法的示例的流程图。
具体实施方式
在以下本发明的详细描述中,阐述了许多具体细节以便提供对本发明的透彻理解。然而,本领域技术人员将会认识到,本发明可以在没有这些具体细节或有其等同物的情况下实施。在其他实例中,众所周知的方法、过程、组件和电路未被详细描述,以免不必要地模糊本发明的各方面。
以下详细描述的一些部分是按照制造半导体器件的操作的过程、逻辑块、处理和其他符号表示来呈现的。这些描述和表示是半导体器件制造领域的技术人员用来将其工作的本质最有效地传达给本领域其他技术人员的手段。在本申请中,过程、逻辑块、处理等被认为是导致期望结果的步骤或指令的自洽序列。这些步骤是需要对物理量进行物理操纵的步骤。但是,应该牢记的是,所有这些和类似的术语都与适当的物理量相关联,并且仅仅是适用于这些量的便利标签。除非特别指出,否则从以下讨论中可以明显看出,应当理解,贯穿本申请使用诸如“生长”、“移除”、“形成”、“连接”、“蚀刻”、“沉积”或类似的术语的讨论,指的是半导体器件制造的动作和处理(例如,图6的流程图600)。
应该理解,附图不必按比例绘制,并且仅示出了所描绘的器件和结构的一部分以及形成那些结构的各种层。为了简化讨论和说明,可以针对一个或两个器件或结构来描述过程,尽管实际上可以形成多于一个或两个器件或结构。
图1示出了根据本发明的实施例中的高电子迁移率晶体管(HEMT)器件100的结构的一部分。在实施例中,该结构被集成到单芯片中。
在本文中可以被称为整个HEMT器件的HEMT器件100至少包括第一HEMT 110和第二HEMT 120。HEMT 110和120也可以被称为场效应晶体管(FET)。
第一HEMT 110在本文可以被称为主HEMT。第二HEMT 120具有比第一HEMT器件110低的阈值电压(Vth),并因此第二HEMT 120在本文中可以被称为低Vth HEMT。HEMT 120也可以被称为连接到主HEMT 110的伪肖特基FET,因为它表现得像具有相对低的导通电压(例如,相对于常规二极管)的二极管。
在实施例中,低Vth HEMT 120在正向导通模式下具有较高的阈值电压,但是在反向导通模式下具有低得多的阈值电压。在本实施例中,HEMT器件100更加免疫于由于漏极电压耦合到栅极而可能发生的伪栅极触发。
主HEMT 110包括第一栅极131、漏极或漏区140以及源极或源区142。低Vth HEMT120包括第二栅极132、漏极140和源极142。也就是说,主HEMT110和低Vth HEMT 120以这样的方式连接:低Vth HEMT的栅极132电连接到主HEMT的漏极140,低Vth HEMT的漏极和栅极两者都电连接到主HEMT的源极142,并且低Vth HEMT的源极电连接到主HEMT的漏极。因此,主HEMT具有一个栅极,低Vth HEMT具有另一个栅极,并且主HEMT和低Vth HEMT共享相同的源极和相同的漏极。在实施例中,低Vth HEMT 120占据的面积大约是主HEMT 110占据的面积的百分之五到百分之十五。
在实施例中,低Vth HEMT分布在主HEMT中。换句话说,这样的器件的阵列中的一些主HEMT包括集成的低Vth HEMT,而其他主HEMT不包括集成的低Vth HEMT。可选地,所有主HEMT都包括集成的低Vth HEMT。
在实施例中,低Vth HEMT 120在正常操作模式下关断,并且仅在漏极-源极电压(Vds)为负(反向模式)时导通。有利地,低Vth HEMT 120在反向模式中比主HEMT 110更快导通,从而允许电流在较低的电压下流动;电压和电流的乘积(功率)因此较低,因此功率损耗也较低。因此,增加低Vth HEMT 120与主HEMT 110相结合,通过减少HEMT器件100的反向恢复时间,减少了开关损耗,并提高了效率,从而加快了开关速度。此外,低Vth HEMT120既不会影响HEMT器件100的泄漏,也不会由于低Vth HEMT电连接到源极电势而由耦合到栅极区域的漏极而触发。
如将要描述的,低Vth HEMT可以以多种不同的方式实现。因此,根据本发明的实施例可以以不同的技术实现,如下面的示例所述。根据本发明的实施例不限于这些示例,并且本文体现的构思可以被并入到其他技术中。
图2A是包括类似于图1的主HEMT 110的主HEMT 210的HEMT器件200的一部分的实施例的截面表示。在图2A的实施例中,主HEMT 210包括源极232和漏极234。主HEMT 210还包括第一栅极237。第一栅极237包括掺杂区域236和接触238。接触238可以是欧姆的或者它可以是非欧姆的(例如,其可以是肖特基接触)。
主HEMT 210还包括含镓(Ga)的第一层230。在实施例中,第一层230是GaN基的(例如,第一层包含GaN)。在一个这样的实施例中,层230是铝GaN(AlGaN)层。可以使用除了GaN基材料之外的材料,例如铝砷化镓(AlGaAs),来代替AlGaN。
源极232和漏极234形成在第一层230中。二维电子气(2DEG)层228与层230相邻,并且第二层226与2DEG层相邻。在实施例中,第二层226由GaN构成,但是本发明不限于此;例如,可以使用GaAs来代替GaN。缓冲层224与第二层226相邻,并且衬底(例如,硅)层222与缓冲层相邻。在实施例中,缓冲层224包括氮化铝以及AlGaN和GaN的交替层。缓冲层224中的交替层可以具有不同的厚度。
图2B是包括类似于图1的低Vth HEMT 120的低Vth HEMT 220的HEMT器件200的一部分的实施例的截面表示。如上所述,主HEMT 210和低Vth HEMT 220在同一芯片上,并如图1所示耦合(还可参见下文讨论的图2C)。在图2B的实施例中,低Vth HEMT 220包括第二栅极239。
值得注意的是,第一栅极237和第一层230的配置(第一配置)不同于第二栅极239和第一层230的配置(第二配置)。具体地,第一栅极237和第二栅极239是不同的。
在图2A的实施例中,第一栅极237包括在接触238与第一层230之间的第一掺杂区域236。第一掺杂区域236掺杂有第一浓度C1的掺杂剂。在实施例中,第一掺杂区域236掺杂有第一浓度的p型掺杂剂。在一个这样的实施例中,p型掺杂剂是镁。
在图2B的实施例中,第二栅极包括在接触238与第一层230之间的第二掺杂区域240。第二掺杂区域240掺杂有第二浓度C2的掺杂剂。在实施例中,第二掺杂区域240掺杂有第二浓度的p型掺杂剂。在一个这样的实施例中,p型掺杂剂是镁。
值得注意的是,第二掺杂区域240中的掺杂剂的第二浓度C2小于第一掺杂区域236中的掺杂剂的第一浓度C1。即,低Vth HEMT 220中的第二掺杂区域240中的掺杂剂的浓度C2小于主HEMT 210的第一掺杂区域236中的掺杂剂的浓度C1。在实施例中,第一掺杂区域236中的掺杂浓度大约为1018-1019每立方厘米(cm3),而第二掺杂区域240中的掺杂浓度大约为1017每cm3。一般而言,对于实际中可能使用的掺杂浓度范围,第一掺杂区域236中的掺杂浓度处于该范围的最高点或者较高点,而第二掺杂区域240中的掺杂浓度处于该范围的最低点或者较低点。通常,阈值电压与掺杂浓度成正比。因为第二掺杂区域240中的掺杂浓度C2小于第一掺杂区域236中的掺杂浓度C1,所以HEMT 220的阈值电压小于主HEMT 210的阈值电压。
此外,在实施例中,低Vth HEMT 220的栅极经由金属层或互连242物理连接和电连接到源极232。图2C是在根据本发明的实施例中的HEMT器件200的一部分的俯视图的表示。在图2C的示例中,低Vth HEMT 220位于两个主HEMT 210之间。主HEMT 210的栅极237通过隔离结构256与低Vth HEMT 220的栅极239隔离。低Vth HEMT 220的栅极239通过金属层或互连242物理连接和电连接到源极232。
图3A和3B示出了在根据本发明的实施例中实现低Vth HEMT的另一种方式。图3A是包括类似于图1的主HEMT 110的主HEMT 310的HEMT器件300的一部分的实施例的截面表示。HEMT器件300包括源极232、漏极234、第一层230(例如,AlGaN层)、2DEG层228、第二层226(例如,GaN层)、缓冲层226和衬底层222,如本文先前所述。在图3A的实施例中,主HEMT 310包括第一栅极312。
图3B是包括类似于图1的低Vth HEMT 120的低Vth HEMT 320的HEMT器件300的一部分的实施例的截面表示。如上所述,主HEMT 310和低Vth HEMT 320在同一芯片上并如图1所示耦合。在图3B的实施例中,低Vth HEMT器件320包括第二栅极314。
在图3A和3B的实施例中,第一栅极312和第一层230的配置(第一配置)不同于第二栅极314和第一层230的配置(第二配置)。具体地,相对于低Vth HEMT来说,主HEMT的第一层230包括不同的注入区域。
在图3A的实施例中,第一注入区域322被设置在第一栅极312下方的第一层230(例如,AlGaN层)中。通过在形成第一栅极312之前将材料注入层230而形成第一注入区域322,如图3C所示。在图3B的实施例中,第二注入区域324设置在第二栅极314下方的第一层230中。通过在形成第二栅极314之前将材料注入层230中而形成第二注入区域324,如图3D所示。
在实施例中,注入到注入区域322和324中的材料是氟。值得注意的是,注入到第二注入区域324中的注入剂量I2小于注入到第一注入区域322中的注入剂量I1。也就是说,低Vth HEMT 320中的第二注入区域324中的注入剂量I2小于主HEMT 310的第一注入区域322中的注入剂量I1。在实施例中,第一注入区域322中的注入剂量大约为1014每平方厘米(cm2),而第二注入区域324中的注入剂量大约为1012每cm2。一般而言,对于实际中可以使用的注入剂量范围,第一注入区域322中的注入剂量处于该范围的最高点或者较高点,而第二注入区域324中的注入剂量处于该范围的最低点或者较低点。通常,阈值电压与注入剂量成正比。因为第二注入区域324中的注入剂量I2小于第一注入区域322中的注入剂量I1,所以HEMT 320的阈值电压小于主HEMT 310的阈值电压。
图4A和图4B示出了在根据本发明的实施例中实现低Vth HEMT的另一种方式。图4A是包括类似于图1的主HEMT 110的主HEMT 410的HEMT器件400的一部分的实施例的截面表示。HEMT器件400包括源极232、漏极234、第一层230(例如,AlGaN层)、2DEG层228、第二层226(例如,GaN层)、缓冲层226和衬底层222,如本文先前所述。在图4A的实施例中,主HEMT 410包括第一栅极412。
图4B是包括类似于图1的低Vth HEMT 120的低Vth HEMT 420的HEMT器件400的一部分的实施例的截面表示。如上所述,主HEMT 410和低Vth HEMT 420在同一芯片上并如图1所示耦合。在图4B的实施例中,低Vth HEMT器件420包括第二栅极414。
值得注意的是,第一栅极412和第一层230的配置(第一配置)不同于第二栅极414和第一层230的配置(第二配置)。具体地,对于主HEMT相对低Vth HEMT不同的绝缘体被包括在各自的栅极和第一层230之间。
在图4A的实施例中,第一绝缘体422设置在第一栅极412与第一层230之间。第一绝缘体422具有第一厚度T1。在实施例中,第一绝缘体422至少部分地嵌入到第一层230中。
在图4B的实施例中,第二绝缘体424设置在第二栅极414与第一层230之间。第二绝缘体424具有第二厚度T2。在实施例中,第二绝缘体424至少部分地嵌入到第一层230中。绝缘体422和424可以是例如氧化铝(Al2O3)或二氧化硅(SiO2)。
值得注意的是,第二厚度T2小于第一厚度T1。也就是说,低Vth HEMT420中的绝缘体424的厚度小于主HEMT 410中的绝缘体422的厚度。在实施例中,厚度T2比厚度T1小约一个数量级。例如,绝缘体422的厚度T1可以是大约1000埃,而绝缘体424的厚度T2可以是大约200埃。通常,阈值电压与绝缘体的厚度成正比。因为绝缘体424比绝缘体422薄,所以HEMT420的阈值电压小于主HEMT 410的阈值电压。
图5A和图5B示出了根据本发明的实施例中实现低Vth HEMT(例如,在肖特基金属半导体FET(MESFET)中)的另一种方式。图5A是包括类似于图1的主HEMT 110的主HEMT 510的HEMT器件500的一部分的实施例的截面表示。HEMT器件500包括源极232、漏极234、第一层230(例如,AlGaN层)、2DEG层228、第二层226(例如,GaN层)、缓冲层226和衬底层222,如本文先前所述。在图5A的实施例中,主HEMT 510包括第一金属栅极512。
图5B是包括类似于图1的低Vth HEMT 120的低Vth HEMT 520的HEMT器件500的一部分的实施例的截面表示。如上所述,主HEMT 510和低Vth HEMT 520在同一芯片上并如图1所示耦合。在图5B的实施例中,低Vth HEMT器件520包括第二金属栅极514。
然而,第一栅极512和第一层230的配置(第一配置)不同于第二栅极514和第一层230的配置(第二配置)。具体地,在图5A和图5B的实施例中,第一栅极512凹入到第一层230中第一深度D1,而第二栅极514凹入到第一层230中第二深度D2。
值得注意的是,第二深度D2小于第一深度D1。因此,低Vth HEMT 520中的第二栅极514下面的第一层230的厚度小于主HEMT 510中的栅极512下面的第一层230的厚度。通常,阈值电压与凹入的深度成正比。因为第二栅极514凹入第一层230的深度D2小于第一栅极512凹入第一层230的深度D1,所以HEMT 520的阈值电压小于主HEMT 510的阈值电压。
图6是根据本发明的实施例中制造HEMT器件(例如,图1、2A、2B、3A、3B、4A、4B、5A和5B的器件)的方法或过程的示例的流程图600。图6是在包括主HEMT和低Vth HEMT的单个HEMT器件的情况下讨论的,但是可以容易地扩展到多个这种器件的并行制造。
在图6中,被描述为单独框的操作可以在相同的处理步骤中(即,在相同的时间间隔中,在前面的处理步骤之后并且在下一个处理步骤之前)组合并执行。而且,这些操作可以以与下文描述的顺序不同的顺序执行。此外,制造工艺和步骤可以与本文讨论的工艺和步骤一起进行;也就是说,在本文所示和所述的步骤之前、之间和/或之后可以有多个处理步骤。重要的是,根据本发明的实施例可以结合这些其他(可能是传统的)工艺和步骤实施,而不会显着干扰它们。一般而言,根据本发明的实施例可以替代传统工艺的一部分而不显著影响外围工艺和步骤。
在框602中,在衬底(例如,硅衬底)上和其上方形成缓冲层。
在框604中,在缓冲层上和其上方形成包括Ga的层(例如,图2A的第二层226)。在实施例中,该层包括GaN。
在图6的框606中,在框604中形成的层上和其上方形成2DEG层。
在框608中,在2DEG层上方形成包括Ga的层(例如,图2A的第一层230)。在实施例中,该层包括AlGaN。
在框610中,在框608中形成的层中形成源极和漏极。
在框612中,形成用于主HEMT的栅极或栅极结构,以及用于低Vth HEMT的栅极或栅极结构。值得注意的是,用于主HEMT的栅极和在框608中形成的层(以下称为第一层)的配置(第一配置)不同于用于低Vth HEMT的栅极和第一层的配置(第二配置)。第一配置和第二配置可以并行形成(在相同的处理步骤中),但是本发明不限于此。
参考图2A、2B和2C的实施例,框612中包括的处理步骤包括在栅极237中沉积第一浓度的掺杂剂以形成第一掺杂区域236并在栅极239中沉积第二浓度的掺杂剂以形成第二掺杂区域240,其中第二浓度小于第一浓度。此外,在实施例中,框602中包括的处理步骤包括在栅极239和源极之间形成金属连接。
参考图3A和3B的实施例,框612中包括的处理步骤包括:在形成栅极312之前,注入第一剂量的注入材料以在第一层230中形成第一注入区域322,然后在第一注入区域上方形成栅极312。框612中包括的处理步骤还包括:在形成栅极314之前,注入第二剂量的注入材料以在第一层230中形成第二注入区域324,然后在第二注入区域上方形成栅极314,其中第二剂量小于第一剂量。
参照图4A和4B的实施例,框612中包括的处理步骤包括:在形成栅极412之前,在第一层230中形成凹槽并且在凹槽中形成第一绝缘体422并从凹槽延伸,使得第一绝缘体具有第一厚度并且至少部分地嵌入在第一层中,然后在第一绝缘体上方形成栅极412。框612中包括的处理步骤还包括:在形成栅极414之前,在第一层230中形成另一个凹槽,并在该凹槽中形成第二绝缘体424并从该凹槽延伸,使得第二绝缘体具有第二厚度并且至少部分地嵌入第一层中,其中第二厚度小于第一厚度。
参考图5A和5B的实施例,框612中包括的处理步骤包括:在形成栅极512之前,在第一层230中形成具有第一深度的凹槽,然后在凹槽中沉积并形成金属并从该凹槽延伸以形成栅极512。框612中包括的处理步骤还包括:在形成栅极514之前,在第一层230中形成具有第二深度的另一个凹槽,然后在该凹槽中沉积并形成金属并从该凹槽延伸以形成栅极514,其中第二深度小于第一深度。
总之,在根据本发明的实施例中,HEMT器件结构包括主HEMT和与单个芯片上的主HEMT基本上平行的附加低Vth HEMT。如图2A、2B、3A、3B、4A、4B、5A和图5B的实施例中所示例的,可以根据并入器件中的HEMT技术的类型来制造不同类型的HEMT器件。本文公开的HEMT器件结构的实施例通过减少HEMT器件的反向恢复时间来减少开关损耗并提高效率,从而也提高了开关速度。
出于说明和描述的目的已经呈现了本发明的特定实施例的前述描述。它们不旨在穷举或者将本发明限制为所公开的确切形式,并且根据上述教导许多修改和变化是可能的。选择和描述实施例是为了最好地解释本发明的原理及其实际应用,从而使本领域的其他技术人员能够最佳地利用本发明以及具有适合于预期的特定用途的具有各种修改的各种实施例。意图是本发明的范围由所附权利要求及其等同物限定。
Claims (20)
1.一种器件,包括:
第一结构,包括:
第一高电子迁移率晶体管HEMT,包括:
第一栅极;
耦合到所述第一栅极的源极;以及
耦合到所述第一栅极的漏极;以及
第二HEMT,包括:
耦合到所述第一HEMT的所述源极的第二栅极和第二漏极;以及
耦合到所述第一HEMT的所述漏极的第二源极;
其中所述第二HEMT具有比所述第一HEMT更低的阈值电压;以及
第二结构,包括:
单个HEMT,其中所述单个HEMT包括:栅极,耦合到所述第一HEMT的所述源极的源极,以及耦合到所述第一HEMT的所述漏极的漏极,其中所述单个HEMT具有比所述第二HEMT更高的阈值电压。
2.如权利要求1所述的器件,其中所述第一栅极包括第一接触和具有第一浓度的掺杂的第一区域,其中所述第二栅极包括第二接触和具有第二浓度的掺杂的第二区域,其中所述第二浓度小于所述第一浓度。
3.如权利要求2所述的器件,还包括将所述第二栅极连接至所述源极的金属连接。
4.如权利要求2所述的器件,其中所述掺杂包括p型掺杂。
5.如权利要求1所述的器件,还包括:
包含镓的层;
设置在所述包含镓的层中所述第一栅极下方的第一区域,其中所述第一区域包括第一剂量的注入材料;以及
设置在所述包含镓的层中所述第二栅极下方的第二区域,其中所述第二区域包括第二剂量的所述注入材料,并且其中所述第二剂量小于所述第一剂量。
6.如权利要求1所述的器件,还包括:
包含镓的层;
设置在所述第一栅极与所述包含镓的层之间的第一区域,其中所述第一区域包括具有第一厚度的绝缘材料;以及
设置在所述第二栅极与所述包含镓的层之间的第二区域,其中所述第二区域包括具有第二厚度的绝缘材料,并且其中所述第二厚度小于所述第一厚度。
7.如权利要求1所述的器件,还包括包含镓的层,其中所述第一栅极凹入到所述包含镓的层中第一深度,并且其中所述第二栅极凹入到所述包含镓的层中第二深度,并且其中所述第二深度小于所述第一深度。
8.一种电子器件,包括:
第一高电子迁移率晶体管HEMT结构,包括:
第一场效应晶体管FET,包括:
包含镓的层;
第一栅极;
第一源极;以及
第一漏极;以及
第二FET,包括:
所述包含镓的层;以及
耦合到所述第一源极的第二栅极和第二漏极;以及
耦合到所述第一漏极的第二源极;
其中所述第二FET具有比所述第一FET更低的阈值电压;以及第二HEMT结构,包括:
单个FET,其中所述单个FET包括:栅极,耦合到所述第一源极的源极,以及耦合到所述第一漏极的漏极,其中所述第二HEMT结构的所述单个FET具有比所述第二FET更高的阈值电压。
9.如权利要求8所述的电子器件,其中所述第一栅极包括第一接触和具有第一浓度的掺杂的第一区域,其中所述第二栅极包括第二接触和具有第二浓度的掺杂的第二区域,并且其中所述第二浓度小于所述第一浓度。
10.如权利要求9所述的电子器件,还包括:
所述包含镓的层中的源区;以及
将所述第二栅极连接到所述包含镓的层中的所述源区的金属连接。
11.如权利要求8所述的电子器件,还包括:
设置在所述包含镓的层中所述第一栅极下方的第一区域,其中所述第一区域包括第一剂量的氟;以及
设置在所述包含镓的层中所述第二栅极下方的第二区域,其中所述第二区域包括第二剂量的氟,并且其中所述第二剂量小于所述第一剂量。
12.如权利要求8所述的电子器件,还包括:
设置在所述第一栅极与所述包含镓的层之间的第一区域,其中所述第一区域包括具有第一厚度的绝缘材料;以及
设置在所述第二栅极与所述包含镓的层之间的第二区域,其中所述第二区域包括具有第二厚度的绝缘材料,并且其中所述第二厚度小于所述第一厚度。
13.如权利要求8所述的电子器件,其中所述第一栅极凹入到所述包含镓的层中第一深度,并且其中所述第二栅极凹入到所述包含镓的层中第二深度,并且其中所述第二深度小于所述第一深度。
14.如权利要求8所述的电子器件,其中所述包含镓的层包括铝氮化镓AlGaN,并且其中所述电子器件还包括:
在所述包含AlGaN的层中形成的源区;
在所述包含AlGaN的层中形成的漏区;
耦合到所述包含AlGaN的层的包含GaN的第二层;
在所述包含AlGaN的层与所述第二层之间的二维电子气2DEG层;
耦合到所述第二层的缓冲层;以及
耦合到所述缓冲层的包含硅的衬底。
15.一种电子器件,包括:
第一高电子迁移率晶体管HEMT结构,包括:
第一场效应晶体管FET,包括:
源极;
漏极;以及
用于包括第一栅极和包含镓的层的结构的第一配置,所述第一配置耦合到所述源极和所述漏极;以及
第二FET,包括:
用于包括第二栅极、第二源极、第二漏极和所述包含镓的层的结构的第二配置,其中所述第二栅极和第二漏极耦合到所述第一FET的所述源极,以及所述第二源极耦合到所述第一FET的所述漏极;以及
第二HEMT结构,包括:
单个FET,其中所述单个FET包括:栅极,耦合到所述第一FET的所述源极的源极,以及耦合到所述第一FET的所述漏极的漏极,其中所述第二HEMT结构的所述单个FET具有比所述第二FET更高的阈值电压。
16.如权利要求15所述的电子器件,还包括将所述第二栅极连接到所述第一FET的所述源极的金属连接,其中所述第一栅极包括第一接触和具有第一浓度的掺杂的第一区域,其中所述第二栅极包括第二接触和具有第二浓度的掺杂的第二区域,并且其中所述第二浓度小于所述第一浓度。
17.如权利要求15所述的电子器件,其中:
所述第一配置包括设置在所述包含镓的层中所述第一栅极下方的第一区域,其中所述第一区域包括第一剂量的氟;以及
所述第二配置包括设置在所述包含镓的层中所述第二栅极下方的第二区域,其中所述第二区域包括第二剂量的氟,并且其中所述第二剂量小于所述第一剂量。
18.如权利要求15所述的电子器件,其中:
所述第一配置包括设置在所述第一栅极和所述包含镓的层之间的第一区域,其中所述第一区域包括具有第一厚度的绝缘材料;以及
所述第二配置包括设置在所述第二栅极和所述包含镓的层之间的第二区域,其中所述第二区域包括具有第二厚度的绝缘材料,并且其中所述第二厚度小于所述第一厚度。
19.如权利要求15所述的电子器件,其中所述第一栅极凹入到所述包含镓的层中第一深度,并且其中所述第二栅极凹入到所述包含镓的层中第二深度,并且其中所述第二深度小于所述第一深度。
20.如权利要求15所述的电子器件,其中所述包含镓的层包括铝氮化镓AlGaN,其中所述源极和所述漏极位于所述包含AlGaN的层中,并且其中所述电子器件还包括:
包含GaN的第二层;
在所述包含AlGaN的层与所述第二层之间的二维电子气2DEG层;
耦合到所述第二层的缓冲层;以及
耦合到所述缓冲层的包含硅的衬底。
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JP2015056557A (ja) | 2013-09-12 | 2015-03-23 | 株式会社東芝 | 半導体装置 |
US9941267B2 (en) | 2014-09-09 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company Limited | Electro-static discharge protection circuit |
JP6831752B2 (ja) * | 2016-06-08 | 2021-02-17 | パナソニック株式会社 | 基板電圧制御回路 |
US10204995B2 (en) | 2016-11-28 | 2019-02-12 | Infineon Technologies Austria Ag | Normally off HEMT with self aligned gate structure |
US10224426B2 (en) | 2016-12-02 | 2019-03-05 | Vishay-Siliconix | High-electron-mobility transistor devices |
US10381473B2 (en) | 2016-12-02 | 2019-08-13 | Vishay-Siliconix | High-electron-mobility transistor with buried interconnect |
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2017
- 2017-07-06 US US15/643,306 patent/US10224426B2/en active Active
- 2017-12-01 EP EP23154511.2A patent/EP4207286A1/en active Pending
- 2017-12-01 KR KR1020170164286A patent/KR102114157B1/ko active IP Right Grant
- 2017-12-01 EP EP17204984.3A patent/EP3331026A3/en not_active Ceased
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- 2017-12-04 CN CN201711261540.5A patent/CN108155232B/zh active Active
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US10651303B2 (en) | 2020-05-12 |
EP4207286A1 (en) | 2023-07-05 |
US20180158940A1 (en) | 2018-06-07 |
US20190198651A1 (en) | 2019-06-27 |
KR102114157B1 (ko) | 2020-05-22 |
EP3331026A3 (en) | 2018-10-31 |
KR20180063848A (ko) | 2018-06-12 |
CN108155232A (zh) | 2018-06-12 |
EP3331026A2 (en) | 2018-06-06 |
US10224426B2 (en) | 2019-03-05 |
CN114582971A (zh) | 2022-06-03 |
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