CN107980173B - 通过有源层挖掘工艺而具有隔离的周边接触部的三维存储器器件 - Google Patents
通过有源层挖掘工艺而具有隔离的周边接触部的三维存储器器件 Download PDFInfo
- Publication number
- CN107980173B CN107980173B CN201680047973.8A CN201680047973A CN107980173B CN 107980173 B CN107980173 B CN 107980173B CN 201680047973 A CN201680047973 A CN 201680047973A CN 107980173 B CN107980173 B CN 107980173B
- Authority
- CN
- China
- Prior art keywords
- memory cells
- dielectric
- memory
- vertical length
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 23
- 238000009412 basement excavation Methods 0.000 title description 3
- 230000015654 memory Effects 0.000 claims abstract description 93
- 230000002093 peripheral effect Effects 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000003860 storage Methods 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 3
- 238000005429 filling process Methods 0.000 claims description 2
- 239000012777 electrically insulating material Substances 0.000 claims 3
- 210000004027 cell Anatomy 0.000 abstract description 23
- 210000000352 storage cell Anatomy 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 description 14
- 238000011049 filling Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005065 mining Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Human Computer Interaction (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Geometry (AREA)
Abstract
描述了一种具有阵列区域和周边区域的三维存储器器件。所述阵列区域具有存储单元的三维堆叠体。所述周边区域具有从所述存储单元的三维堆叠体上方延伸到所述存储单元的三维堆叠体下方的接触部。所述周边区域大体上没有所述存储单元的三维堆叠体的导电和/或半导电层。
Description
技术领域
本发明的领域总体上涉及半导体技术,并且更具体而言,涉及通过有源层挖掘工艺而具有隔离的周边接触部的三维存储器器件。
背景技术
移动设备的出现使得非易失性半导体存储器制造商对他们的器件的密度产生了浓厚兴趣。通常,移动设备不利用有利于基于半导体的非易失性存储器件的磁盘驱动。然而,从历史上看,半导体存储器件不具有与磁盘驱动相同的存储密度。
为了使半导体存储器的存储密度更接近或超过磁盘驱动,非易失性存储器器件制造商正在开发三维存储器技术。就三维存储器技术而言,在存储器件内,个体存储单元被垂直地堆叠在另一个存储单元顶上。因此,三维存储器器件可以以更小的封装、成本和功耗包络为移动设备提供类似磁盘驱动的存储密度。然而,三维存储器器件的制造提出了新的制造技术挑战。
附图说明
结合以下附图,根据以下具体实施方式可以获得对本发明的更好的理解,在附图中:
图1示出了三维存储器电路;
图2a至图2j示出了用于制造三维存储器电路的第一实施例;
图3a至图3g示出了用于制造三维存储器电路的第二实施例;
图4示出了用于制造三维存储器器件的方法;
图5示出了计算系统的实施例。
具体实施方式
图1示出了用于三维NAND FLASH存储器的存储单元区域的电路示意图。如在图1中观察到的,电路包括耦合在选择栅极源极晶体管102和选择栅极漏极晶体管103之间的NANDFLASH存储单元的堆叠体101。选择栅极源极晶体管102被耦合到源极线104。存储单元的堆叠体101可以被实施为FLASH晶体管的三维堆叠体,FLASH晶体管与选择栅极源极晶体管102和选择栅极漏极晶体管103以及帮助实施例如存储单元的NAND功能、感测放大器、行解码器、地址解码器等的其它晶体管器件(未示出)一起被单片集成为半导体芯片上的三维存储阵列。
在各种实施例中,存储单元堆叠体101可以物理地夹在选择栅极源极晶体管102(其例如可以存在于存储单元堆叠体下面)和选择栅极漏极晶体管103(其例如可以存在于存储单元上方)之间。由于存储单元堆叠体在高度上生长以容纳存储单元的更多层以便增大存储器器件的密度,因此可能更难以在下部电路结构(例如,选择栅极源极晶体管102、逻辑晶体管或解码器)与各种线路后端(BEOL)输入和/或输出(I/O)结构(例如,功率输入、读/写输入、擦除输入)之间形成电接触部/互连。在此,存储单元堆叠体101的绝对高度(sheerheight)要求从BEOL I/O结构到位于选择栅极源晶体管102处或其下面的层级的很长(例如,>5μm)的接触部结构。
图2a至图2j描绘了用于制造三维NAND FLASH存储器器件的第一方法。各种实施例可以减轻与很长的接触部结构相关联的问题。
首先在图2a中观察到部分完成的器件。如在图2a中观察到的,用于实施例如感测放大器、地址解码器、行解码器等的下部层级晶体管203被设置在器件的存储单元区域下面的半导体衬底上。在下部晶体管203上方形成多个源极层204。源极层204用于形成存储器器件的源极线104。在实施例中,源极层包括电介质层204_1(例如,氧化物层)、一个或多个导电层204_2和另一个上部电介质层204_3。
下部电介质层204_1有助于将下部晶体管203与上部存储单元层叠结构207、209绝缘。导电层204_2形成实际的源极线布线。在实施例中,导电层204_2是由金属(例如,钨硅化物(WSix))的下部层和多晶硅的上部层组成的多层结构。上部电介质层204_3将源极线204_2与蚀刻停止层205绝缘。蚀刻停止层可以由例如金属、金属氧化物(例如,氧化铝)中的任一种组成。蚀刻停止层205的目的将在下面得到更成分的解释。
选择栅极源极晶体管结构206形成在蚀刻停止层205之上。在实施例中,选择栅极源极晶体管结构包括处于电介质(例如,氧化物)层206_2下面的多晶硅层206_1。为了简单起见,图2a示出了仅在“周边”区域202中被图案化的多晶硅层206_1。
堆叠的存储器件(例如,FLASH晶体管单元)的第一层叠结构207形成在电介质层206_2上方。在实施例中,堆叠的存储器件由交替的多晶硅层和氧化物层构成。在各种实施例中,在单个层叠结构中可以存在例如多于二十层的存储器件。另一个电介质(例如,氮化物)层208存在于堆叠的存储器件的第一层叠结构207与堆叠的存储器件的第二层叠结构209之间,以有效地充当用于下部阵列单元形成和从顶部阵列平台(deck)到下部阵列平台的接触部/插塞形成的硬掩模。
选择栅极漏极晶体管器件结构210形成在第二堆叠存储层叠结构209上方。在实施例中,选择栅极漏极晶体管器件结构210由多晶硅的第一下部层210_1和上部电介质层210_2(例如,由氮化物组成)形成。再次,为了例示方便,多晶硅选择栅极晶体管层210_1被描绘为仅在周边区域202内被图案化。
衬底的阵列区域201区域包括实际存储器件本身,而周边区域202是保留区域,在其中形成很长的接触部结构以将BEOL I/O接触部结构(未示出)连接到下部选择栅极源极晶体管结构206,甚至下部源极线结构204,或甚至下部晶体管203。
形成这些接触部的潜在问题是在周边202内的堆叠的层叠结构区域207、209的导电多晶硅层的存在。在通过需要非常宽且非常深的过孔的周边构造很长的接触部时的先前尝试,使得可以在接触部周围形成适合厚度的电介质,以使它们与导电多晶硅层绝缘。利用沿着接触部整个延伸长度完全围绕接触部的适当厚度和/或均匀性来围绕接触部制造绝缘体未被示为容易重复并可靠的。另一种方法是完全蚀刻掉整个周边区域,其导致在晶圆表面中形成大的过孔开口。然后用最终覆盖整个晶圆表面的电介质材料填充大的周边开口。利用电介质覆盖晶圆表面需要附加的处理程序来从晶圆表面去除电介质(同时留下填充有电介质的周边开口),以准备用于随后的BEOL处理的晶圆表面。
下面紧接着描述的制造方法至少旨在在避免或减少上面刚刚描述的问题和/或处理低效的同时在周边202中形成接触部,所述接触部具有围绕接触部和堆叠层叠结构区域的多晶硅层的适当隔离。
参考图2b,整体结构被涂覆有光致抗蚀剂并被图案化以暴露结构表面上的区域处的开口。蚀刻所暴露的开口以形成在蚀刻停止层205处停止的开放过孔。在实施例中,利用当到达金属或金属氧化物时停止的非选择性蚀刻来执行蚀刻。如在图2c中观察的,开放过孔填充有电介质(例如,氧化物)以形成阵列区域201内的阵列缝隙211_1、以及沿着阵列区域201和周边区域202之间的边界的周边壕沟211_2。阵列缝隙211_1根据存储器器件的架构将两个存储层叠结构207、209解析为较小的存储单元组(例如,确定块大小尺寸)。周边壕沟211_2将存储层叠结构207、209与周边区域202隔离。
参考图2d,整体结构再次被涂覆光致抗蚀剂并被图案化以暴露结构表面上的位于周边区域202内的区域处的开口。还蚀刻所暴露的开口以形成在栅极源极层的多晶硅处停止的开放过孔。参考图2e,然后利用金属填充过孔以形成通往选择栅极源极晶体管层206的接触部212。在实施例中,尽管图中未示出,首先利用氧化物或其它电介质材料填充开放过孔,然后再次蚀刻穿过所述开放过孔直到底部以形成用于随后的接触部金属填充的电介质间隔体层。
参照图2f,整体结构再次被涂覆光致抗蚀剂并被图案化以暴露结构表面上的位于周边区域202内的区域处的另一个开口。所暴露的开口也被蚀刻以形成在源极线布线层204_2处停止的开放过孔。值得注意的是,用于形成图2f的开放过孔的蚀刻穿透了蚀刻停止层205以便到达源极线布线层204_2。在实施例中,使用在金属处停止的非选择性蚀刻(因为源极线布线由金属组成)。
参考图2g,在图2f中产生的过孔被填充有金属以形成通往源极线布线层204_2的接触部213。再次,如上面关于接触部212所讨论的,间隔体层可以形成在接触部与其周围事物之间。
在替代的实施例中,同时利用非选择性蚀刻执行图2d和图2f的蚀刻,所述非选择性蚀刻在到达多晶硅或金属时停止(这样,蚀刻将在到达多晶源极栅极层206时以及到达源极层204的金属时停止)。也可以通过临界尺寸控制而使用于不同深度蚀刻的总蚀刻时间基本上相同,在此,回想结构的表面被光致抗蚀剂覆盖并被图案化,以在期望进行蚀刻的表面中形成开口。通过调整开口的大小,可以确立针对特定时间量的蚀刻的深度,例如,较小的开口可能导致比较大的开口更浅的刻蚀深度。这样,针对应该在栅极源极层206处停止的蚀刻的开口可以被制造得比针对应该在源极层204停止的蚀刻的开口更小。如果图2d和图2f的蚀刻同时执行,则同样地,也可以同时执行图2e和图2g的金属填充。
不管图2d和图2f的蚀刻是同时执行还是分开执行和/或图2e和图2g的金属填充是同时执行还是分开执行,要注意,可能发生蚀刻和金属填充的整个其它序列,其尝试形成通往下面的电路层203的接触部。用于到达层203的接触部的蚀刻和金属填充可以与图2d和图2f的蚀刻以及图2e和图2g的填充分开执行或与其同时执行,与上面提供的教导一致。例如,在同时蚀刻的情况下,针对到达层203的蚀刻的图案化的开口可以被制造得比针对应该到达源极层204的蚀刻的开口更大。
参考图2h,整体结构再次被涂覆光致抗蚀剂并被图案化以暴露结构表面上的周边区域202内的区域处的开口。蚀刻所暴露的开口以形成在蚀刻停止层205处停止的开放过孔。在实施例中,当到达金属或金属氧化物时停止的非选择性蚀刻被用于使蚀刻在蚀刻停止层205(其可以例如由金属或金属氧化物组成)处停止。在另一个实施例中,蚀刻与图2b中执行的蚀刻相同。
如图2i中所观察到的,并非填充形成在图2h中的过孔,而是使开放过孔保持开放213以便暴露周边区域202内的两个堆叠层叠结构区207、209的多晶硅层的环境。然后例如通过环境化学反应蚀刻工艺将暴露的多晶硅层从周边区域挖掘出来或以其它方式去除,所述环境化学反应蚀刻工艺以化学方式去除多晶硅而不是周围的电介质或接触部金属。示例包括热四甲基氢氧化铵(TMAH)。
在从周边区域202移除多晶硅存储层叠结构层之后,生长周边202内的周围电介质和/或利用更多的电介质共形地填充所暴露的开口以形成如图2j所观察到的完整的结构。在此,可以使用共形电介质“填充”工艺(即,符合其应该覆盖的结构的形貌的工艺),例如将液体形式的电介质施加到衬底,然后旋涂液体氧化物以填充由所去除的多晶硅产生的裂缝。然而,值得注意的是,周边202内的电介质的均匀性不是关键参数,因为已经去除了多晶硅。在此,周边202的绝缘材料内的气隙的存在实际上可以改善绝缘的程度。
在形成了图2j的结构之后,BEOL处理可以开始完成器件的制造。BEOL处理可以包括例如在晶圆表面上形成被电耦合到接触部212、213的I/O结构。
注意,图2a到图2j的方法开始于在开始形成周边接触部之前已经完成了用于所有器件的层的结构。也就是说,如图2a所示,已经形成了选择栅极漏极晶体管器件层210。相反,图3a至图3i示出了另一个实施例,其中对周边接触部的处理在完成形成选择栅极漏极晶体管器件之前开始。
图3a示出了向上直到第二存储层叠结构309的完成的结构。然而,并非形成了存在于第二存储层叠结构309上方的选择栅极漏极晶体管器件层,而是形成了(例如,氮化物)牺牲层310。在各种实施例中,氮化物层310被用作用于形成上部存储单元的硬掩模,并且一旦完成了存储单元就牺牲该氮化物层310。
参考图3b,整体结构被涂覆有光致抗蚀剂并被图案化以暴露位于结构表面上的区域处的开口。蚀刻所暴露的开口以形成在蚀刻停止层305处停止的开放过孔。如图3c中所观察的,利用电介质(例如,氧化物)填充开放过孔以形成阵列区域301内的阵列缝隙311_1以及沿着阵列区域301和周边区域302之间的边界的周边壕沟311_2。
如图3d中所观察的,整体结构被涂覆有光致抗蚀剂并被图案化以暴露结构表面上的位于周边区域302内的区域处的开口。蚀刻所暴露的开口以形成在蚀刻停止层305处停止的开放过孔。在此,形成了开放过孔对以更好地暴露周边302内的多晶硅区域。也就是说,因为在周边区域302中还没有形成接触部,所以在图3d的周边区域302中存在比在图2h的周边区域202中存在的更多的要去除的多晶硅。因此,为了暴露更大量的多晶硅,在图3d的方案中蚀刻了更多的过孔。
如图3e中所观察的,挖掘周边区域302内的多晶硅区域。如图3f中所观察的,例如通过生长和/或填充周围氧化物(利用例如上面所描述的共形填充工艺)来利用电介质填充由去除的多晶硅形成的开放空隙。
如图3g中所观察的,在周边302内形成了金属接触部,并且在该结构之上形成了选择栅极漏极晶体管器件层310以形成完成的结构。如上面所描述的,可以在接触部周围形成间隔体。为了在周边内形成金属接触部,可以分开或同时执行对源极栅极306和源极层304的蚀刻。同样地,由蚀刻形成的开口的金属填充可以分开执行或同时执行。在其中同时形成蚀刻的实施例中,可以使用临界尺寸控制来同时产生不同蚀刻深度的蚀刻(例如,用较小的开口实现较浅的蚀刻,并且用较大的开口实现较深的蚀刻)。还可以形成通往下部电路层203的蚀刻和接触部(再次与其它蚀刻和填充同时或分开执行)。在形成了图3g的结构之后,BEOL处理可以开始形成电耦合到接触部314的I/O结构。
尽管上面的描述针对NAND FLASH存储器存储单元技术,但可以设想的是,由其有源层可以由化学挖掘工艺去除的多晶硅或任何其它导电和/或半导电材料组成的其它存储器存储单元技术可以是要利用此处的教导的候选。这种可能的存储单元技术可以包括但不限于基于相变的存储单元、基于铁电的存储单元(例如,FRAM)、基于磁的存储单元(例如MRAM)、基于自旋转移矩的存储单元(例如,STT-RAM)、基于电阻器的存储单元(例如,ReRAM)或基于“忆阻器(Memristor)”的存储单元。
图4示出了上面所描述的方法。如上面所观察的,所述方法包括形成401存储单元的三维堆叠体,其中存储单元的三维堆叠体具有导电和/或半导电材料层。所述方法还包括从存在于与存储器器件的存储区域相邻处的周边区域中挖掘402导电和/或半导电材料层,以及在周边区域内形成从存储单元的三维堆叠体上方向存储单元的三维堆叠体下方延伸的接触部。注意,接触部可以在挖掘工艺之前或之后执行。
图5示出了可以包括如上面所描述的三维存储器器件的计算系统500的实施例。计算系统500可以是个人计算系统(例如,台式机或膝上型计算机)或者移动或手持式计算系统(例如平板设备或智能手机)、或者诸如服务器计算系统之类的较大的计算系统。
如图5所观察到的,基本计算系统可以包括中央处理单元501(其可以包括例如设置在应用处理器或多核处理器上的多个通用处理内核和主存储器控制器)、系统存储器502、显示器503(例如,触摸屏、平板)、本地有线点对点链路(例如,USB)接口504、各种网络I/O功能505(例如以太网接口和/或蜂窝调制解调器子系统)、无线局域网(例如,WiFi)接口506、无线点对点链路(例如,蓝牙)接口507和全球定位系统接口508、各种传感器509_1到509_N(例如,陀螺仪、加速度计、磁力计、温度传感器、压力传感器、湿度传感器等中的一个或多个)、相机510、电池511、功率管理控制单元512、扬声器和麦克风513以及音频编码器/解码器514。
应用处理器或多核处理器550可以包括位于其CPU 501内的一个或多个通用处理内核515、一个或多个图形处理单元516、存储器管理功能517(例如,存储器控制器)和I/O控制功能518。通用处理内核515通常执行操作系统和计算系统的应用软件。图形处理单元516通常执行图形密集型功能以例如生成呈现在显示器503上的图形信息。存储器控制功能517与系统存储器502接口连接。
系统存储器502可以是(例如,字节可寻址)多级系统存储器。在此,计算系统的性能往往取决于其系统存储器的性能。如本领域技术人员所理解的,程序代码在系统存储器外“执行”。如果数据或程序代码的一部分目前不在系统存储器中,而是通过执行代码而被需要,则从存储装置520(例如,非易失性硬盘驱动(HDD)或半导体存储器件(SSD))调取所需的数据或代码。信息从存储装置到系统存储器的转移可以与系统低效率相对应,因为系统内的流量拥塞可能增大和/或系统或系统内的线程可能空闲等待信息被加载到系统存储器中。
这样,计算机系统设计者对新的、较高密度的系统存储器技术感兴趣,所述系统存储器技术例如所三维系统存储器器件技术,其可以包括具有根据上面的教导的结构和/或根据上面的教导而制造的三维存储器器件。利用三维系统存储器技术,与具有二维系统存储器技术(例如SRAM或DRAM)的传统计算机系统相比,系统存储器的大小可以显著增大。这样,程序代码或数据的所需部分不存在于系统存储器中的可能性被降低,这又降低了忍受信息从存储装置到系统存储器的低效率转移的可能性。
这样,在各种实施例中,以上详细描述的三维存储器可以被包括作为例如多维系统存储器的较低层级。在此,可以在(多个)较高层级处使用较低密度但较快的系统存储器技术(例如DRAM),而可以在较低层级处使用更高密度但较慢的系统存储器技术(例如,三维NAND FLASH或其它三维技术)。
在系统存储器502的任何层级由非易失性存储器(例如NAND FLASH)组成的程度上,非传统计算系统范例可能受到欢迎。例如,可以省去存储装置520,或者软件应用(例如数据库应用)可能耗尽了系统存储器,并“提交”到系统存储器502而不是存储装置520。
返回参考计算系统500,注意,计算机的存储设备520也可以由三维存储器技术(例如以上详述的三维存储器器件)构成。功率管理控制单元512通常控制系统500的功率消耗。
触摸屏显示器503、通信接口504-507、GPS接口508、传感器509、相机510、以及扬声器/麦克风编解码器513、514中的每一个都可以被视为与整体计算系统(在适当时其还包括集成外围设备(例如,相机510))相关的各种形式的I/O(输入和/或输出)。取决于实施方式,这些I/O部件中的各种I/O部件可以被集成在应用处理器/多核处理器550上,或者可以位于管芯之外或者应用处理器/多核处理器550的封装的外部。
在前面的说明书中,已经参考本发明的具体示例性实施例描述了本发明。然而,将显而易见的是,可以对其进行各种修改和改变,而不脱离如所附权利要求书中所阐述的本发明的较宽泛的精神和范围。说明书和附图因此被认为具有说明性意义而非限制性意义。
Claims (20)
1.一种存储装置,包括:
半导体芯片,所述半导体芯片包括:
i)衬底;
ii)存储单元的阵列,所述存储单元的阵列包括所述衬底上方的堆叠存储单元,所述堆叠存储单元具有被定义为从相应的最底部存储单元到最顶部存储单元的距离的第一垂直长度;以及
iii)处于所述存储单元的阵列外部的没有堆叠存储单元的周边区域,所述周边区域包括具有大于所述第一垂直长度的第二垂直长度的至少一个导电列,所述周边区域包括制造在第二电介质中的开口内的第一电介质,其中,形成在所述开口内的所述第一电介质具有大于所述第二垂直长度的第三垂直长度。
2.根据权利要求1所述的装置,其中,所述存储单元是FLASH存储单元。
3.根据权利要求2所述的装置,其中,所述FLASH存储单元是NAND FLASH存储单元。
4.根据权利要求1所述的装置,其中,所述至少一个导电列的底端接触包括多晶硅的导电结构。
5.根据权利要求1所述的装置,其中,所述至少一个导电列的顶端接触后端导电元件。
6.根据权利要求1所述的装置,其中,所述至少一个导电列包括金属。
7.根据权利要求1所述的装置,其中,形成在所述第二电介质中的所述第一电介质中存在气隙。
8.一种形成半导体芯片的方法,包括:
形成半导电材料和电绝缘材料的多个交替层;
在半导电材料和电绝缘材料的所述交替层的内部区域中形成堆叠存储单元;
在所述半导电材料和所述电绝缘材料的外部区域中,通过穿过所述交替层蚀刻出孔洞而去除所述半导电材料,使得所述孔洞至少从所述堆叠存储单元的底部存储单元延伸到所述堆叠存储单元的顶部存储单元,以及挖掘通过所述孔洞暴露的所述半导电材料;
在空的空间中形成更加电绝缘的材料;以及
穿过所述外部区域形成导电列,所述导电列至少从所述堆叠存储单元的底部存储单元延伸到所述堆叠存储单元的顶部存储单元。
9.根据权利要求8所述的方法,其中,所述存储单元是FLASH存储单元。
10.根据权利要求8所述的方法,其中,所述导电列是在所述挖掘之前形成的。
11.根据权利要求8所述的方法,其中,所述导电列是在所述挖掘之后形成的。
12.根据权利要求8所述的方法,其中,所述更加电绝缘的材料是利用共形填充工艺形成的。
13.根据权利要求12所述的方法,其中,所述共形填充工艺包括将液体电介质引入到所述空的空间中。
14.一种计算系统,包括:
多个处理内核;
系统存储器;
系统存储器控制器,所述系统存储器控制器耦合在所述系统存储器与所述多个处理内核之间;
网络接口;以及
存储设备,所述存储设备包括半导体芯片,所述半导体芯片包括以下i)、ii)和iii):
i)衬底;
ii)存储单元的阵列,所述存储单元的阵列包括所述衬底上方的堆叠存储单元,所述堆叠存储单元具有被定义为从相应的最底部存储单元到最顶部存储单元的距离的第一垂直长度;以及
iii)处于所述存储单元的阵列外部的没有堆叠存储单元的周边区域,所述周边区域包括具有大于所述第一垂直长度的第二垂直长度的至少一个导电列,所述周边区域包括制造在第二电介质中的开口内的第一电介质,其中,形成在所述开口内的所述第一电介质具有大于所述第二垂直长度的第三垂直长度。
15.根据权利要求14所述的计算系统,其中,所述存储单元是FLASH存储单元。
16.根据权利要求15所述的计算系统,其中,所述FLASH存储单元是NAND FLASH存储单元。
17.根据权利要求14所述的计算系统,其中,所述至少一个导电列的底端接触包括多晶硅的导电结构。
18.根据权利要求14所述的计算系统,其中,所述至少一个导电列的顶端接触后端导电元件。
19.根据权利要求14所述的计算系统,其中,所述至少一个导电列包括金属。
20.根据权利要求14所述的计算系统,其中,形成在所述第二电介质中的所述第一电介质中存在气隙。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/853,783 | 2015-09-14 | ||
US14/853,783 US10096612B2 (en) | 2015-09-14 | 2015-09-14 | Three dimensional memory device having isolated periphery contacts through an active layer exhume process |
PCT/US2016/044074 WO2017048367A1 (en) | 2015-09-14 | 2016-07-26 | Three dimensional memory device having isolated periphery contacts through an active layer exhume process |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107980173A CN107980173A (zh) | 2018-05-01 |
CN107980173B true CN107980173B (zh) | 2023-01-10 |
Family
ID=58237173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201680047973.8A Active CN107980173B (zh) | 2015-09-14 | 2016-07-26 | 通过有源层挖掘工艺而具有隔离的周边接触部的三维存储器器件 |
Country Status (4)
Country | Link |
---|---|
US (2) | US10096612B2 (zh) |
CN (1) | CN107980173B (zh) |
TW (1) | TWI713151B (zh) |
WO (1) | WO2017048367A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI646667B (zh) * | 2017-07-28 | 2019-01-01 | 旺宏電子股份有限公司 | 三維堆疊半導體結構之製造方法及其製得之結構 |
JP2019160922A (ja) | 2018-03-09 | 2019-09-19 | 東芝メモリ株式会社 | 半導体装置 |
CN110114879B (zh) * | 2019-03-29 | 2021-01-26 | 长江存储科技有限责任公司 | 具有氮氧化硅栅极到栅极电介质层的存储堆叠体及其形成方法 |
WO2020198944A1 (en) | 2019-03-29 | 2020-10-08 | Yangtze Memory Technologies Co., Ltd. | Memory stacks having silicon nitride gate-to-gate dielectric layers and methods for forming the same |
CN110476209B (zh) | 2019-06-28 | 2020-11-17 | 长江存储科技有限责任公司 | 三维存储器件中的存储器内计算 |
WO2020258209A1 (en) * | 2019-06-28 | 2020-12-30 | Yangtze Memory Technologies Co., Ltd. | Computation-in-memory in three-dimensional memory device |
CN111033739B (zh) * | 2019-11-05 | 2022-06-28 | 长江存储科技有限责任公司 | 键合的三维存储器件及其形成方法 |
CN110998844A (zh) * | 2019-11-05 | 2020-04-10 | 长江存储科技有限责任公司 | 键合的三维存储器件及其形成方法 |
US11437435B2 (en) * | 2020-08-03 | 2022-09-06 | Micron Technology, Inc. | On-pitch vias for semiconductor devices and associated devices and systems |
US11830816B2 (en) * | 2020-08-14 | 2023-11-28 | Micron Technology, Inc. | Reduced resistivity for access lines in a memory array |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7335906B2 (en) * | 2003-04-03 | 2008-02-26 | Kabushiki Kaisha Toshiba | Phase change memory device |
US20070057289A1 (en) * | 2004-01-10 | 2007-03-15 | Davies Robert B | Power semiconductor device and method therefor |
US8541305B2 (en) * | 2010-05-24 | 2013-09-24 | Institute of Microelectronics, Chinese Academy of Sciences | 3D integrated circuit and method of manufacturing the same |
JP2012009701A (ja) | 2010-06-25 | 2012-01-12 | Toshiba Corp | 不揮発性半導体記憶装置 |
US10128261B2 (en) | 2010-06-30 | 2018-11-13 | Sandisk Technologies Llc | Cobalt-containing conductive layers for control gate electrodes in a memory structure |
US20120193785A1 (en) * | 2011-02-01 | 2012-08-02 | Megica Corporation | Multichip Packages |
US20120208347A1 (en) * | 2011-02-11 | 2012-08-16 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices and methods of fabricating the same |
JP2013211292A (ja) * | 2012-03-30 | 2013-10-10 | Elpida Memory Inc | 半導体装置 |
KR20140025049A (ko) | 2012-08-21 | 2014-03-04 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
KR101985936B1 (ko) | 2012-08-29 | 2019-06-05 | 에스케이하이닉스 주식회사 | 불휘발성 메모리 소자와 그 제조방법 |
US9853053B2 (en) * | 2012-09-10 | 2017-12-26 | 3B Technologies, Inc. | Three dimension integrated circuits employing thin film transistors |
KR101986245B1 (ko) * | 2013-01-17 | 2019-09-30 | 삼성전자주식회사 | 수직형 반도체 소자의 제조 방법 |
US9691981B2 (en) * | 2013-05-22 | 2017-06-27 | Micron Technology, Inc. | Memory cell structures |
US8987089B1 (en) | 2013-09-17 | 2015-03-24 | Sandisk Technologies Inc. | Methods of fabricating a three-dimensional non-volatile memory device |
KR102142366B1 (ko) * | 2013-11-14 | 2020-08-07 | 삼성전자 주식회사 | 반도체 집적 회로 소자 및 그 제조 방법, 반도체 패키지 |
KR20150078008A (ko) * | 2013-12-30 | 2015-07-08 | 에스케이하이닉스 주식회사 | 반도체 장치, 이의 제조 방법 및 이의 테스트 방법 |
KR20160007972A (ko) * | 2014-07-10 | 2016-01-21 | 삼성전자주식회사 | 불 휘발성 메모리 장치 및 메모리 컨트롤러, 그리고 그것의 동작 방법 |
US9524901B2 (en) * | 2014-09-30 | 2016-12-20 | Sandisk Technologies Llc | Multiheight electrically conductive via contacts for a multilevel interconnect structure |
-
2015
- 2015-09-14 US US14/853,783 patent/US10096612B2/en active Active
-
2016
- 2016-07-20 TW TW105122883A patent/TWI713151B/zh active
- 2016-07-26 WO PCT/US2016/044074 patent/WO2017048367A1/en active Application Filing
- 2016-07-26 CN CN201680047973.8A patent/CN107980173B/zh active Active
-
2018
- 2018-10-05 US US16/153,422 patent/US20190051662A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20170077117A1 (en) | 2017-03-16 |
US10096612B2 (en) | 2018-10-09 |
TWI713151B (zh) | 2020-12-11 |
TW201719816A (zh) | 2017-06-01 |
CN107980173A (zh) | 2018-05-01 |
US20190051662A1 (en) | 2019-02-14 |
WO2017048367A1 (en) | 2017-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107980173B (zh) | 通过有源层挖掘工艺而具有隔离的周边接触部的三维存储器器件 | |
US10593624B2 (en) | Three dimensional storage cell array with highly dense and scalable word line design approach | |
US10868038B2 (en) | Memory devices | |
KR102649162B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US10049743B2 (en) | Semiconductor device and method of manufacturing the same | |
US8268687B2 (en) | Three-dimensional semiconductor memory device and method of fabricating the same | |
KR102282139B1 (ko) | 반도체 장치 | |
CN108369947B (zh) | 在存储单元堆叠体中具有变化的存储单元设计的竖直存储器 | |
US20150064902A1 (en) | Methods of Fabricating Semiconductor Devices | |
KR20180106727A (ko) | 반도체 장치 및 그 제조 방법 | |
US9502432B1 (en) | Semiconductor device comprising a slit insulating layer configured to pass through a stacked structure | |
KR20150139357A (ko) | 반도체 장치 및 그 제조 방법 | |
KR20170099209A (ko) | 반도체 장치 및 그 제조 방법 | |
KR20150035224A (ko) | 반도체 장치 및 그 제조 방법 | |
KR20160045457A (ko) | 반도체 장치 및 그 제조 방법 | |
US9257487B2 (en) | Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same | |
US20240172439A1 (en) | Semiconductor structures and fabrication methods thereof, three-dimensional memories, and memory systems | |
US20230136139A1 (en) | Flash memory chip with self aligned isolation fill between pillars | |
CN118215299A (zh) | 半导体结构、三维存储器及其制备方法、存储系统 | |
CN114068566A (zh) | 用于防止块提升的nand闪存块架构增强 | |
CN118215298A (zh) | 半导体结构、三维存储器及其制备方法、存储系统 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |