CN107978581A - 多芯片封装件 - Google Patents

多芯片封装件 Download PDF

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Publication number
CN107978581A
CN107978581A CN201710945679.5A CN201710945679A CN107978581A CN 107978581 A CN107978581 A CN 107978581A CN 201710945679 A CN201710945679 A CN 201710945679A CN 107978581 A CN107978581 A CN 107978581A
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China
Prior art keywords
semiconductor chip
group
chip
bond pad
conducting wiring
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CN201710945679.5A
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CN107978581B (zh
Inventor
韩元吉
金秉柱
李龙济
李在兴
河承源
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供一种多芯片封装件，所述多芯片封装件包括：封装基底，包括第一基底焊盘；第一组半导体芯片，堆叠在封装基底上，第一组半导体芯片中的每个包括结合焊盘；第一螺柱凸部，布置在第一组半导体芯片的除了第一组中的最下侧半导体芯片之外的结合焊盘上；第一导电布线，从第一组中的最下侧半导体芯片的结合焊盘向下地延伸，并且连接到第一基底焊盘；第二导电布线，从第一组中的最下侧半导体芯片的结合焊盘向上地延伸，并且顺序地连接到第一螺柱凸部。

Description

多芯片封装件
于2016年10月24日在韩国知识产权局提交的名称为“多芯片封装件及其制造方法”的第10-2016-0138090号韩国专利申请通过引用全部包含于此。
技术领域
示例实施例涉及多芯片封装件及其制造方法。更具体地，示例实施例涉及包括通过导电布线彼此连接的多个半导体芯片的多芯片封装件以及制造该多芯片封装件的方法。
背景技术
多芯片封装件可以包括封装基底、多个半导体芯片和导电布线。半导体芯片可以堆叠在封装基底上。导电布线可以在封装基底与半导体芯片之间以及在半导体芯片之间电连接。
发明内容
根据示例实施例，可以提供一种多芯片封装件。多芯片封装件可以包括封装基底、第一组半导体芯片、第一螺柱凸部、第一导电布线和第二导电布线。封装基底可以包括第一基底焊盘。第一组半导体芯片可以堆叠在封装基底上。第一组半导体芯片中的每个可以包括结合焊盘。第一螺柱凸部可以布置在第一组半导体芯片的除了最下侧半导体芯片之外的结合焊盘上。第一导电布线可以从最下侧半导体芯片的结合焊盘向下地延伸。第一导电布线可以连接到第一基底焊盘。第二导电布线可以从最下侧半导体芯片的结合焊盘向上地延伸。第二导电布线可以顺序地连接到第一螺柱凸部。
根据示例实施例，可以提供一种多芯片封装件。多芯片封装件可以包括封装基底、第一半导体芯片至第四半导体芯片、螺柱凸部、第一导电布线和第二导电布线。封装基底可以包括第一基底焊盘。第一半导体芯片至第四半导体芯片可以以阶梯状形状堆叠在封装基底上。第一半导体芯片至第四半导体芯片中的每个可以包括结合焊盘。第一半导体芯片至第四半导体芯片可以具有基本相同的尺寸。螺柱凸部可以布置在第二半导体芯片至第四半导体芯片的结合焊盘上。第一导电布线可以包括附着到第一半导体芯片的结合焊盘的第一球。第一导电布线可以从第一球向下地延伸。第一导电布线可以连接到基底焊盘。第二导电布线可以包括附着到第一球的第二球。第二导电布线可以从第二球向上地延伸。第二导电布线可以顺序地连接到螺柱凸部。
根据示例实施例，可以提供一种多芯片封装件。所述多芯片封装件可以包括：封装基底，包括第一基底焊盘；第一组半导体芯片，堆叠在封装基底上，第一组中的半导体芯片中的每个半导体芯片包括至少一个结合焊盘；第一螺柱凸部，位于第一组半导体芯片的除了第一组中的最下侧半导体芯片之外的每个结合焊盘上；第一导电布线，从第一组中的最下侧半导体芯片中的至少一个结合焊盘延伸，以接触第一基底焊盘；第二导电布线，从第一组中的最下侧半导体芯片中的至少一个结合焊盘连续地延伸，以接触位于第一组中的最下侧半导体芯片上的半导体芯片中的每个上的至少一个第一螺柱凸部。
根据示例实施例，可以提供一种制造多芯片封装件的方法。在制造多芯片封装件的方法中，可以在包括第一基底焊盘的封装基底上堆叠第一组半导体芯片。可以在第一组半导体芯片的除了最下侧半导体芯片之外的结合焊盘上形成第一螺柱凸部。可以从最下侧半导体芯片的结合焊盘向下地延伸第一导电布线。第一导电布线可以连接到第一基底焊盘。可以从最下侧半导体芯片的结合焊盘向上地延伸第二导电布线。第二导电布线可以顺序地连接到第一螺柱凸部。
附图说明
通过参照附图详细地描述示例性实施例，对于本领域普通技术人员而言，特征将变得明显，其中：
图1示出根据示例实施例的多芯片封装件的剖视图；
图2示出堆叠在图1中的多芯片封装件的封装基底上的半导体芯片的透视图；
图3至图12示出在制造图1中的多芯片封装件的方法中的阶段的剖视图；
图13示出根据示例实施例的多芯片封装件的剖视图；
图14至图23示出在制造图13中的多芯片封装件的方法中的阶段的剖视图；
图24示出根据示例实施例的多芯片封装件的剖视图；
图25示出根据示例实施例的多芯片封装件的剖视图；
图26示出根据示例实施例的多芯片封装件的剖视图。
具体实施方式
在下文中，将参照附图详细说明示例实施例。
图1是示出根据示例实施例的多芯片封装件的剖视图，图2是示出堆叠在图1中的多芯片封装件的封装基底上的半导体芯片的透视图。
参照图1和图2，本示例实施例的多芯片封装件可以包括封装基底300、第一半导体芯片至第四半导体芯片110、120、130和140、螺柱凸部(stud bump)500、第一导电布线410、第二导电布线420、成型构件600和外部端子700。
封装基底300可以具有例如矩形形状。封装基底300可以包括绝缘基底和形成在绝缘基底中的导电图案。导电图案可以包括通过绝缘基底的上表面暴露的上端以及通过绝缘基底的下表面暴露的下端。基底焊盘302可以形成在导电图案的上端上，例如，基底焊盘302可以形成在绝缘基底的上表面上。基底焊盘302可以位于封装基底300的上表面的例如右边缘部的边缘处。
第一半导体芯片至第四半导体芯片110、120、130和140可以堆叠在封装基底300的上表面上(例如，直接堆叠在封装基底300的上表面上)以暴露基底焊盘302。第一半导体芯片至第四半导体芯片110、120、130和140可以具有基本相同的尺寸。可选择地，多芯片封装件可以包括例如直接彼此堆叠的两个、三个或至少五个半导体芯片。
第一半导体芯片110可以包括第一结合焊盘112。第一结合焊盘112可以位于第一半导体芯片110的上表面的例如右边缘部的边缘处。第二半导体芯片120可以包括第二结合焊盘122。第二结合焊盘122可以位于第二半导体芯片120的上表面的例如右边缘部的边缘处。第三半导体芯片130可以包括第三结合焊盘132。第三结合焊盘132可以位于第三半导体芯片130的上表面的例如右边缘部的边缘处。第四半导体芯片140可以包括第四结合焊盘142。第四结合焊盘142可以位于第四半导体芯片140的上表面的例如右边缘部的边缘处。例如，第一结合焊盘112至第四结合焊盘142中的每个可以位于对应的第一半导体芯片110至第四半导体芯片140的如基底焊盘302相对于封装基底300的相同的一侧和边缘处，例如，位于右边缘部处。例如，如图2中所示，第一半导体芯片110至第四半导体芯片140中的每个可以包括沿其边缘对齐的多个结合焊盘。
第一半导体芯片110可以堆叠在封装基底300的上表面上以暴露基底焊盘302。第二半导体芯片120可以堆叠在第一半导体芯片110的上表面上以暴露第一结合焊盘112。第三半导体芯片可以堆叠在第二半导体芯片120的上表面上以暴露第二结合焊盘122。第四半导体芯片140可以堆叠在第三半导体芯片130的上表面上以暴露第三结合焊盘132。即，第一半导体芯片至第四半导体芯片110、120、130和140可以沿着左方向以阶梯状的形状顺序地堆叠在封装基底300上。换句话说，第一半导体芯片至第四半导体芯片110、120、130和140中的每个可以在与阶梯构造中的结合焊盘相反的方向上偏移，例如，从位于右边缘部处的各个结合焊盘向左偏移。
因为第一半导体芯片至第四半导体芯片110、120、130和140可以具有基本相同的尺寸，所以如图1中所示，阶梯构造可以引起第一半导体芯片至第四半导体芯片110、120、130和140中的每个的与结合焊盘的一侧相反的一侧突出，例如，悬于下面的半导体芯片之上、超过下面的半导体芯片。即，因为第一半导体芯片至第四半导体芯片110、120、130和140可以具有基本相同的尺寸，所以第二半导体芯片120的左侧表面可以从第一半导体芯片110的左侧表面突出，第三半导体芯片130的左侧表面可以从第二半导体芯片120的左侧表面突出，第四半导体芯片140的左侧表面可以从第三半导体芯片130的左侧表面突出。
螺柱凸部500可以形成在第二结合焊盘122、第三结合焊盘132和第四结合焊盘142上。与此相反，螺柱凸部500可以不形成在第一结合焊盘112上。
第一导电布线410可以从第一结合焊盘112向下地延伸。第一导电布线410可以连接到基底焊盘302。即，第一导电布线410可以包括连接到第一结合焊盘112的上端以及从上端延伸并连接到基底焊盘302的下端。
第一导电布线410可以包括附着到第一结合焊盘112的第一球412。第一球412可以与第一导电布线410的上端一体地形成。因此，第一导电布线410可以从第一球412延伸并连接到基底焊盘302。
第二导电布线420可以从第一结合焊盘112向上地延伸。第二导电布线420可以顺序地连接到螺柱凸部500。第二导电布线420可以包括附着到第一球412的第二球422。第二球422可以与第二导电布线420的下端一体地形成。
第二导电布线420可以从第二球422向上地延伸。第二导电布线420可以连接到第二半导体芯片120的第二结合焊盘122上的螺柱凸部500。第二导电布线420可以从第二结合焊盘122上的螺柱凸部500连续地向上延伸。第二导电布线420可以连接到第三半导体芯片130的第三结合焊盘132上的螺柱凸部500。第二导电布线420可以从第三结合焊盘132上的螺柱凸部500连续地向上延伸。第二导电布线420可以连接到第四半导体芯片140的第四结合焊盘142上的螺柱凸部500。即，第二导电布线420可以与从第二球422例如连续地向上地延伸并顺序地连接到例如第二半导体芯片120至第四半导体芯片140中的每个上的螺柱凸部500的单条布线对应。
成型构件600可以形成在封装基底300的上表面上以覆盖第一半导体芯片至第四半导体芯片110、120、130和140、第一导电布线410以及第二导电布线420。成型构件600可以包括例如环氧树脂模塑料(EMC)。
外部端子700可以安装在导电图案的通过封装基底300的下表面暴露的下端上。外部端子700可以包括焊球。
图3至图12是示出在制造图1中的多芯片封装件的方法中的阶段的剖视图。
参照图3，可以在封装基底300的上表面上堆叠第一半导体芯片110以暴露基底焊盘302。可以在第一半导体芯片110的上表面上堆叠第二半导体芯片120以暴露第一结合焊盘112。可以在第二半导体芯片120的上表面上堆叠第三半导体芯片130以暴露第二结合焊盘122。可以在第三半导体芯片130的上表面上堆叠第四半导体芯片140以暴露第三结合焊盘132。
参照图4，可以在第二结合焊盘122、第三结合焊盘132和第四结合焊盘142上形成螺柱凸部500。可以通过将火花(spark)施加到从毛细管抽出的布线的下端来形成螺柱凸部500。与此相反，可以不在第一结合焊盘112上形成螺柱凸部500。
参照图5，可以在第一结合焊盘112之上布置毛细管C。可以在从毛细管C抽出的布线W的下端处形成第一球412。第一球412可以附着到第一结合焊盘112。
参照图6，可以沿水平方向将毛细管C移动到基底焊盘302之上的区域。因此，从第一球412延伸的布线W可以位于基底焊盘302之上。可以朝着基底焊盘302向下地移动毛细管C以将布线W缝合到基底焊盘302。
参照图7，可以切割从基底焊盘302延伸到毛细管C的布线W以形成第一导电布线410。第一导电布线410可以从附着到第一结合焊盘112的第一球412向下地延伸。第一导电布线410可以连接到基底焊盘302。
参照图8，可以在第一结合焊盘112之上布置毛细管C。可以在从毛细管C抽出的布线W的下端处形成第二球422。第二球422可以附着到第一球412。
参照图9，可以沿竖直方向向上地移动毛细管C。然后可以沿水平方向朝向第二结合焊盘122移动毛细管C。因此，从第二球422延伸的布线W可以连接到第二结合焊盘122上的螺柱凸部500。因为在向上地移动毛细管C之后可以沿水平方向(例如，仅沿水平方向)移动毛细管C，所以可以在由布线W形成的环与第二半导体芯片120的侧表面之间形成足够的间隙。例如，可以沿两个不同的方向(例如，竖直地和水平地)以两个阶段移动毛细管C，以限定与第二半导体芯片120的面向布线W的横侧间隔开的倾斜的L形布线，例如，具有相对于彼此以非零度角的两个基本上线型的部分的布线。因此，布线W可以不与第二半导体芯片120的侧表面接触。
参照图10，可以沿竖直方向向上地移动毛细管C。然后可以沿水平方向朝向第三结合焊盘132移动毛细管C。因此，从第二结合焊盘122上的螺柱凸部500延伸的布线W可以连接到第三结合焊盘132上的螺柱凸部500。如上所述，因为在向上地移动毛细管C之后可以沿水平方向移动毛细管C，所以可以在由布线W形成的环与第三半导体芯片130的侧表面之间形成足够的间隙。因此，布线W可以不与第三半导体芯片130的侧表面接触。
参照图11，可以沿竖直方向向上地移动毛细管C。然后可以沿水平方向朝向第四结合焊盘142移动毛细管C。因此，从第三结合焊盘132上的螺柱凸部500延伸的布线W可以连接到第四结合焊盘142上的螺柱凸部500。如上所述，因为在向上地移动毛细管C之后可以沿水平方向移动毛细管C，所以可以在由布线W形成的环与第四半导体芯片140的侧表面之间形成足够的间隙。因此，布线W可以不与第四半导体芯片140的侧表面接触。
参照图12，可以切割从第四结合焊盘142上的螺柱凸部500延伸到毛线管C的布线W以形成第二导电布线420。第二导电布线420可以从附着到第一球412的第二球422向上地延伸。第二导电布线420可以与第二至第四结合焊盘122、132和142上的螺柱凸部500顺序地连接。
可以在封装基底300的上表面上形成成型构件600以覆盖第一半导体芯片至第四半导体芯片110、120、130和140、第一导电布线410以及第二导电布线420。可以在导电图案的通过封装基底300的下表面暴露的下端上安装外部端子700以完成图1中的多芯片封装件。
图13是示出根据示例实施例的多芯片封装件的剖视图。
参照图13，本示例实施例的多芯片封装件可以包括封装基底300、第一组半导体芯片100、第一螺柱凸部500、第一导电布线410、第二导电布线420、第二组半导体芯片800、第二螺柱凸部510、第三导电布线430、第四导电布线440、成型构件610和外部端子710。
封装基底300可以包括第一基底焊盘302和第二基底焊盘304。第一基底焊盘302可以位于例如封装基底300的上表面的右边缘部处。第二基底焊盘304可以位于封装基底300的相对于第一基底焊盘302的相对侧处，例如，第二基底焊盘304可以位于封装基底300的上表面的左边缘部处。
图13中的第一组半导体芯片100、第一螺柱凸部500、第一导电布线410和第二导电布线420可以分别与图1中的第一半导体芯片至第四半导体芯片110、120、130和140、螺柱凸部500、第一导电布线410以及第二导电布线420基本相同。因此，为了简洁，这里可以省略关于图13中的第一组半导体芯片100、第一螺柱凸部500、第一导电布线410和第二导电布线420的任何进一步说明。第一导电布线410可以连接到第一基底焊盘302。
第二组半导体芯片800可以包括第一半导体芯片至第四半导体芯片810、820、830和840。第二组中的第一半导体芯片至第四半导体芯片810、820、830和840可以以阶梯状的形状堆叠在第一组中的第四半导体芯片140的上表面上。第二组中的第一半导体芯片至第四半导体芯片810、820、830和840可以具有基本相同的尺寸。此外，第二组半导体芯片800的尺寸可以与第一组半导体芯片100的尺寸基本相同。可选择地，第二组半导体芯片800可以包括两个、三个或至少五个半导体芯片。
第一半导体芯片至第四半导体芯片810、820、830和840可以包括相对于第一组半导体芯片100中的结合焊盘位于相反侧处的结合焊盘。详细地，第一半导体芯片810可以包括第一结合焊盘812。第一结合焊盘812可以位于第一半导体芯片810的上表面的左边缘部处。第二半导体芯片820可以包括第二结合焊盘822。第二结合焊盘822可以位于第二半导体芯片820的上表面的左边缘部处。第三半导体芯片830可以包括第三结合焊盘832。第三结合焊盘832可以位于第三半导体芯片830的上表面的左边缘部处。第四半导体芯片840可以包括第四结合焊盘842。第四结合焊盘842可以位于第四半导体芯片840的上表面的左边缘部处。
第二半导体芯片820可以堆叠在第一半导体芯片810的上表面上以暴露第一结合焊盘812。第三半导体芯片830可以堆叠在第二半导体芯片820的上表面上以暴露第二结合焊盘822。第四半导体芯片840可以堆叠在第三半导体芯片830的上表面上以暴露第三结合焊盘832。即，第一半导体芯片至第四半导体芯片810、820、830和840可以沿右方向以阶梯状的形状顺序地堆叠。例如，如图13中所示，第一半导体芯片至第四半导体芯片810、820、830和840可以在相对于焊盘相对的方向上移动，以相对于第一组半导体芯片100关于使第一组半导体芯片100的第四半导体芯片140与第二组半导体芯片800的第一半导体芯片810分离的平面对称地布置。
第二螺柱凸部510可以形成在第二结合焊盘822、第三结合焊盘832和第四结合焊盘842上。与此相反，第二螺柱凸部510可以不形成在第一结合焊盘812上。
第三导电布线430可以从第一结合焊盘812向下地延伸。第三导电布线430可以连接到第二基底焊盘304。可选择地，第三导电布线430可以连接到封装基底300上的控制芯片。
第三导线布线430可以包括附着到第一结合焊盘812的第三球432。第三球432可以与第三导线布线430的上端一体地形成。因此，第三导电布线430可以从第三球432延伸，并且连接到第二基底焊盘304。
第四导电布线440可以从第一结合焊盘812向上地延伸。第四导电布线440可以顺序地连接到第二螺柱凸部510。第四导电布线440可以包括附着到第三球432的第四球442。第四球442可以与第四导电布线440的下端一体地形成。
第四导电布线440可以从第四球442向上地延伸。第四导电布线440可以连接到第二半导体芯片820的第二结合焊盘822上的第二螺柱凸部510。第四导电布线440可以从第二结合焊盘822上的第二螺柱凸部510连续地向上延伸。第四导电布线440可以连接到第三半导体芯片830的第三结合焊盘832上的第二螺柱凸部510。第四导电布线440可以从第三结合焊盘832上的第二螺柱凸部510连续地向上延伸。第四导电布线440可以连接到第四半导体芯片840的第四结合焊盘842上的第二螺柱凸部510。即，第四导电布线440可以与从第四球442向上地延伸并顺序地连接到第二螺柱凸部510的单条布线对应。
成型构件610可以形成在封装基底300的上表面上以覆盖第一组半导体芯片100、第二组半导体芯片800以及第一至第四导电布线410、420、430和440。
外部端子710可以安装在导电图案的通过封装基底300的下表面暴露的下端上。
图14至图23是示出在制造图13中的多芯片封装件的方法中的阶段的剖视图。
可以执行与参照图3至图12示出的工艺基本相同的工艺以在封装基底300上以阶梯状的形状堆叠第一组半导体芯片100，并且使用第一导电布线410和第二导电布线420将第一组半导体芯片100与封装基底300电连接。
参照图14，可以在第一组中的第四半导体芯片140的上表面上堆叠第一半导体芯片810。可以在第一半导体芯片810的上表面上堆叠第二半导体芯片820以暴露第一结合焊盘812。可以在第二半导体芯片820的上表面上堆叠第三半导体芯片830以暴露第二结合焊盘822。可以在第三半导体芯片830的上表面上堆叠第四半导体芯片840以暴露第三结合焊盘832。
参照图15，可以在第二结合焊盘822、第三结合焊盘832和第四结合焊盘842上形成第二螺柱凸部510。与此相反，可以不在第一结合焊盘812上形成第二螺柱凸部510。
参照图16，可以在第一结合焊盘812之上布置毛细管C。可以在从毛细管C抽出的布线W的下端处形成第三球432。第三球432可以附着到第一结合焊盘812。
参照图17，可以沿水平方向将毛细管C移动到第二基底焊盘304之上的区域。因此，从第三球432延伸的布线W可以位于第二基底焊盘304之上。可以将毛细管C朝向第二基底焊盘304向下地移动以将布线W缝合到第二基底焊盘304。
参照图18，可以切割从第二基底焊盘304延伸到毛细管C的布线W以形成第三导电布线430。第三导电布线430可以从附着到第一结合焊盘812的第三球432向下地延伸。第三导电布线430可以连接到第二基底焊盘304。
参照图19，可以在第一结合焊盘812之上布置毛细管C。可以在从毛细管C抽出的布线W的下端处形成第四球442。第四球442可以附着到第三球432。
参照图20，可以沿竖直方向向上地移动毛细管C。然后可以沿水平方向朝向第二结合焊盘822移动毛细管C。因此，从第四球442延伸的布线W可以连接到第二结合焊盘822上的第二螺柱凸部510。因为在向上地移动毛细管C之后可以沿水平方向移动毛细管C，所以可以在由布线W形成的环与第二半导体芯片820的侧表面之间形成足够的间隙。因此，布线W可以不与第二半导体芯片820的侧表面接触。
参照图21，可以沿竖直方向向上地移动毛细管C。然后可以沿水平方向朝向第三结合焊盘832移动毛细管C。因此，从第二结合焊盘822上的第二螺柱凸部510延伸的布线W可以连接到第三结合焊盘832上的第二螺柱凸部510。如上所述，因为在向上地移动毛细管C之后可以沿水平方向移动毛细管C，所以可以在由布线W形成的环与第三半导体芯片830的侧表面之间形成足够的间隙。因此，布线W可以不与第三半导体芯片830的侧表面接触。
参照图22，可以沿竖直方向向上地移动毛细管C。然后可以沿水平方向朝向第四结合焊盘842移动毛细管C。因此，从第三结合焊盘832上的第二螺柱凸部510延伸的布线W可以连接到第四结合焊盘842上的第二螺柱凸部510。如上所述，因为在向上地移动毛细管C之后可以沿水平方向移动毛细管C，所以可以在由布线W形成的环与第四半导体芯片840的侧表面之间形成足够的间隙。因此，布线W可以不与第四半导体芯片840的侧表面接触。
参照图23，可以切割从第四结合焊盘842上的第二螺柱凸部510延伸到毛细管C的布线W，以形成第四导电布线440。第四导电布线440可以从附着到第三球432的第四球442向上地延伸。第四导电布线440可以与第二至第四结合焊盘822、832和842上的第二螺柱凸部510顺序地连接。
可以在封装基底300的上表面上形成成型构件610，以覆盖第一组半导体芯片100、第二组半导体芯片800以及第一至第四导电布线410、420、430和440。可以在导电图案的通过封装基底300的下表面暴露的下端上安装外部端子710，以完成图13中的多芯片封装件。
图24是示出根据示例实施例的多芯片封装件的剖视图。
参照图24，本示例实施例的多芯片封装件可以包括封装基底300、第一组半导体芯片100、第二组半导体芯片850、第三组半导体芯片900、第四组半导体芯片950、控制芯片750、成型构件620和外部端子720。
封装基底300可以包括第一基底焊盘302和第二基底焊盘304。控制芯片750可以位于封装基底300的上表面的中心部分处。第一基底焊盘302可以位于封装基底300的例如控制芯片750的左侧的上表面上。第二基底焊盘304可以位于封装基底300的例如控制芯片750的右侧的上表面上。控制芯片750可以与第一基底焊盘302和第二基底焊盘304电连接。
第一组半导体芯片100可以沿左方向以阶梯状的形状堆叠在封装基底300的上表面的左部分上。第二组半导体芯片850可以沿右方向以阶梯状的形状堆叠在封装基底300的上表面的右部分上。第三组半导体芯片900可以沿左方向以阶梯状的形状堆叠在第一组半导体芯片100上。第四组半导体芯片950可以沿右方向以阶梯状的形状堆叠在第二组半导体芯片850上。
第一至第四组半导体芯片100、850、900和950的布线结合结构可以与图13中的第一组半导体芯片100的布线结合结构基本相同。第一组半导体芯片100的第一导电布线410和第二组半导体芯片850的第五导电布线450可以具有与图13中的第一组半导体芯片100的第一导电布线410的功能和形状基本相同的功能和形状。第一组半导体芯片100的第二导电布线420和第二组半导体芯片850的第六导电布线455可以具有与图13中的第一组半导体芯片100的第二导电布线420的功能和形状基本相同的功能和形状。第三组半导体芯片900的第三导电布线460和第四组半导体芯片950的第七导电布线470可以具有与图13中的第二组半导体芯片800的第三导电布线430的功能和形状基本相同的功能和形状。第三组半导体芯片900的第四导电布线465和第四组半导体芯片950的第八导电布线475可以具有与图13中的第二组半导体芯片800的第四导电布线440的功能和形状基本相同的功能和形状。因此，为了简洁，这里可以省略关于第一至第四组半导体芯片100、850、900和950的布线结合结构的任何进一步说明。
第一组半导体芯片100可以与第一基底焊盘302电连接。第二组半导体芯片850可以与第二基底焊盘304电连接。第三组半导体芯片900和第四组半导体芯片950可以与控制芯片750电连接。可选择地，第三组半导体芯片900可以与第一基底焊盘302电连接。第四组半导体芯片950可以与第二基底焊盘304电连接。
本示例实施例的多芯片封装件可以通过对第一至第四组半导体芯片100、850、900和950执行参照图3至图12示出的上述工艺来制造。因此，为了简洁，这里可以省略关于本示例实施例的多芯片封装件的制造方法的任何进一步说明。
图25是示出根据示例实施例的多芯片封装件的剖视图。除了半导体芯片的尺寸之外，本示例实施例的多芯片封装件可以包括与图1中的多芯片封装件的元件基本相同的元件。因此，同样的附图标记可以表示同样的元件，并且为了简洁，这里可以省略关于同样元件的任何进一步说明。
参照图25，第一半导体芯片至第四半导体芯片110a、120a、130a和140a可以具有基本相同的宽度。可以沿着结合焊盘的布置方向测量宽度。与此相反，第一半导体芯片至第四半导体芯片110a、120a、130a和140a可以具有不同的长度。可以沿着与结合焊盘的布置方向基本上垂直的方向测量长度。
在示例实施例中，第一半导体芯片110a可以具有最长的长度。第四半导体芯片140a可以具有最短的长度。因此，第一半导体芯片至第四半导体芯片110a、120a、130a和140a的左侧表面可以位于竖直平面上，例如第一半导体芯片至第四半导体芯片110a、120a、130a和140a的左侧表面可以对齐。
图26是示出根据示例实施例的多芯片封装件的剖视图。除了半导体芯片的尺寸之外，本示例实施例的多芯片封装件可以包括与图1中的多芯片封装件的元件基本相同的元件。因此，同样的附图标记可以表示同样的元件，并且为了简洁，这里可以省略关于同样元件的任何进一步说明。
参照图26，第一半导体芯片至第四半导体芯片110b、120b、130b和140b可以具有不同的宽度和长度。在示例实施例中，第一半导体芯片110b可以具有最宽的宽度和最长的长度。第四半导体芯片140b可以具有最窄的宽度和最短的长度。因此，堆叠的第一半导体芯片至第四半导体芯片110b、120b、130b和140b可以具有锥体的阶梯状的形状。
通过总结和回顾，使用导电布线的结合时间会太长。此外，由于半导体芯片与对应的布线环之间的窄的间隙，会在由导电布线形成的环中产生故障。
与此相反，示例实施例可以提供一种多芯片封装件，该多芯片封装件不具有布线环的故障且缩短的布线结合时间。示例实施例还可以提供制造上述多芯片封装件的方法。
即，根据示例实施例，多芯片封装件中的第一导电布线可以从最下侧半导体芯片的结合焊盘向下地延伸。第一导电布线可以连接到封装基底的基底焊盘。因此，第一导电布线可以牢固地固定到基底焊盘。此外，第二导电布线可以从最下侧半导体芯片的结合焊盘向上地延伸。第二导电布线可以顺序地并连续地连接到多芯片封装件的位于第一半导体芯片上方的半导体芯片的螺柱凸部。因此，由第二导电布线形成的环可以与半导体芯片的侧表面间隔开足够的间隙，使得第二导电布线可以不与半导体芯片的侧表面接触。此外，由于布线结合工艺仅包括两次切割第一导电布线和第二导电布线，例如，由于第二布线连续延伸以在顶部半导体芯片处的单个切割步骤来接触多个半导体芯片，可以减少布线结合时间。
这里已经公开了示例实施例，尽管采用了特定术语，但是它们被使用并且仅在通用和描述性意义上被解释，而不是为了限制的目的。在一些情况下，如本领域的普通技术人员将清楚的，自提交本申请之时起，结合具体实施例描述的特征、特性和/或元件可以单独使用，或者可以与结合其他实施例描述的特征、特性和/或元件组合使用，除非另有具体说明。因此，本领域技术人员将理解的是，在不脱离如权利要求书所阐述的本发明的精神和范围的情况下，可以对形式和细节进行各种改变。

Claims (20)

1.一种多芯片封装件，所述多芯片封装件包括：
封装基底，包括第一基底焊盘；
第一组半导体芯片，堆叠在封装基底上，第一组中的半导体芯片中的每个半导体芯片包括至少一个结合焊盘；
第一螺柱凸部，布置在除了第一组中的最下侧半导体芯片之外的第一组半导体芯片的结合焊盘上；
第一导电布线，从第一组中的最下侧半导体芯片的至少一个结合焊盘向下地延伸，并且连接到第一基底焊盘；
第二导电布线，从第一组中的最下侧半导体芯片的至少一个结合焊盘向上地延伸，并且顺序地连接到第一螺柱凸部。
2.根据权利要求1所述的多芯片封装件，其中，第一组中的半导体芯片以阶梯状的形状堆叠，以暴露结合焊盘。
3.根据权利要求1所述的多芯片封装件，其中，第一组中的半导体芯片具有基本相同的尺寸。
4.根据权利要求1所述的多芯片封装件，其中，第一导电布线包括第一球，所述第一球附着到第一组半导体芯片中的最下侧半导体芯片的至少一个结合焊盘。
5.根据权利要求4所述的多芯片封装件，其中，第二导电布线包括附着到第一球的第二球。
6.根据权利要求5所述的多芯片封装件，其中，第二导电布线包括在第二球与第一螺柱凸部之间以及在多个第一螺柱凸部之间连续地连接的单条布线。
7.根据权利要求1所述的多芯片封装件，其中，封装基底还包括第二基底焊盘。
8.根据权利要求7所述的多芯片封装件，所述多芯片封装件还包括：
第二组半导体芯片，堆叠在第一组半导体芯片的最上侧半导体芯片上，第二组中的半导体芯片中的每个半导体芯片包括至少一个结合焊盘；
第二螺柱凸部，布置在除了第二组中的最下侧半导体芯片之外的第二组半导体芯片的结合焊盘上；
第三导电布线，从第二组中的最下侧半导体芯片的至少一个结合焊盘向下地延伸，并且连接到第二基底焊盘；
第四导电布线，从第二组中的最下侧半导体芯片的至少一个结合焊盘向上地延伸，并且顺序地连接到第二螺柱凸部。
9.根据权利要求8所述的多芯片封装件，其中，第二组中的半导体芯片沿着与第一组半导体芯片的堆叠方向相反的方向以阶梯状形状堆叠，以暴露第二组半导体芯片的结合焊盘。
10.根据权利要求8所述的多芯片封装件，其中，第二组中的半导体芯片具有基本相同的尺寸。
11.根据权利要求10所述的多芯片封装件，其中，第二组半导体芯片中的半导体芯片的数量与第一组半导体芯片中的半导体芯片的数量基本相同。
12.根据权利要求8所述的多芯片封装件，其中，第三导电布线包括第三球，所述第三球附着到第二组中的最下侧半导体芯片的至少一个结合焊盘。
13.根据权利要求12所述的多芯片封装件，其中，第四导电布线包括附着到第三球的第四球。
14.根据权利要求13所述的多芯片封装件，其中，第四导电布线包括在第四球与第二螺柱凸部之间以及在多个第二螺柱凸部之间连续地连接的单条布线。
15.一种多芯片封装件，所述多芯片封装件包括：
封装基底，包括基底焊盘；
第一半导体芯片至第四半导体芯片，以阶梯状形状堆叠在封装基底上，第一半导体芯片至第四半导体芯片中的每个包括至少一个结合焊盘，第一半导体芯片至第四半导体芯片具有基本相同的尺寸；
螺柱凸部，布置在第二半导体芯片至第四半导体芯片的结合焊盘上；
第一导电布线，包括附着到第一半导体芯片的至少一个结合焊盘的第一球，第一导电布线从第一球向下地延伸并连接到基底焊盘；
第二导电布线，包括附着到第一球的第二球，第二导电布线从第二球向上地延伸并顺序地连接到螺柱凸部。
16.根据权利要求15所述的多芯片封装件，其中，第二导电布线包括在第二球与螺柱凸部之间以及在多个螺柱凸部之间连续地连接的单条布线。
17.一种多芯片封装件，所述多芯片封装件包括：
封装基底，包括第一基底焊盘；
第一组半导体芯片，堆叠在封装基底上，第一组中的半导体芯片中的每个半导体芯片包括至少一个结合焊盘；
第一螺柱凸部，位于除了第一组中的最下侧半导体芯片之外的第一组半导体芯片的结合焊盘上；
第一导电布线，从第一组中的最下侧半导体芯片的至少一个结合焊盘延伸，以接触第一基底焊盘；
第二导电布线，从第一组中的最下侧半导体芯片的至少一个结合焊盘连续地延伸，以接触位于第一组中的最下侧半导体芯片上的每个半导体芯片上的至少一个螺柱凸部。
18.根据权利要求17所述的多芯片封装件，其中，第一组中的半导体芯片以阶梯状结构堆叠，第二导电布线沿所述最下侧半导体芯片上方的阶梯状结构的每个阶梯连续地并顺序地延伸。
19.根据权利要求17所述的多芯片封装件，其中，第一导电布线和第二导电布线在所述最下侧半导体芯片上彼此连接。
20.根据权利要求17所述的多芯片封装件，其中，第一导电布线和第二导电布线中的每个包括位于每两个半导体芯片之间的两个线型布线部分，所述两个线型布线部分以非零角度彼此连接。
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