CN107946276A - Conductive frame and power semiconductor cascaded structure - Google Patents
Conductive frame and power semiconductor cascaded structure Download PDFInfo
- Publication number
- CN107946276A CN107946276A CN201711421677.2A CN201711421677A CN107946276A CN 107946276 A CN107946276 A CN 107946276A CN 201711421677 A CN201711421677 A CN 201711421677A CN 107946276 A CN107946276 A CN 107946276A
- Authority
- CN
- China
- Prior art keywords
- conductive frame
- solidus
- chip
- area
- chip region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49537—Plurality of lead frames mounted in one device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
The present invention provides a kind of conductive frame and power semiconductor cascaded structure, the conductive frame includes spaced first conductive frame of mutually insulated, second conductive frame and the 3rd conductive frame, second conductive frame includes the second chip region, the second pin extended by second chip region and the first solidus area, the first solidus area is located at the side that second chip region deviates from the second pin, there is sunk structure between second chip region and the first solidus area, the sunk structure can accommodate solder unnecessary when second chip region and/or the first solidus area weld job.The present invention is used as solidus region by the use of the one end in welding chip region, save space, effectively increase the area of the solderable chip of the conductive frame, at the same time, design the sunk structure between welding chip region and solidus region, so that weld job and solidus operation are independent of each other, the reliability of Weldability and solidus ability ensure that.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of conductive frame and has the conductive pane
The power semiconductor cascaded structure of frame.
Background technology
Semiconductor devices has a wide range of applications in electronic field, and, it is necessary to by semiconductor in specific application process
It is encapsulated.Series Package can improve the opering characteristic of electric apparatus of semiconductor as reversely pressure-resistant, and form all kinds of power modules to coordinate
The requirement of circuit design.Solidus region is all located at conductive frame lower end and extension pin company in existing semiconductor Series Package structure
Place is met, and occupied area is larger, has extruded the area in welding chip region on conductive frame, further, since solidus region and weldering
Connect that chip area is adjacent, in welding chip, unnecessary scolding tin easily flows into solidus region and influences solidus operation, otherwise also
So, it is impossible to meet field of power electronics high power density there is an urgent need to.
The content of the invention
Based on this, the present invention provides a kind of conductive frame and power semiconductor cascaded structure.
A kind of conductive frame, for serial semiconductor chip, the conductive frame includes the first conductive frame, the second conduction
Frame and the 3rd conductive frame, first conductive frame, second conductive frame and the 3rd conductive frame are mutually exhausted
Edge is spaced, and first conductive frame includes the first chip region and the first pin extended by first chip region；
The second pin and the first solidus that second conductive frame includes the second chip region, extended by second chip region
Area, the first solidus area are located at the side that second chip region deviates from the second pin, second chip region and institute
Stating between the first solidus area has sunk structure, and the sunk structure can accommodate second chip region and/or described first
Unnecessary solder during solidus area weld job；3rd conductive frame includes the second solidus area and is extended by the second solidus area
The 3rd pin.
In one of the embodiments, the sunk structure is any one in v-depression, U-shaped groove, rectangular recess
Kind.
In one of the embodiments, the through hole for mechanical connection is further included, the through hole is located at the conductive frame
One end.
In one of the embodiments, the opposite side difference in the end of first conductive frame and the second conductive frame
Semicircular notch is opened up, the notch surrounds the through hole.
In one of the embodiments, the width in the second solidus area is more than the width of the 3rd pin.
A kind of power semiconductor cascaded structure, including the first semiconductor chip, the second semiconductor chip and such as above-mentioned reality
Apply any conductive frame of example, first semiconductor chip be attached at electrically first chip region and with it is described
First solidus area is electrically connected, and second semiconductor chip is attached at second chip region and consolidates with described second electrically
Line area is electrically connected.
In one of the embodiments, the first pole of first semiconductor chip is attached at first chip region, the
Two poles are electrically connected with the first solidus area on second conductive frame；Second semiconductor chip and first semiconductor
The identical pole of first pole polarity of chip is attached at second chip region, another pole and the on the 3rd conductive frame
Two solidus areas are electrically connected.
In one of the embodiments, the semiconductor chip is attached at the conductive frame by welding.
In one of the embodiments, first semiconductor chip is electrically connected by plain conductor and the first solidus area
Connect；And/or second semiconductor chip is electrically connected by plain conductor with the second solidus area.
In one of the embodiments, the plain conductor is copper wire or aluminum steel.
Above-mentioned conductive frame, the welding chip on the conductive frame is designed by the solidus region on one of conductive frame
Region effectively increases the area of the solderable chip of the conductive frame away from one end of extension pin, saving space, together
When, design the sunk structure between welding chip region and solidus region so that welding chip region and solidus region
Can independently working be independent of each other, ensure that the reliability of Weldability and solidus ability.
Above-mentioned power semiconductor cascaded structure, reduces the space of semiconductor Series Package structure, and solidus is moved towards to close
Reason does not conflict neatly, meets the requirement of field of power electronics high power density and high reliability.
Brief description of the drawings
Fig. 1 is conductive frame structure chart provided in an embodiment of the present invention；
Fig. 2 is power semiconductor tandem junction composition provided in an embodiment of the present invention；
Fig. 3 encapsulates schematic diagram for Diode series provided in an embodiment of the present invention.
Embodiment
Referring to Fig. 1, in one embodiment, there is provided a kind of conductive frame 300, for serial semiconductor chip, institute
Stating conductive frame 300 includes the first conductive frame 310, the second conductive frame 320 and the 3rd conductive frame 330, and described first leads
Electric frame 310, second conductive frame 320 and 330 mutually insulated of the 3rd conductive frame are spaced.
Further, first conductive frame 310 includes the first chip region 311 and is prolonged by first chip region 311
The first pin 312 stretched out, first chip region 311 are used to attach semiconductor chip, and first pin 312 is used to draw
Semiconductor chip is attached to the electrode of 311 side of the first chip region；Second conductive frame 320 include the second chip region 321,
The 323 and first solidus area 322 of second pin extended by the second chip region 321, second chip region 321 are used to attach
Semiconductor chip, the second pin 323 are used to draw the common port that two semiconductor chips are connected in series, first solidus
Area 322 is located at the side that second chip region 321 deviates from the second pin 323, for being attached to the first conductive frame
Semiconductor chip on 310 is electrically connected, so as to the semiconductor chip being attached on the first conductive frame 310 and be attached to second and lead
Semiconductor chip on electric frame 320 is connected in series；3rd conductive frame 330 includes the second solidus area 331 and by second
The 3rd pin 332 that solidus area 331 extends, the second solidus area 331 are used for being attached on the second conductive frame 320
Semiconductor chip is electrically connected, and the 3rd pin 332 is used to draw semiconductor chip and the institute on second conductive frame 320
State the electrode that the second solidus area 331 is electrically connected side.
Further, there is sunk structure 324 between second chip region 321 and the first solidus area 322, it is described
Sunk structure 324 is to be formed on the surface of second conductive frame 320 by way of punching press, for accommodating second core
Unnecessary solder, ensure that second conductive frame 320 during 322 weld job of section 321 and/or the first solidus area
Solidus ability and reliability.In the present embodiment, the sunk structure 324 is v-depression, in U-shaped groove, rectangular recess
Any one.
Further, the 3rd conductive frame 330 is located at the second chip region 321 on second conductive frame 320
Lower section, be arranged side by side with the second pin 323.
Further, the conductive frame 300 further includes the through hole 340 for mechanical connection, and the through hole 340 is located at institute
One end of conductive frame 300 is stated, in the present embodiment, at the end of 310 and second conductive frame 320 of the first conductive frame
The opposite side in portion opens up semicircular notch respectively, and the notch surrounds the through hole 340.
In the present embodiment, the extension side of first pin 312, the second pin 323 and the 3rd pin 332
To identical, it will be understood that first pin 312, the second pin 323 and the 3rd pin 332 can also be to not
Same direction extension, the present invention are not limited.
Referring to Fig. 2, in one embodiment, there is provided a kind of power semiconductor cascaded structure, including the first semiconductor
Conductive frame 300 described in chip 100, the second semiconductor chip 200 and any of the above-described embodiment, the conductive frame 300
Carry and be electrically connected first semiconductor chip 100 and second semiconductor chip 200.Specifically, described the first half
Conductor chip 100 be attached at electrically the first chip region 311 on first conductive frame 310 and with it is described second conductive
The first solidus area 322 on frame 320 is electrically connected；Second semiconductor chip 200 is attached at described second and leads electrically
The second chip region 321 on electric frame 320 is simultaneously electrically connected with the second solidus area 331 on the 3rd conductive frame 330.
Further, the first pole of first semiconductor chip 100 is attached at described electrically by welding manner
The first chip region 311 on first conductive frame 310, the second pole of first semiconductor chip 100 by plain conductor with
The first solidus area 322 on second conductive frame 320 is electrically connected；Second semiconductor chip 200 and described the first half
The pole that first pole polarity of conductor chip 100 is identical is attached to second conductive frame by welding manner electrically
The second chip region 321 on 320, another pole pass through the second solidus area 331 on plain conductor and the 3rd conductive frame 330
It is electrically connected.In the present embodiment, welding material used in the welding manner is scolding tin；The plain conductor for aluminum steel or
Copper wire, and the plain conductor is fixed on using ultrasonic bonding mode by the solidus area on conductive frame 300.
Specifically, the semiconductor chip is diode chip for backlight unit, patch of the diode chip for backlight unit on conductive frame 300
Mode is that anode attaches.The cathode of first semiconductor chip 100 is attached to the of metal material by welding
The first chip region 311 on one conductive frame 310, the cathode of second semiconductor chip 200 attach by welding
The second chip region 321 on the second conductive frame 320 of metal material, the anode of first semiconductor chip 100 is with being somebody's turn to do
The first solidus area 322 on second conductive frame 320 is electrically connected, the anode of second semiconductor chip 200 and the 3rd conduction
The second solidus area 331 on frame 330 is electrically connected, that is, realizes first semiconductor chip 100 and second semiconductor
Chip 200 is connected in series, formed diode series circuit structure, its schematic diagram as shown in figure 3, series connection after cathode by described
First pin 312 is drawn, and the anode after series connection is drawn by the 3rd pin 332, and the common port of two diodes is by described
Two pins 323 are drawn.
Likewise, the cathode of two diode chip for backlight unit can also be attached on different conductive frames, series connection envelope is realized
Dress.
The power semiconductor cascaded structure that the embodiment of the present invention is provided has the advantages that：
1st, conductive frame provided by the present invention, the solidus region on one of conductive frame is designed in the conductive pane
Space is saved, and effectively increase the solderable core of the conductive frame in welding chip region away from one end of extension pin on frame
The area of piece, meanwhile, design the sunk structure between welding chip region and solidus region so that welding chip region
With solidus region can independently working be independent of each other, ensure that the reliability of Weldability and solidus ability.
2nd, power semiconductor cascaded structure provided by the present invention, reduces the space of semiconductor Series Package structure, and
The trend of solidus does not conflict neatly rationally, meets the requirement of field of power electronics high power density and high reliability.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, its description is more specific and detailed, but simultaneously
Cannot therefore it be construed as limiting the scope of the patent.It should be pointed out that come for those of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of conductive frame, for serial semiconductor chip, the conductive frame includes the first conductive frame, the second conductive pane
Frame and the 3rd conductive frame, first conductive frame, second conductive frame and the 3rd conductive frame mutually insulated
It is spaced, it is characterised in that：
First conductive frame includes the first chip region and the first pin extended by first chip region；
Second conductive frame is consolidated including the second chip region, the second pin extended by second chip region and first
Line area, the first solidus area be located at second chip region deviate from the second pin side, second chip region with
There is sunk structure, the sunk structure can accommodate second chip region and/or described between the first solidus area
Unnecessary solder during one solidus area weld job；
3rd conductive frame includes the second solidus area and the 3rd pin extended by the second solidus area.
2. conductive frame according to claim 1, it is characterised in that the sunk structure is v-depression, U-shaped groove, square
Any one in connected in star.
3. conductive frame according to claim 1, it is characterised in that the through hole for mechanical connection is further included, it is described logical
Hole is located at one end of the conductive frame.
4. conductive frame according to claim 3, it is characterised in that first conductive frame and the second conductive frame
The opposite side in end opens up semicircular notch respectively, and the notch surrounds the through hole.
5. conductive frame according to claim 1, it is characterised in that the width in the second solidus area is more than the described 3rd
The width of pin.
6. a kind of power semiconductor cascaded structure, including the first semiconductor chip, the second semiconductor chip and such as claim
1-5 any one of them conductive frames, first semiconductor chip be attached at electrically first chip region and with institute
The electrical connection of the first solidus area is stated, second semiconductor chip is attached at second chip region and with described second electrically
Solidus area is electrically connected.
7. power semiconductor cascaded structure according to claim 6, it is characterised in that the of first semiconductor chip
One pole is attached at first chip region, and the second pole is electrically connected with the first solidus area on second conductive frame；Described
A two semiconductor chips pole identical with the first pole polarity of first semiconductor chip is attached at second chip region, separately
One pole is electrically connected with the second solidus area on the 3rd conductive frame.
8. power semiconductor cascaded structure according to claim 6, it is characterised in that the semiconductor chip passes through welding
Mode be attached at the conductive frame.
9. power semiconductor cascaded structure according to claim 6, it is characterised in that first semiconductor chip passes through
Plain conductor is electrically connected with the first solidus area；And/or second semiconductor chip passes through plain conductor and described second
Solidus area is electrically connected.
10. power semiconductor cascaded structure according to claim 6, it is characterised in that the plain conductor for copper wire or
Aluminum steel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711421677.2A CN107946276A (en) | 2017-12-25 | 2017-12-25 | Conductive frame and power semiconductor cascaded structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711421677.2A CN107946276A (en) | 2017-12-25 | 2017-12-25 | Conductive frame and power semiconductor cascaded structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107946276A true CN107946276A (en) | 2018-04-20 |
Family
ID=61938990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711421677.2A Pending CN107946276A (en) | 2017-12-25 | 2017-12-25 | Conductive frame and power semiconductor cascaded structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107946276A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002261230A (en) * | 2001-02-28 | 2002-09-13 | Nippon Inter Electronics Corp | Fully molded semiconductor device and lead frame used for the same |
| JP2008066553A (en) * | 2006-09-08 | 2008-03-21 | Furukawa Electric Co Ltd:The | Semiconductor device |
| CN103972184A (en) * | 2013-01-28 | 2014-08-06 | 英飞凌科技奥地利有限公司 | Chip arrangement and chip package |
| CN207800600U (en) * | 2017-12-25 | 2018-08-31 | 深圳市矽莱克半导体有限公司 | Conductive frame and power semiconductor cascaded structure |
-
2017
- 2017-12-25 CN CN201711421677.2A patent/CN107946276A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002261230A (en) * | 2001-02-28 | 2002-09-13 | Nippon Inter Electronics Corp | Fully molded semiconductor device and lead frame used for the same |
| JP2008066553A (en) * | 2006-09-08 | 2008-03-21 | Furukawa Electric Co Ltd:The | Semiconductor device |
| CN103972184A (en) * | 2013-01-28 | 2014-08-06 | 英飞凌科技奥地利有限公司 | Chip arrangement and chip package |
| CN207800600U (en) * | 2017-12-25 | 2018-08-31 | 深圳市矽莱克半导体有限公司 | Conductive frame and power semiconductor cascaded structure |
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|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180420 |