CN207800600U - Conductive frame and power semiconductor cascaded structure - Google Patents
Conductive frame and power semiconductor cascaded structure Download PDFInfo
- Publication number
- CN207800600U CN207800600U CN201721845020.4U CN201721845020U CN207800600U CN 207800600 U CN207800600 U CN 207800600U CN 201721845020 U CN201721845020 U CN 201721845020U CN 207800600 U CN207800600 U CN 207800600U
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- Prior art keywords
- conductive frame
- solidus
- chip
- area
- chip region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A kind of conductive frame of the utility model offer and power semiconductor cascaded structure, the conductive frame includes spaced first conductive frame of mutually insulated, second conductive frame and third conductive frame, second conductive frame includes the second chip region, the second pin extended by second chip region and the first solidus area, first solidus area is located at the side that second chip region deviates from the second pin, there is sunk structure between second chip region and first solidus area, the sunk structure can accommodate solder extra when second chip region and/or first solidus area's weld job.The utility model is using the one end in welding chip region as solidus region, save space, effectively increase the area of the solderable chip of the conductive frame, simultaneously, design the sunk structure between welding chip region and solidus region, so that weld job and solidus operation are independent of each other, the reliability of Weldability and solidus ability ensure that.
Description
Technical field
The utility model is related to technical field of semiconductor encapsulation, are led more particularly to a kind of conductive frame and with described
The power semiconductor cascaded structure of electric frame.
Background technology
Semiconductor devices has a wide range of applications in electronic field, and in the specific application process, it needs semiconductor
It is encapsulated.Series Package can improve such as reversed pressure resistance of the opering characteristic of electric apparatus of semiconductor, and form all kinds of power modules to coordinate
The requirement of circuit design.Solidus region is all located at conductive frame lower end and connects with pin is extended in existing semiconductor Series Package structure
Place is met, and occupied area is larger, squeezed the area in welding chip region on conductive frame, in addition, due to solidus region and weldering
Connect that chip area is adjacent, in welding chip, extra scolding tin easily flows into solidus region and influences solidus operation, otherwise also
So, cannot meet field of power electronics high power density there is an urgent need to.
Utility model content
Based on this, a kind of conductive frame of the utility model offer and power semiconductor cascaded structure.
A kind of conductive frame, is used for serial semiconductor chip, and the conductive frame includes the first conductive frame, the second conduction
Frame and third conductive frame, first conductive frame, second conductive frame and the third conductive frame are mutually exhausted
Edge is alternatively arranged, and first conductive frame includes the first chip region and the first pin for being extended by first chip region；
The second pin and the first solidus that second conductive frame includes the second chip region, is extended by second chip region
Area, first solidus area are located at the side that second chip region deviates from the second pin, second chip region and institute
Stating, there is between the first solidus area sunk structure, the sunk structure can accommodate second chip region and/or described first
Extra solder when solidus area weld job；The third conductive frame includes the second solidus area and is extended by the second solidus area
Third pin.
The sunk structure is any one in v-depression, U-shaped groove, rectangular recess in one of the embodiments,
Kind.
Further include the through-hole for mechanical connection in one of the embodiments, the through-hole is located at the conductive frame
One end.
The opposite side difference in the end of first conductive frame and the second conductive frame in one of the embodiments,
Semicircular notch is opened up, the notch surrounds the through-hole.
The width in second solidus area is more than the width of the third pin in one of the embodiments,.
A kind of power semiconductor cascaded structure, including the first semiconductor chip, the second semiconductor chip and such as above-mentioned reality
Apply any conductive frame of example, first semiconductor chip be attached at electrically first chip region and with it is described
First solidus area is electrically connected, and second semiconductor chip is attached at second chip region and consolidates with described second electrically
Line area is electrically connected.
The first pole of first semiconductor chip is attached at first chip region in one of the embodiments, the
Two poles are electrically connected with the first solidus area on second conductive frame；Second semiconductor chip and first semiconductor
The identical pole of the first pole polarity of chip is attached at second chip region, another pole and the on the third conductive frame
Two solidus areas are electrically connected.
The semiconductor chip is attached at the conductive frame by welding in one of the embodiments,.
First semiconductor chip is electrically connected by plain conductor and first solidus area in one of the embodiments,
It connects；And/or second semiconductor chip is electrically connected by plain conductor with second solidus area.
The plain conductor is copper wire or aluminum steel in one of the embodiments,.
The welding chip on the conductive frame is designed in solidus region on one of conductive frame by above-mentioned conductive frame
Space is saved, and effectively increase the area of the solderable chip of the conductive frame, together in region away from the one end for extending pin
When, design the sunk structure between welding chip region and solidus region so that welding chip region and solidus region
Can independently working be independent of each other, ensure that the reliability of Weldability and solidus ability.
Above-mentioned power semiconductor cascaded structure, reduces the space of semiconductor Series Package structure, and solidus is moved towards to close
Reason does not conflict neatly, meets the requirement of field of power electronics high power density and high reliability.
Description of the drawings
Fig. 1 is the conductive frame structure chart that the utility model embodiment provides；
Fig. 2 is the power semiconductor tandem junction composition that the utility model embodiment provides；
Fig. 3 is that the Diode series that the utility model embodiment provides encapsulate schematic diagram.
Specific implementation mode
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
Referring to Fig. 1, in one embodiment, providing a kind of conductive frame 300, it to be used for serial semiconductor chip, institute
It includes the first conductive frame 310, the second conductive frame 320 and third conductive frame 330 to state conductive frame 300, and described first leads
Electric frame 310, second conductive frame 320 and 330 mutually insulated of third conductive frame are alternatively arranged.
Further, first conductive frame 310 includes the first chip region 311 and is prolonged by first chip region 311
The first pin 312 stretched out, first chip region 311 is for attaching semiconductor chip, and first pin 312 is for drawing
Semiconductor chip is attached to the electrode of 311 side of the first chip region；Second conductive frame 320 include the second chip region 321,
The second pin 323 extended by the second chip region 321 and the first solidus area 322, second chip region 321 is for attaching
Semiconductor chip, the second pin 323 is for drawing the common end that two semiconductor chips are connected in series with, first solidus
Area 322 be located at second chip region 321 deviate from the second pin 323 side, for be attached to the first conductive frame
Semiconductor chip electrical connection on 310, so as to the semiconductor chip being attached on the first conductive frame 310 and be attached to second and lead
Semiconductor chip on electric frame 320 is connected in series with；The third conductive frame 330 is including the second solidus area 331 and by second
The third pin 332 that solidus area 331 extends, second solidus area 331 are used for and are attached on the second conductive frame 320
Semiconductor chip is electrically connected, and the third pin 332 is used to draw semiconductor chip and the institute on second conductive frame 320
State the electrode of the second solidus area 331 electrical connection side.
Further, there is sunk structure 324 between second chip region 321 and first solidus area 322, it is described
Sunk structure 324 is formed by way of punching press on the surface of second conductive frame 320, for accommodating second core
Extra solder, ensure that second conductive frame 320 when section 321 and/or first solidus, 322 weld job of area
Solidus ability and reliability.In the present embodiment, the sunk structure 324 is in v-depression, U-shaped groove, rectangular recess
Any one.
Further, the third conductive frame 330 is located at the second chip region 321 on second conductive frame 320
Lower section, be arranged side by side with the second pin 323.
Further, the conductive frame 300 further includes the through-hole 340 for mechanical connection, and the through-hole 340 is located at institute
One end of conductive frame 300 is stated, in the present embodiment, at the end of first conductive frame, 310 and second conductive frame 320
The opposite side in portion opens up semicircular notch respectively, and the notch surrounds the through-hole 340.
In the present embodiment, first pin 312, the second pin 323 and the third pin 332 extension side
To identical, it will be understood that first pin 312, the second pin 323 and the third pin 332 can also be to not
Same direction extends, and the utility model is not limited.
Referring to Fig. 2, in one embodiment, providing a kind of power semiconductor cascaded structure, including the first semiconductor
Conductive frame 300 described in chip 100, the second semiconductor chip 200 and any of the above-described embodiment, the conductive frame 300
Carry and be electrically connected first semiconductor chip 100 and second semiconductor chip 200.Specifically, described the first half
Conductor chip 100 be attached at electrically the first chip region 311 on first conductive frame 310 and with it is described second conductive
The first solidus area 322 electrical connection on frame 320；Second semiconductor chip 200 is attached at described second and leads electrically
The second chip region 321 on electric frame 320 is simultaneously electrically connected with the second solidus area 331 on the third conductive frame 330.
Further, the first pole of first semiconductor chip 100 is attached at described electrically by welding manner
The first chip region 311 on first conductive frame 310, the second pole of first semiconductor chip 100 by plain conductor with
The first solidus area 322 electrical connection on second conductive frame 320；Second semiconductor chip 200 and described the first half
The identical pole of the first pole polarity of conductor chip 100 is attached to second conductive frame by welding manner electrically
The second chip region 321 on 320, another pole pass through the second solidus area 331 on plain conductor and the third conductive frame 330
Electrical connection.In the present embodiment, welding material used in the welding manner is scolding tin；The plain conductor be aluminum steel or
Copper wire, and the plain conductor is fixed on using ultrasonic bonding mode by the solidus area on conductive frame 300.
Specifically, the semiconductor chip is diode chip for backlight unit, patch of the diode chip for backlight unit on conductive frame 300
Mode is that cathode attaches.The cathode of first semiconductor chip 100 is attached to the of metal material by welding
The first chip region 311 on one conductive frame 310, the cathode of second semiconductor chip 200 attach by welding
The second chip region 321 on the second conductive frame 320 of metal material, the anode of first semiconductor chip 100 with should
The first solidus area 322 electrical connection on second conductive frame 320, the anode and third of second semiconductor chip 200 are conductive
The second solidus area 331 electrical connection on frame 330, that is, realize first semiconductor chip 100 and second semiconductor
Chip 200 is connected in series with, formed diode series circuit structure, schematic diagram as shown in figure 3, series connection after cathode by described
First pin 312 is drawn, and the anode after series connection drawn by the third pin 332, and the common ends of two diodes is by described the
Two pins 323 are drawn.
Likewise, the anode of two diode chip for backlight unit can also be attached on different conductive frames, series connection envelope is realized
Dress.
The power semiconductor cascaded structure that the utility model embodiment is provided has the advantages that：
Solidus region on one of conductive frame is designed and is led at this by 1, conductive frame provided by the utility model
Space is saved, and it is solderable to effectively increase the conductive frame in welding chip region away from the one end for extending pin on electric frame
The area of chip is connect, meanwhile, design the sunk structure between welding chip region and solidus region so that welding chip
Region and solidus region can independently working be independent of each other, ensure that the reliability of Weldability and solidus ability.
2, power semiconductor cascaded structure provided by the utility model, reduces the sky of semiconductor Series Package structure
Between, and the trend of solidus does not conflict neatly rationally, meets the requirement of field of power electronics high power density and high reliability.
Each technical characteristic of embodiment described above can be combined arbitrarily, to keep description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Above-described embodiments merely represent several embodiments of the utility model, the description thereof is more specific and detailed,
But therefore it can not be interpreted as the limitation to utility model patent range.It should be pointed out that for the common skill of this field
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
The scope of protection of the utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (10)
1. a kind of conductive frame, is used for serial semiconductor chip, the conductive frame includes the first conductive frame, the second conductive pane
Frame and third conductive frame, first conductive frame, second conductive frame and the third conductive frame mutually insulated
It is alternatively arranged, it is characterised in that：
First conductive frame includes the first chip region and the first pin for being extended by first chip region；
Second conductive frame includes the second chip region, the second pin extended by second chip region and first consolidates
Line area, first solidus area be located at second chip region deviate from the second pin side, second chip region with
There is sunk structure, the sunk structure can accommodate second chip region and/or described the between first solidus area
Extra solder when one solidus area weld job；
The third conductive frame includes the second solidus area and the third pin that is extended by the second solidus area.
2. conductive frame according to claim 1, which is characterized in that the sunk structure is v-depression, U-shaped groove, square
Any one in connected in star.
3. conductive frame according to claim 1, which is characterized in that further include the through-hole for mechanical connection, it is described logical
Hole is located at one end of the conductive frame.
4. conductive frame according to claim 3, which is characterized in that first conductive frame and the second conductive frame
The opposite side in end opens up semicircular notch respectively, and the notch surrounds the through-hole.
5. conductive frame according to claim 1, which is characterized in that the width in second solidus area is more than the third
The width of pin.
6. a kind of power semiconductor cascaded structure, including the first semiconductor chip, the second semiconductor chip and such as claim
1-5 any one of them conductive frames, first semiconductor chip be attached at electrically first chip region and with institute
The electrical connection of the first solidus area is stated, second semiconductor chip is attached at second chip region and electrically with described second
Solidus area is electrically connected.
7. power semiconductor cascaded structure according to claim 6, which is characterized in that the of first semiconductor chip
One pole is attached at first chip region, and the second pole is electrically connected with the first solidus area on second conductive frame；Described
A two semiconductor chips pole identical with the first pole polarity of first semiconductor chip is attached at second chip region, separately
One pole is electrically connected with the second solidus area on the third conductive frame.
8. power semiconductor cascaded structure according to claim 6, which is characterized in that the semiconductor chip passes through welding
Mode be attached at the conductive frame.
9. power semiconductor cascaded structure according to claim 6, which is characterized in that first semiconductor chip passes through
Plain conductor is electrically connected with first solidus area；And/or second semiconductor chip passes through plain conductor and described second
Solidus area is electrically connected.
10. power semiconductor cascaded structure according to claim 9, which is characterized in that the plain conductor be copper wire or
Aluminum steel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721845020.4U CN207800600U (en) | 2017-12-25 | 2017-12-25 | Conductive frame and power semiconductor cascaded structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721845020.4U CN207800600U (en) | 2017-12-25 | 2017-12-25 | Conductive frame and power semiconductor cascaded structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207800600U true CN207800600U (en) | 2018-08-31 |
Family
ID=63281841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721845020.4U Active CN207800600U (en) | 2017-12-25 | 2017-12-25 | Conductive frame and power semiconductor cascaded structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207800600U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946276A (en) * | 2017-12-25 | 2018-04-20 | 深圳市矽莱克半导体有限公司 | Conductive frame and power semiconductor cascaded structure |
-
2017
- 2017-12-25 CN CN201721845020.4U patent/CN207800600U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946276A (en) * | 2017-12-25 | 2018-04-20 | 深圳市矽莱克半导体有限公司 | Conductive frame and power semiconductor cascaded structure |
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