JP2015225988A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP2015225988A JP2015225988A JP2014110854A JP2014110854A JP2015225988A JP 2015225988 A JP2015225988 A JP 2015225988A JP 2014110854 A JP2014110854 A JP 2014110854A JP 2014110854 A JP2014110854 A JP 2014110854A JP 2015225988 A JP2015225988 A JP 2015225988A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000004020 conductor Substances 0.000 claims description 92
- 229910052751 metal Inorganic materials 0.000 claims description 92
- 239000002184 metal Substances 0.000 claims description 92
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 9
- 230000008859 change Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000006378 damage Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000005674 electromagnetic induction Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910017944 Ag—Cu Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
Description
本発明は、半導体装置に関し、例えばパワーデバイスなどの電力変換用途で使用される半導体装置に関する。 The present invention relates to a semiconductor device, for example, a semiconductor device used for power conversion such as a power device.
太陽光発電システムのパワーコンディショナーや、家電や電気自動車のモーターの回転制御に使用されるパワー半導体素子は、機器の省エネに関わるキーデバイスとして注目されている。例えば直流電力から交流電力を電気的に生成するインバータは、パワー半導体素子の一例である複数個のトランジスタで構成される。 Power semiconductor elements used in power conditioners of solar power generation systems and rotation control of motors of home appliances and electric vehicles are attracting attention as key devices related to energy saving of equipment. For example, an inverter that electrically generates AC power from DC power includes a plurality of transistors that are examples of power semiconductor elements.
この場合用いられるトランジスタとしては、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）のようなパワー半導体素子がある。 As the transistors used in this case, there are power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).
これらパワー半導体素子が用いられるような大電流・高電圧を扱う機器を、パワーエレクトロニクス機器と呼ぶ。パワーエレクトロニクス機器を小型化する手法として、パワー半導体素子のスイッチング動作の高周波化が挙げられる。 Devices that handle large currents and voltages that use these power semiconductor elements are called power electronics devices. As a technique for reducing the size of power electronics equipment, there is a high frequency switching operation of a power semiconductor element.
しかしながら、単に周波数を上げると単位時間当りのスイッチング回数が増え、スイッチング動作により電流のオン・オフが切り替わるまでの時間にエネルギーをロスすることになり、そのロスはスイッチング損失と呼ばれる。スイッチング周波数が大きくなると単位時間当たりのスイッチング損失も増えることになるため、できるだけ高速にスイッチングさせ、一回分のスイッチングにおけるスイッチング損失を低減することが重要である。 However, simply increasing the frequency increases the number of times of switching per unit time, and energy is lost in the time until the on / off of the current is switched by the switching operation. This loss is called switching loss. As the switching frequency increases, the switching loss per unit time also increases. Therefore, it is important to switch as fast as possible and reduce the switching loss in one switching.
しかしながら、スイッチング動作を高速化すると、さらに別の問題が発生する。例えば、パワー半導体素子は、急激な電流の変化があると、電磁誘導による意図しない起電力が発生し、素子の最大定格電圧を超えてしまい、破壊に至る可能性がある。この誘導起電力はサージ電圧と呼ばれ、サージ電圧は、回路の持つインダクタンス成分と電流変化率に依存している。換言すると、サージ電圧を一定に保とうとすると、高速にスイッチング動作を行う場合には寄生インダクタンスを低減させる必要があることが分かる。 However, when the switching operation is speeded up, another problem occurs. For example, in a power semiconductor element, when there is a sudden change in current, an unintended electromotive force is generated due to electromagnetic induction, exceeding the maximum rated voltage of the element, which may lead to destruction. This induced electromotive force is called a surge voltage, and the surge voltage depends on the inductance component and current change rate of the circuit. In other words, if the surge voltage is kept constant, it can be seen that the parasitic inductance needs to be reduced when the switching operation is performed at high speed.
特許文献１は、従来のパワー半導体装置に関するものであり、特に前述のようなサージ電圧を抑制する方法について記載されている。構成としては正極側のアームと負極側のアームが１パッケージとなっているハーフブリッジタイプのパワーモジュールとなっており、各アームにはＩＧＢＴと、これと逆並列に接続された還流ダイオードとが一対となって配置されている。 Patent Document 1 relates to a conventional power semiconductor device, and particularly describes a method for suppressing the surge voltage as described above. The structure is a half-bridge type power module in which a positive arm and a negative arm are in one package, and each arm has a pair of IGBT and a free-wheeling diode connected in reverse parallel thereto. It is arranged.
図６及び図７に、従来のパワー半導体装置の概略図を示す。図６は平面図、図７は斜視図である。図６及び図７に示すように、セラミック基板１０１上に形成された正極側配線パターン１０２及び負極側配線パターン１０３には、それぞれＩＧＢＴ１０４と還流ダイオード１０５とが一つずつ搭載されている。正極側配線パターン１０２には、正極側バスバー１０６が接続されており、正極側配線パターン１０２に搭載されているＩＧＢＴ１０４と還流ダイオード１０５とは、その表面電極に出力側バスバー１０７が接続されている。一方、負極側配線パターン１０３に搭載されているＩＧＢＴ１０４と還流ダイオード１０５とは、その表面電極に負極側バスバー１０８が接続されている。 6 and 7 are schematic views of a conventional power semiconductor device. 6 is a plan view and FIG. 7 is a perspective view. As shown in FIGS. 6 and 7, one IGBT 104 and one free-wheeling diode 105 are mounted on each of the positive electrode side wiring pattern 102 and the negative electrode side wiring pattern 103 formed on the ceramic substrate 101. A positive electrode side bus bar 106 is connected to the positive electrode side wiring pattern 102, and an output side bus bar 107 is connected to the surface electrode of the IGBT 104 and the free wheel diode 105 mounted on the positive electrode side wiring pattern 102. On the other hand, the negative electrode side bus bar 108 is connected to the surface electrode of the IGBT 104 and the reflux diode 105 mounted on the negative electrode side wiring pattern 103.
従来のパワー半導体装置では、正極側バスバー１０６と出力側バスバー１０７と負極側バスバー１０８とが重なり合っており、ラミネート配線構造のように板状に形成して近接配置されている。ただし、各バスバーには電気的な絶縁が必要になるため、図７に示すように、これらの間に絶縁物１０９を挟んだ構成となっている。 In the conventional power semiconductor device, the positive-side bus bar 106, the output-side bus bar 107, and the negative-side bus bar 108 overlap each other, and are arranged close to each other in a plate shape like a laminate wiring structure. However, since electrical insulation is required for each bus bar, as shown in FIG. 7, an insulator 109 is sandwiched between them.
図８は、従来のパワー半導体装置の回路図を示す。例えば、図６及び図７で正極側のＩＧＢＴ１０４がオンしている場合、電流は正極側バスバー１０６から正極側配線パターン１０２を介して、正極側のＩＧＢＴ１０４のコレクタ電極に流れ、さらにエミッタ電極を通って出力側バスバー１０７に流れる。このとき、正極側バスバー１０６と出力側バスバー１０７とが重なり合う部分で、同じ大きさの電流が互いに反対方向に流れていることになる。 FIG. 8 shows a circuit diagram of a conventional power semiconductor device. For example, when the positive-side IGBT 104 is turned on in FIGS. 6 and 7, the current flows from the positive-side bus bar 106 to the collector electrode of the positive-side IGBT 104 via the positive-side wiring pattern 102 and further passes through the emitter electrode. To the output side bus bar 107. At this time, currents of the same magnitude are flowing in opposite directions at the portion where the positive-side bus bar 106 and the output-side bus bar 107 overlap.
定常的には電流の変化率は非常に小さいためインダクタンスを考慮する必要はないが、例えばインダクタンス値の影響が出る電流変化率の大きなターンオフ時においては、同じ大きさの電流が互いに反対方向に流れることによって発生する磁界を打ち消しあう作用が起こり、インダクタンス値を減少させることができる。これは負極側のＩＧＢＴ１０４の場合も同様である。 There is no need to consider inductance because the rate of change of current is very small in a steady state, but currents of the same magnitude flow in opposite directions at the time of turn-off where the rate of change of current that is affected by the inductance value is large. Thus, the action of canceling out the generated magnetic field occurs, and the inductance value can be reduced. The same applies to the case of the IGBT 104 on the negative electrode side.
つまり、従来のパワー半導体装置は、図８のように、インダクタＬ１，Ｌ２、ならびにインダクタＬ３，Ｌ４のそれぞれでインダクタンスが互いに打ち消しあう構成となっている。 That is, the conventional power semiconductor device has a configuration in which the inductances cancel each other out in the inductors L1 and L2 and the inductors L3 and L4 as shown in FIG.
しかしながら、従来のパワー半導体装置では、各バスバーが重なり合って電流の往復経路が形成されているため、出力側バスバー１０７が半導体装置の外部に出るまでの距離が長くなり、バスバーが重なり合っていない部分のインダクタンスが大きくなる。そのため、サージ電圧を充分に低減することができない可能性がある。インダクタンスは配線長に比例して大きくなるため、定格電流が大きいパワー半導体素子を使用するほど、インダクタンス成分となる配線も長くなり、サージ電圧の抑制効果が充分でない可能性がある。 However, in the conventional power semiconductor device, each bus bar is overlapped to form a current reciprocating path, so that the distance until the output side bus bar 107 comes out of the semiconductor device becomes long, and the bus bar does not overlap. Inductance increases. Therefore, there is a possibility that the surge voltage cannot be reduced sufficiently. Since the inductance increases in proportion to the wiring length, the power semiconductor element having a large rated current is used, so that the wiring as an inductance component becomes longer, and the surge voltage suppression effect may not be sufficient.
一般的に、パワー半導体装置において、正極及び負極端子はある程度近い位置に配置されて出力端子とは離間している場合が多いが、これは、配線の取り回しが容易になることに加え、配線長を短くしてサージ電圧を抑制するためである。 In general, in a power semiconductor device, the positive electrode and the negative electrode terminal are often arranged at positions close to each other and separated from the output terminal, but this is not only easy to handle the wiring but also the wiring length. This is to suppress the surge voltage by shortening the voltage.
それに対し、従来のパワー半導体装置の構成の場合、出力端子を正極及び負極端子と離間させるためには、バスバーの引き出し方向を変える必要があり、配線長が伸びてインダクタンスが増加してしまう可能性がある。 On the other hand, in the case of the configuration of the conventional power semiconductor device, in order to separate the output terminal from the positive electrode and the negative electrode terminal, it is necessary to change the direction in which the bus bar is drawn out, which may increase the wiring length and increase the inductance. There is.
かかる点に鑑みて、本発明は、サージ電圧と共にインダクタンスの増加の抑制が可能な半導体装置を提供することを目的とする。 In view of this point, an object of the present invention is to provide a semiconductor device capable of suppressing an increase in inductance along with a surge voltage.
上記課題を解決するために、本発明に係る半導体装置は、正極端子に接続される第１基板と、出力端子に接続される第２基板と、負極端子に接続される第３基板と、一面が前記第１基板に接続される一方、他面が前記第２基板に接続される正極側半導体素子と、一面が前記第２基板に接続される一方、他面が前記第１基板を跨いだ金属導体により前記第３基板に接続される負極側半導体素子と、を備えることを特徴とする。 In order to solve the above problems, a semiconductor device according to the present invention includes a first substrate connected to a positive electrode terminal, a second substrate connected to an output terminal, a third substrate connected to a negative electrode terminal, and one surface. Is connected to the first substrate while the other surface is connected to the second substrate, and one surface is connected to the second substrate, while the other surface straddles the first substrate. And a negative electrode-side semiconductor element connected to the third substrate by a metal conductor.
また、上記課題を解決するために、本発明の別の形態に係る半導体装置は、正極端子に接続される第１基板と、出力端子に接続される第２基板と、負極端子に接続される第３基板と、一面が前記第２基板に接続される一方、他面が前記第３基板を跨いだ金属導体により前記第１基板に接続される正極側半導体素子と、一面が前記第３基板に接続される一方、他面が前記第２基板に接続される負極側半導体素子と、を備えることを特徴とする。 In order to solve the above problem, a semiconductor device according to another aspect of the present invention is connected to a first substrate connected to a positive terminal, a second substrate connected to an output terminal, and a negative terminal. A third substrate, a positive-side semiconductor element having one surface connected to the second substrate, the other surface being connected to the first substrate by a metal conductor straddling the third substrate, and one surface being the third substrate And a negative electrode-side semiconductor element having the other surface connected to the second substrate.
本発明によれば、サージ電圧と共にインダクタンスの増加の抑制が可能な半導体装置を提供することができる。 ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can suppress the increase in an inductance with a surge voltage can be provided.
以下、本発明の実施の形態について、図面を参照しながら説明する。なお、各実施の形態では、インバータの基本構成単位となる１アーム分のトランジスタが搭載されている２ｉｎ１モジュールをベースとする。しかしながら、各実施の形態は、本発明に係る半導体装置の構成を限定するものではなく、例えば、３アーム分のトランジスタが搭載されている６ｉｎ１モジュールであってもよく、１アームごとに実施の形態で説明する構成を有していればよい。なお、本実施の形態の半導体装置の一例は、例えばパワーデバイスなどの電力変換用途で使用される半導体装置である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each embodiment is based on a 2-in-1 module on which a transistor for one arm, which is a basic structural unit of an inverter, is mounted. However, each embodiment does not limit the configuration of the semiconductor device according to the present invention, and may be, for example, a 6-in-1 module on which transistors for three arms are mounted. It suffices to have the configuration described in. Note that an example of the semiconductor device of this embodiment is a semiconductor device used for power conversion, such as a power device.
＜実施の形態１＞
図１は、本発明の実施の形態１に係る半導体装置の平面図である。
<Embodiment 1>
FIG. 1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention.
図１に示すように、本実施の形態の半導体装置は、第１基板の一例である正極側リードフレーム１と、第２基板の一例である出力側リードフレーム２と、第３基板の一例である負極側リードフレーム３とを有するモジュールである。モジュールは、破線で示す部分が樹脂１５によって封止されており、正極端子に接続される正極側リードフレーム１、出力端子に接続される出力側リードフレーム２、及び負極端子に接続される負極側リードフレーム３の一部が露出する状態となっている。また、正極側リードフレーム１には、正極側半導体素子として、正極側スイッチング素子４と正極側整流素子５とが搭載されている。また、出力側リードフレーム２には、負極側半導体素子として、負極側スイッチング素子６と負極側整流素子７とが搭載されている。正極側スイッチング素子４及び負極側スイッチング素子６の表面にはゲート電極９が配置されており、図示しないが別途アルミワイヤーなどで外部と接続され、正極側スイッチング素子４及び負極側スイッチング素子６のそれぞれに対する駆動制御信号が、ゲート電極９に供給される。 As shown in FIG. 1, the semiconductor device of the present embodiment includes a positive lead frame 1 that is an example of a first substrate, an output lead frame 2 that is an example of a second substrate, and an example of a third substrate. It is a module having a certain negative electrode side lead frame 3. In the module, the portion indicated by the broken line is sealed with resin 15, and the positive lead frame 1 connected to the positive terminal, the output lead frame 2 connected to the output terminal, and the negative side connected to the negative terminal A part of the lead frame 3 is exposed. The positive lead frame 1 includes a positive switching element 4 and a positive rectifying element 5 as positive semiconductor elements. Further, the output side lead frame 2 is equipped with a negative side switching element 6 and a negative side rectifying element 7 as negative side semiconductor elements. A gate electrode 9 is disposed on the surface of the positive electrode side switching element 4 and the negative electrode side switching element 6, and is connected to the outside by a separate aluminum wire or the like (not shown), and each of the positive electrode side switching element 4 and the negative electrode side switching element 6. Is supplied to the gate electrode 9.
ここで、正極側スイッチング素子４及び負極側スイッチング素子６は、例えばＩＧＢＴのようなスイッチング素子である。また、正極側整流素子５及び負極側整流素子７は、例えばＦＷＤ（Free Wheeling Diode）のような整流素子である。各素子の電極は、ＩＧＢＴであればコレクタ電極、ＦＷＤであればカソード電極となり、図示しないが、例えばＳｎ−Ａｇ−Ｃｕはんだによって正極側リードフレーム１及び出力側リードフレーム２に電気的に接合されている。 Here, the positive electrode side switching element 4 and the negative electrode side switching element 6 are switching elements such as IGBTs. Moreover, the positive electrode side rectifier element 5 and the negative electrode side rectifier element 7 are rectifier elements, such as FWD (Free Wheeling Diode), for example. The electrode of each element is a collector electrode in the case of IGBT, and a cathode electrode in the case of FWD. Although not shown, it is electrically joined to the positive lead frame 1 and the output lead frame 2 by, for example, Sn—Ag—Cu solder. ing.
本実施の形態に係る半導体装置は、第３金属導体としての負極側金属導体８ａ及び第４金属導体としての負極側金属導体８ｂが、負極側スイッチング素子６と負極側整流素子７からそれぞれ個別に引き出されていることを特徴の１つとする。負極側金属導体８ａの一端側は、負極側整流素子７の表面電極に電気的に接続され、負極側金属導体８ａの他端側は、正極側リードフレーム１を跨いで、負極側リードフレーム３に電気的に接続されている。負極側金属導体８ｂの一端側は、負極側スイッチング素子６の表面電極に電気的に接続され、負極側金属導体８ｂの他端側は、正極側リードフレーム１を跨いで、負極側リードフレーム３に電気的に接続されている。負極側金属導体８ａ，８ｂにそれぞれ接続されている各素子の電極は、ＩＧＢＴであればエミッタ電極、ＦＷＤであればアノード電極となる。 In the semiconductor device according to the present embodiment, the negative electrode side metal conductor 8a as the third metal conductor and the negative electrode side metal conductor 8b as the fourth metal conductor are individually separated from the negative electrode side switching element 6 and the negative electrode side rectifier element 7, respectively. One of the features is that it is pulled out. One end side of the negative electrode side metal conductor 8a is electrically connected to the surface electrode of the negative electrode side rectifier element 7, and the other end side of the negative electrode side metal conductor 8a straddles the positive electrode side lead frame 1 and the negative electrode side lead frame 3 Is electrically connected. One end side of the negative electrode side metal conductor 8 b is electrically connected to the surface electrode of the negative electrode side switching element 6, and the other end side of the negative electrode side metal conductor 8 b straddles the positive electrode side lead frame 1 and the negative electrode side lead frame 3. Is electrically connected. The electrodes of the respective elements connected to the negative electrode side metal conductors 8a and 8b are an emitter electrode in the case of IGBT and an anode electrode in the case of FWD.
一般的な半導体装置としては、正極側及び負極側共に、トランジスタと逆並列に配置されるダイオードは同一の金属導体で接続されており、同一極のトランジスタとダイオードの並びに対して、金属導体が同一方向に引き出されるように構成する（例えば、図６においては、紙面上のＹ方向がそれに当たる。）。そのため、例えば従来のパワー半導体装置では、図７に示すように、正極側及び負極側共に、ＩＧＢＴ１０４とＦＷＤ１０５の表面電極は一枚のバスバーで接続されており、同一極のＩＧＢＴ１０４とＦＷＤ１０５の並びに対して、バスバーの長手方向が平行である。 As a general semiconductor device, diodes arranged in reverse parallel to the transistors on both the positive electrode side and the negative electrode side are connected by the same metal conductor, and the metal conductor is the same for the array of transistors and diodes of the same electrode (For example, in FIG. 6, the Y direction on the paper surface corresponds to this). Therefore, for example, in the conventional power semiconductor device, as shown in FIG. 7, the surface electrodes of the IGBT 104 and the FWD 105 are connected by a single bus bar on both the positive electrode side and the negative electrode side. Thus, the longitudinal directions of the bus bars are parallel.
これに対して、本実施の形態に係る半導体装置は、前述のように、従来のパワー半導体装置の構成とは異なり、各素子から負極側金属導体８ａ，８ｂが個別に引き出されていることが特徴である。なお、本実施の形態に係る半導体装置の構成による詳細な効果については、後述する。 On the other hand, as described above, the semiconductor device according to the present embodiment differs from the configuration of the conventional power semiconductor device in that the negative-side metal conductors 8a and 8b are individually drawn out from each element. It is a feature. The detailed effect of the configuration of the semiconductor device according to this embodiment will be described later.
負極側金属導体８ａ，８ｂは、例えば、アルミリボンやアルミワイヤー、または銅バスバーのいずれかで形成することができる。なお、図１ではアルミリボンである場合を図示している。負極側金属導体８ａ，８ｂは、アルミリボンやアルミワイヤーの場合、各素子の表面電極と例えば超音波接合工法によって直接接続され、銅バスバーの場合、例えばＳｎ−Ａｇ−Ｃｕはんだを介して接続される。 The negative electrode side metal conductors 8a and 8b can be formed of, for example, an aluminum ribbon, an aluminum wire, or a copper bus bar. FIG. 1 shows the case of an aluminum ribbon. In the case of an aluminum ribbon or an aluminum wire, the negative electrode side metal conductors 8a and 8b are directly connected to the surface electrode of each element, for example, by an ultrasonic bonding method, and in the case of a copper bus bar, for example, are connected via Sn-Ag-Cu solder. The
図２は、本発明の実施の形態１に係る半導体装置の断面図であり、図２（ａ）は図１におけるIIａ−IIａ断面図、図２（ｂ）は図１におけるIIｂ−IIｂ断面図である。 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view taken along line IIa-IIa in FIG. 1, and FIG. 2B is a cross-sectional view taken along line IIb-IIb in FIG. It is.
図２（ａ）に示すように、第３金属導体としての負極側金属導体８ａの下側には、第１金属導体としての正極側金属導体１０ａが配置されている。この正極側金属導体１０ａは、正極側スイッチング素子４の表面電極と出力側リードフレーム２に接続されている。正極側金属導体１０ａが図１に図示されないのは、負極側金属導体８ａの直下に存在するためである。つまり、負極側金属導体８ａと正極側金属導体１０ａは、立体的に重なるように配置されている。 As shown in FIG. 2A, a positive electrode side metal conductor 10a as a first metal conductor is disposed below the negative electrode side metal conductor 8a as a third metal conductor. The positive electrode side metal conductor 10 a is connected to the surface electrode of the positive electrode side switching element 4 and the output side lead frame 2. The reason why the positive electrode side metal conductor 10a is not shown in FIG. 1 is that it exists directly under the negative electrode side metal conductor 8a. That is, the negative electrode side metal conductor 8a and the positive electrode side metal conductor 10a are arranged so as to overlap three-dimensionally.
また、図２（ｂ）に示すように、第４金属導体としての負極側金属導体８ｂの下側には、第２金属導体としての正極側金属導体１０ｂが配置されている。この正極側金属導体１０ｂは、正極側整流素子５の表面電極と出力側リードフレーム２に接続されている。正極側金属導体１０ｂが図１に図示されないのは、負極側金属導体８ｂの直下に存在するためである。つまり、負極側金属導体８ｂと正極側金属導体１０ｂは、立体的に重なるように配置されている。 Further, as shown in FIG. 2B, a positive electrode side metal conductor 10b as a second metal conductor is disposed below the negative electrode side metal conductor 8b as a fourth metal conductor. The positive electrode side metal conductor 10 b is connected to the surface electrode of the positive electrode side rectifying element 5 and the output side lead frame 2. The reason why the positive electrode side metal conductor 10b is not shown in FIG. 1 is that it exists directly under the negative electrode side metal conductor 8b. That is, the negative electrode side metal conductor 8b and the positive electrode side metal conductor 10b are arranged so as to overlap three-dimensionally.
なお、正極側金属導体１０ａ，１０ｂは、負極側金属導体８ａ，８ｂと同様に、例えば、アルミリボンやアルミワイヤー、または銅バスバーのいずれかで形成することができる。 In addition, the positive electrode side metal conductors 10a and 10b can be formed of, for example, an aluminum ribbon, an aluminum wire, or a copper bus bar, similarly to the negative electrode side metal conductors 8a and 8b.
このように、本実施の形態に係る半導体装置においては、負極側金属導体８ａは、正極側金属導体１０ａ及び正極側スイッチング素子４及び正極側リードフレーム１を跨いで負極側リードフレーム３に接続され、負極側金属導体８ｂは、正極側金属導体１０ｂ及び正極側整流素子５及び正極側リードフレーム１を跨いで負極側リードフレーム３に接続されていることを、特徴の１つとする。配線同士が立体的に重なるように配置されて近接すると、配線自身が持つ自己インダクタンス以外に、インダクタンスが配線同士で相互に影響し合う相互インダクタンスが発生する。そして、これらを合わせた合成インダクタンスが、発生するサージ電圧に実際に影響する。そして、パワーエレクトロニクス機器の一例である半導体装置の高周波化に伴う高速スイッチングの際のインダクタンスに起因するサージ電圧を抑制することで、パワー半導体素子の破壊を防ぐことができる。 Thus, in the semiconductor device according to the present embodiment, the negative electrode side metal conductor 8a is connected to the negative electrode side lead frame 3 across the positive electrode side metal conductor 10a, the positive electrode side switching element 4, and the positive electrode side lead frame 1. The negative electrode side metal conductor 8b is connected to the negative electrode side lead frame 3 across the positive electrode side metal conductor 10b, the positive electrode side rectifying element 5 and the positive electrode side lead frame 1 as one of the features. When the wirings are arranged so as to overlap each other in a three-dimensional manner, mutual inductance in which the inductances mutually affect the wirings is generated in addition to the self-inductance of the wirings themselves. Then, the combined inductance combining these actually affects the generated surge voltage. And the destruction of a power semiconductor element can be prevented by suppressing the surge voltage resulting from the inductance at the time of the high-speed switching accompanying the high frequency of the semiconductor device which is an example of power electronics equipment.
ここで、平面状の配線が平面的に配置される場合、配線同士が近接する表面積が少ないため相互インダクタンスの効果は小さいが、本実施の形態のように、平面状の金属導体（配線）を立体的に配置することで、金属導体同士が近接する表面積がより大きくなり、相互インダクタンスが大きくなり、結果として合成インダクタンスが大きくなる。 Here, when planar wirings are arranged in a plane, the effect of mutual inductance is small because the surface area where the wirings are close to each other is small, but planar metal conductors (wirings) are used as in this embodiment. By arranging in three dimensions, the surface area where the metal conductors are close to each other is increased, the mutual inductance is increased, and as a result, the combined inductance is increased.
図３は、本発明の実施の形態１に係る半導体装置の回路図である。図３を用いて、スイッチング動作時における回路上の電流の状態を説明する。図３に示すように、破線で囲まれたパワー半導体装置１１は、負荷としてインダクタ１２が接続され、その正極及び負極に直流電源１３が接続された閉回路である。パワー半導体装置１１は、半導体装置の一例である。 FIG. 3 is a circuit diagram of the semiconductor device according to the first embodiment of the present invention. The state of current on the circuit during the switching operation will be described with reference to FIG. As shown in FIG. 3, the power semiconductor device 11 surrounded by a broken line is a closed circuit in which an inductor 12 is connected as a load, and a DC power source 13 is connected to the positive electrode and the negative electrode. The power semiconductor device 11 is an example of a semiconductor device.
まず、正極側スイッチング素子４がオンしており、負極側スイッチング素子６はオフしている場合を考える。このとき、電流は、直流電源１３の正極側から正極側スイッチング素子４を経由し、インダクタ１２へ流れる。正極側整流素子５は正極側スイッチング素子４に対して、負極側整流素子７は負極側スイッチング素子６に対して、それぞれ逆並列に接続されているため、正極側整流素子５及び負極側整流素子７には、電流は流れない。また、負極側スイッチング素子６はオフ状態であるため、負極側スイッチング素子６には電流は流れない。 First, consider a case where the positive-side switching element 4 is on and the negative-side switching element 6 is off. At this time, the current flows from the positive electrode side of the DC power supply 13 to the inductor 12 via the positive electrode side switching element 4. The positive-side rectifying element 5 and the negative-side rectifying element 7 are connected in antiparallel to the positive-side switching element 4 and the negative-side switching element 6, respectively. No current flows through 7. In addition, since the negative electrode side switching element 6 is in an off state, no current flows through the negative electrode side switching element 6.
次に、正極側スイッチング素子４がターンオフする場合を考える。正極側スイッチング素子４がターンオフする際、電流は瞬時にゼロにならないため、正極側スイッチング素子４を通過する電流は、ある変化率をもって減少していくことになる。このとき、電磁誘導によってインダクタ１２に電流を流し続けようとする作用が働き、誘導起電力が発生する。インダクタ１２には電流によるエネルギーが蓄積されているため、これと誘導起電力によってインダクタ１２には電流が流れ続けるが、正極側スイッチング素子４はオフ状態に遷移する。したがって、電流は、正極側スイッチング素子４を流れるのではなく、負極側整流素子７に徐々に流れることになる。スイッチング素子と逆並列に整流素子を配置するのは、この還流電流の経路を作るためであり、インバータの基本的な構成である。この還流電流はすぐにエネルギーが消費されるため、ターンオフ期間を経て、正極側スイッチング素子４が完全にオフ状態になると共に、回路内に電流が流れなくなる。このとき、正極側スイッチング素子４及び負極側スイッチング素子６はオフ状態であり、これらが同時にオン状態となる期間は無い。 Next, consider a case where the positive side switching element 4 is turned off. When the positive-side switching element 4 is turned off, the current does not instantaneously become zero, so that the current passing through the positive-side switching element 4 decreases with a certain rate of change. At this time, an action of continuing to pass a current through the inductor 12 by electromagnetic induction works, and an induced electromotive force is generated. Since energy due to current is accumulated in the inductor 12, current continues to flow through the inductor 12 due to this and the induced electromotive force, but the positive switching element 4 transitions to the off state. Therefore, the current does not flow through the positive side switching element 4 but gradually flows through the negative side rectifying element 7. The reason why the rectifying element is arranged in antiparallel with the switching element is to create a path for the return current, and is a basic configuration of the inverter. Since the return current immediately consumes energy, the positive-side switching element 4 is completely turned off through the turn-off period, and no current flows in the circuit. At this time, the positive electrode side switching element 4 and the negative electrode side switching element 6 are in the off state, and there is no period during which they are simultaneously in the on state.
本実施の形態においては、このターンオフ期間に注目している。前述の通り、ターンオフ期間は、正極側スイッチング素子４を通る電流が減少していく期間である。この期間において電流が流れる経路の１つは、正極側リードフレーム１から正極側スイッチング素子４及び正極側金属導体１０ａを経由し、出力側リードフレーム２までの経路２１である。これに対して、ターンオフ期間において、電磁誘導により発生した還流電流が流れる経路は、負極側リードフレーム３から負極側金属導体８ａ及び負極側整流素子７を経由し、出力側リードフレーム２までの経路２２である。この経路２２は、電流が減少していく経路２１とは逆に、経路２１で減少した分だけ電流が増加していく経路である。よって、この２つの経路２１，２２は、符号が異なる単位時間当りの電流変化率を持つことになる。 In the present embodiment, attention is paid to this turn-off period. As described above, the turn-off period is a period during which the current passing through the positive switching element 4 decreases. One of the paths through which current flows during this period is a path 21 from the positive lead frame 1 to the output lead frame 2 via the positive switching element 4 and the positive metal conductor 10a. On the other hand, the path through which the return current generated by electromagnetic induction flows during the turn-off period is a path from the negative lead frame 3 to the output lead frame 2 via the negative metal conductor 8a and the negative rectifier 7. 22. In contrast to the path 21 in which the current decreases, the path 22 is a path in which the current increases by the amount decreased in the path 21. Therefore, the two paths 21 and 22 have current change rates per unit time having different signs.
ここで、本実施の形態の半導体装置は、図２（ａ）に示すように、正極側金属導体１０ａを含む経路及び負極側金属導体８ａを含む経路のそれぞれ、ならびに図２（ｂ）に示すように正極側金属導体１０ｂを含む経路及び負極側金属導体８ｂを含む経路のそれぞれが、立体的に重なる構成となっている。そのため、前述のように、自己インダクタンスに加えて相互インダクタンスの影響も考慮して、この時発生するサージ電圧は次の式（１）のように表される。 Here, as shown in FIG. 2A, the semiconductor device of the present embodiment is shown in each of the path including the positive electrode side metal conductor 10a and the path including the negative electrode side metal conductor 8a, and FIG. 2B. As described above, each of the path including the positive electrode side metal conductor 10b and the path including the negative electrode side metal conductor 8b is three-dimensionally overlapped. Therefore, as described above, in consideration of the influence of the mutual inductance in addition to the self-inductance, the surge voltage generated at this time is expressed as the following equation (1).
式（１）において、Ｌは経路２１の自己インダクタンス、Ｍは経路２１が経路２２から受ける相互インダクタンス、ｉ１は経路２１を流れる電流、ｉ２は経路２２を流れる電流である。ここで、ｄｉ１は減少しているためマイナス、ｄｉ２は増加しているためプラスとなり、これらの絶対値は同値であるため、式（１）は下記式（２）のように変換することができる。 In formula (1), L is the mutual inductance, i 1 self-inductance, M is the path 21 receives from the path 22 of the path 21 is the current flowing through the path 21, i 2 is the current through the path 22. Here, di 1 is decreasing because it is decreasing, and di 2 is increasing because it is increasing. Since these absolute values are the same value, Equation (1) can be converted as shown in Equation (2) below. Can do.
式（２）を見ると、経路２１は経路２２から受ける影響、つまり自己インダクタンスＬと相互インダクタンスＭとが打ち消し合うことによって、インダクタンスの増加を抑制すると共に、発生するサージ電圧が低減されることがわかる。 As seen from the equation (2), the influence of the path 21 from the path 22, that is, the self-inductance L and the mutual inductance M cancel each other, thereby suppressing the increase in inductance and reducing the generated surge voltage. Recognize.
ここで、図１及び図２に示す本実施の形態の半導体装置の構成の更なる特徴の１つは、上述したターンオフ期間に電流が流れる経路だけを立体的に重ねるように配置しているという点である。つまり、図３で示したように、正極側スイッチング素子４がターンオフする場合は、正極側スイッチング素子４と負極側整流素子７には電流は流れるが、負極側スイッチング素子６と正極側整流素子５には電流が流れないため、後者を通る経路はサージ電圧の発生に寄与しない。したがって、本実施の形態の半導体装置のように、これらを通る経路を立体的に重ねて近接させてもインダクタンスの低減には影響しない。そのため、本実施の形態の半導体装置で、インダクタンスを考慮するべき経路は、正極側スイッチング素子４および負極側整流素子７とこれらの素子に接続される金属導体とを含む経路だけでよい。それに対し、図６に示す従来のパワー半導体装置のように、ＩＧＢＴ１０４と還流ダイオード１０５とを同一のバスバーで接続すると、サージ電圧の低減に寄与しない経路が重なることになり、前述したような課題が発生する。 Here, one of the further features of the configuration of the semiconductor device according to the present embodiment shown in FIGS. 1 and 2 is that only the paths through which current flows during the turn-off period are arranged so as to overlap three-dimensionally. Is a point. That is, as shown in FIG. 3, when the positive side switching element 4 is turned off, a current flows through the positive side switching element 4 and the negative side rectifying element 7, but the negative side switching element 6 and the positive side rectifying element 5. Since no current flows through the path, the path through the latter does not contribute to the generation of surge voltage. Therefore, as in the semiconductor device of the present embodiment, even if the paths passing through these three-dimensionally overlap and approach each other, the inductance reduction is not affected. For this reason, in the semiconductor device of the present embodiment, the path that should take inductance into consideration is only the path including the positive side switching element 4 and the negative side rectifying element 7 and the metal conductor connected to these elements. On the other hand, when the IGBT 104 and the freewheeling diode 105 are connected by the same bus bar as in the conventional power semiconductor device shown in FIG. 6, the paths that do not contribute to the reduction of the surge voltage are overlapped. Occur.
なお、このとき、負極側金属導体８ａと正極側金属導体１０ａとを近接させるとともに、負極側金属導体８ｂと正極側金属導体１０ｂとを近接させることが重要になる。これは、自己インダクタンスと相互インダクタンスとを合成した合成インダクタンスがサージ電圧に関与し、式（２）で示したように、自己インダクタンスと相互インダクタンスが打ち消し合うように働くためである。 At this time, it is important that the negative electrode side metal conductor 8a and the positive electrode side metal conductor 10a are brought close to each other, and the negative electrode side metal conductor 8b and the positive electrode side metal conductor 10b are brought close to each other. This is because the combined inductance obtained by synthesizing the self-inductance and the mutual inductance is involved in the surge voltage and works so that the self-inductance and the mutual inductance cancel each other as shown in the equation (2).
また、図２の説明の際に述べたが、正極側金属導体１０ａ，１０ｂが負極側金属導体８ａ，８ｂの直下にあり、図１で、正極側金属導体１０ａ，１０ｂが負極側金属導体８ａ，８ｂに覆われているのは、相互インダクタンスは金属導体同士が近接するほど影響が大きくなるためであり、平面視で重なっている金属導体同士が平面的にずれていないことが好ましい。 Further, as described in the description of FIG. 2, the positive-side metal conductors 10a and 10b are directly below the negative-side metal conductors 8a and 8b. In FIG. 1, the positive-side metal conductors 10a and 10b are the negative-side metal conductor 8a. 8b is because the influence of the mutual inductance increases as the metal conductors come closer to each other, and it is preferable that the metal conductors overlapping in plan view are not displaced in a plane.
また、平面視で重なっている金属導体のそれぞれの高さも近接している方が望ましく、例えば金属導体がアルミリボンであればプロセス的なばらつきを考慮しても、例えば１．０ｍｍ前後の距離を保つような高さにすることが好ましい。これにより、経路２１及び経路２２におけるインダクタンスの低減効果を充分に得ることができるようになる。このような効果は、正極側及び負極側のそれぞれにおいて、スイッチング素子及び整流素子のそれぞれの表面電極を接続する金属導体を個別に引き出すことによって得られるものである。つまり、従来のパワー半導体装置のように同一極のトランジスタ及びダイオードの表面電極を同一の金属導体で接続すると、電流が流れない経路までもが近接して配置されるだけでなく、物理的に重ねることが困難な領域が発生してしまうため、インダクタンスを低減する効果が小さくなるだけではなく、半導体装置の回路面積が大きくなってしまう可能性がある。これに対して、本実施の形態のような構成にすることによって、出力側リードフレーム２を従来例のように無理に引き回す必要がなく、端子の配置が容易となり、さらに、半導体装置が大型化することもない。 In addition, it is desirable that the metal conductors that are overlapped in plan view are also close to each other. For example, if the metal conductor is an aluminum ribbon, a distance of, for example, about 1.0 mm is taken into consideration even if process variations are considered. It is preferable that the height be maintained. Thereby, the effect of reducing inductance in the path 21 and the path 22 can be sufficiently obtained. Such an effect is obtained by individually pulling out the metal conductors connecting the surface electrodes of the switching element and the rectifying element on the positive electrode side and the negative electrode side, respectively. In other words, when the same polarity transistor and the surface electrode of the diode are connected by the same metal conductor as in the conventional power semiconductor device, not only the path where the current does not flow is disposed close but also physically stacked. Therefore, not only the effect of reducing the inductance is reduced, but also the circuit area of the semiconductor device may be increased. On the other hand, by adopting the configuration as in the present embodiment, it is not necessary to forcibly route the output side lead frame 2 as in the conventional example, the terminal arrangement is facilitated, and the semiconductor device is increased in size. I don't have to.
また、本実施の形態では、通常の金属導体の接合プロセスをそのまま用いて、各金属導体を立体配置とすることができるため、大幅なコストアップもなく、サージ電圧を効果的に低減することができる。 In the present embodiment, since the metal conductors can be three-dimensionally arranged by using a normal metal conductor joining process as it is, the surge voltage can be effectively reduced without significant cost increase. it can.
また、本実施の形態では、正極側スイッチング素子４がターンオフする場合について説明しているが、負極側スイッチング素子６がターンオフする際も同様の考え方で同様の効果を得ることができる。 Moreover, although the case where the positive electrode side switching element 4 is turned off has been described in the present embodiment, the same effect can be obtained with the same concept even when the negative electrode side switching element 6 is turned off.
また、本実施の形態では、従来のパワー半導体装置では必要であったバスバー間の絶縁物自体や、これらを積層・接着させるためのプロセスが不要となるため、コストダウンにも繋がる。 Further, in this embodiment, since the insulator between the bus bars itself and the process for laminating and adhering them, which are necessary in the conventional power semiconductor device, are not required, the cost can be reduced.
＜実施の形態２＞
図４は、本発明の実施の形態２における半導体装置の平面図である。本実施の形態は、半導体素子をフリップチップ接合させた場合の構成である。前述の実施の形態１の構成をフェイスアップ構造と呼ぶのに対して、本実施の形態の構成はフェイスダウン構造と呼ばれる。
<Embodiment 2>
FIG. 4 is a plan view of the semiconductor device according to the second embodiment of the present invention. In this embodiment, a semiconductor element is flip-chip bonded. The configuration of the first embodiment is called a face-up structure, whereas the configuration of the present embodiment is called a face-down structure.
図５（ａ）及び図５（ｂ）は、本発明の実施の形態２に係る半導体装置の断面図であり、図５（ａ）は図４におけるＶａ−Ｖａ断面図、図５（ｂ）は図４におけるＶｂ−Ｖｂ断面図である。 5 (a) and 5 (b) are cross-sectional views of the semiconductor device according to the second embodiment of the present invention. FIG. 5 (a) is a cross-sectional view taken along the line Va-Va in FIG. These are Vb-Vb sectional drawings in FIG.
本実施の形態において、サージ電圧の低減を目的とする考え方や効果は実施の形態１と同一であるが、その構成としては、実施の形態１では正極側スイッチング素子４のコレクタ電極及び正極側整流素子５のカソード電極が正極側リードフレーム１に接続されているのに対して、本実施の形態では、これら電極が正極側金属導体１０ａ，１０ｂに接続されている点で異なる。 In the present embodiment, the concept and effect for the purpose of reducing the surge voltage are the same as those in the first embodiment. However, in the first embodiment, the collector electrode of the positive-side switching element 4 and the positive-side rectification are used in the first embodiment. While the cathode electrode of the element 5 is connected to the positive lead frame 1, the present embodiment is different in that these electrodes are connected to the positive metal conductors 10a and 10b.
また、前述の実施の形態１では、負極側スイッチング素子６のコレクタ電極及び負極側整流素子７のカソード電極が出力側リードフレーム２に接続されているのに対して、本実施の形態では、これらが負極側金属導体８ｂ，８ａと接続されている。さらに、前述の実施の形態１では、負極側金属導体８ａ，８ｂの直下に正極側金属導体１０ａ，１０ｂが平面視で重なるように配置されていたが、本実施の形態では、それらの位置関係が逆転している。 In the first embodiment, the collector electrode of the negative electrode side switching element 6 and the cathode electrode of the negative electrode side rectifying element 7 are connected to the output side lead frame 2. Is connected to the negative electrode side metal conductors 8b, 8a. Further, in the first embodiment described above, the positive electrode side metal conductors 10a and 10b are arranged so as to overlap directly below the negative electrode side metal conductors 8a and 8b. Is reversed.
また、本実施の形態では、正極側スイッチング素子４のエミッタ電極及び正極側整流素子５のアノード電極、ならびに負極側スイッチング素子６のエミッタ電極及び負極側整流素子７のアノード電極は、例えばはんだ等の接合材料１４によって、それぞれ、出力側リードフレーム２及び負極側リードフレーム３に接続されている。 Further, in the present embodiment, the emitter electrode of the positive electrode side switching element 4 and the anode electrode of the positive electrode side rectifier element 5, and the emitter electrode of the negative electrode side switching element 6 and the anode electrode of the negative electrode side rectifier element 7 are, for example, solder The bonding material 14 is connected to the output side lead frame 2 and the negative side lead frame 3, respectively.
本実施の形態における電気回路図は前述の実施の形態１と同一であるため省略するが、図３における経路２１と経路２２とが重なることによってサージ電圧が抑制可能である点は本実施の形態でも同じであり、フェイスダウン構造であっても同様の効果を得ることができる。 Although the electrical circuit diagram in the present embodiment is the same as that in the first embodiment described above, the description is omitted. However, the surge voltage can be suppressed by overlapping the path 21 and the path 22 in FIG. However, the same effect can be obtained even with the face-down structure.
なお、上記各実施の形態において、正極側及び負極側の半導体素子のそれぞれについて、スイッチング用半導体素子と整流用半導体素子とが１つのチップで実装されていてもよい。 In each of the above embodiments, the switching semiconductor element and the rectifying semiconductor element may be mounted on one chip for each of the positive electrode side and negative electrode side semiconductor elements.
また、正極側金属導体１０ａ及び負極側金属導体８ａ、ならびに正極側金属導体１０ｂ及び負極側金属導体８ｂはそれぞれ、平面視で少なくとも一部が重なっているだけでもよく、また、平面視で平行になっているだけでもよい。 Further, each of the positive electrode side metal conductor 10a and the negative electrode side metal conductor 8a, and the positive electrode side metal conductor 10b and the negative electrode side metal conductor 8b may be at least partially overlapped in plan view, and in parallel in plan view. It may just be.
また、負極側金属導体８ａ，８ｂ、及び正極側金属導体１０ａ，１０ｂの本数は任意である。 Moreover, the number of the negative electrode side metal conductors 8a and 8b and the positive electrode side metal conductors 10a and 10b is arbitrary.
本発明に係る半導体装置は、パワーエレクトロニクス機器の高周波化に伴う高速スイッチングの際のインダクタンスに起因するサージ電圧を抑制し、パワー半導体素子の破壊を防ぐことができるという効果を有し、大電力・大電流対応の半導体装置などとして有用である。 The semiconductor device according to the present invention has the effect of suppressing the surge voltage caused by the inductance at the time of high-speed switching accompanying the increase in the frequency of the power electronics equipment and preventing the destruction of the power semiconductor element. It is useful as a semiconductor device for large current.
１ 正極側リードフレーム
２ 出力側リードフレーム
３ 負極側リードフレーム
４ 正極側スイッチング素子
５ 正極側整流素子
６ 負極側スイッチング素子
７ 負極側整流素子
８ａ，８ｂ 負極側金属導体
９ ゲート電極
１０ａ，１０ｂ 正極側金属導体
１１ パワー半導体装置
１２ インダクタ
１３ 直流電源
１４ 接合材料
１５ 樹脂
２１，２２ 経路
１０１ セラミック基板
１０２ 正極側配線パターン
１０３ 負極側配線パターン
１０４ ＩＧＢＴ
１０５ 還流ダイオード
１０６ 正極側バスバー
１０７ 出力側バスバー
１０８ 負極側バスバー
１０９ 絶縁物
DESCRIPTION OF SYMBOLS 1 Positive electrode side lead frame 2 Output side lead frame 3 Negative electrode side lead frame 4 Positive electrode side switching element 5 Positive electrode side rectification element 6 Negative electrode side switching element 7 Negative electrode side rectification element 8a, 8b Negative electrode side metal conductor 9 Gate electrodes 10a, 10b Positive electrode side Metal conductor 11 Power semiconductor device 12 Inductor 13 DC power supply 14 Bonding material 15 Resin 21 and 22 Path 101 Ceramic substrate 102 Positive electrode side wiring pattern 103 Negative electrode side wiring pattern 104 IGBT
105 Free-wheeling diode 106 Positive side bus bar 107 Output side bus bar 108 Negative side bus bar 109 Insulator
Claims (7)
出力端子に接続される第２基板と、
負極端子に接続される第３基板と、
一面が前記第１基板に接続される一方、他面が前記第２基板に接続される正極側半導体素子と、
一面が前記第２基板に接続される一方、他面が前記第１基板を跨いだ金属導体により前記第３基板に接続される負極側半導体素子と、を備える、
半導体装置。 A first substrate connected to the positive terminal;
A second substrate connected to the output terminal;
A third substrate connected to the negative terminal;
A positive-side semiconductor element having one surface connected to the first substrate and the other surface connected to the second substrate;
A negative electrode side semiconductor element having one surface connected to the second substrate and the other surface connected to the third substrate by a metal conductor straddling the first substrate.
Semiconductor device.
出力端子に接続される第２基板と、
負極端子に接続される第３基板と、
一面が前記第２基板に接続される一方、他面が前記第３基板を跨いだ金属導体により前記第１基板に接続される正極側半導体素子と、
一面が前記第３基板に接続される一方、他面が前記第２基板に接続される負極側半導体素子と、を備える、
半導体装置。 A first substrate connected to the positive terminal;
A second substrate connected to the output terminal;
A third substrate connected to the negative terminal;
A positive-side semiconductor element having one surface connected to the second substrate and the other surface connected to the first substrate by a metal conductor straddling the third substrate;
A negative electrode side semiconductor element having one surface connected to the third substrate and the other surface connected to the second substrate,
Semiconductor device.
前記正極側半導体素子に含まれる前記スイッチング素子の他面と前記第２基板とは、第１金属導体により接続され、
前記正極側半導体素子に含まれる前記整流素子の他面と前記第２基板とは、第２金属導体により接続され、
前記負極側半導体素子に含まれる前記スイッチング素子の他面と前記第３基板とは、前記第１基板を跨いだ第４金属導体により接続され、
前記負極側半導体素子に含まれる前記整流素子の他面と前記第３基板とは、前記第１基板を跨いだ第３金属導体により接続された、
請求項１に記載の半導体装置。 Each of the positive electrode side semiconductor element and the negative electrode side semiconductor element includes a switching element and a rectifying element connected in reverse parallel,
The other surface of the switching element included in the positive electrode side semiconductor element and the second substrate are connected by a first metal conductor,
The other surface of the rectifier element included in the positive electrode side semiconductor element and the second substrate are connected by a second metal conductor,
The other surface of the switching element included in the negative electrode-side semiconductor element and the third substrate are connected by a fourth metal conductor straddling the first substrate,
The other surface of the rectifying element included in the negative electrode-side semiconductor element and the third substrate are connected by a third metal conductor straddling the first substrate.
The semiconductor device according to claim 1.
前記正極側半導体素子に含まれる前記スイッチング素子の他面と前記第１基板とは、前記第３基板を跨いだ第１金属導体により接続され、
前記正極側半導体素子に含まれる前記整流素子の他面と前記第１基板とは、前記第３基板を跨いだ第２金属導体により接続され、
前記負極側半導体素子に含まれる前記スイッチング素子の他面と前記第２基板とは、第４金属導体により接続され、
前記負極側半導体素子に含まれる前記整流素子の他面と前記第２基板とは、第３金属導体により接続された、
請求項２に記載の半導体装置。 Each of the positive electrode side semiconductor element and the negative electrode side semiconductor element includes a switching element and a rectifying element connected in reverse parallel,
The other surface of the switching element included in the positive electrode side semiconductor element and the first substrate are connected by a first metal conductor straddling the third substrate,
The other surface of the rectifying element included in the positive electrode side semiconductor element and the first substrate are connected by a second metal conductor straddling the third substrate,
The other surface of the switching element included in the negative electrode-side semiconductor element and the second substrate are connected by a fourth metal conductor,
The other surface of the rectifying element included in the negative electrode-side semiconductor element and the second substrate are connected by a third metal conductor,
The semiconductor device according to claim 2.
前記第１及び第４金属導体は、それぞれ平行となるように配置されており、
前記第２及び第３金属導体は、それぞれ平行となるように配置されている、
請求項３及び４のうちいずれか１つに記載の半導体装置。 In plan view of the semiconductor device,
The first and fourth metal conductors are arranged so as to be parallel to each other,
The second and third metal conductors are arranged so as to be parallel to each other,
The semiconductor device according to claim 3.
前記第１及び第４金属導体は、それぞれ少なくとも一部が重なるように配置されており、
前記第２及び第３金属導体は、それぞれ少なくとも一部が重なるように配置されている、
請求項３乃至５のうちいずれか１つに記載の半導体装置。 In plan view of the semiconductor device,
The first and fourth metal conductors are arranged so that at least a part thereof overlaps,
Each of the second and third metal conductors is disposed so that at least a part thereof overlaps,
6. The semiconductor device according to any one of claims 3 to 5.
請求項３乃至６のうちいずれか１つに記載の半導体装置。 The first to fourth metal conductors are any one of an aluminum wire, an aluminum ribbon, and a copper bus bar.
The semiconductor device according to claim 3.
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