CN107845690A - 多结光伏器件及其制备方法 - Google Patents

多结光伏器件及其制备方法 Download PDF

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CN107845690A
CN107845690A CN201711071248.7A CN201711071248A CN107845690A CN 107845690 A CN107845690 A CN 107845690A CN 201711071248 A CN201711071248 A CN 201711071248A CN 107845690 A CN107845690 A CN 107845690A
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gaas
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photovoltaic devices
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CN107845690B (zh
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安德鲁·约翰逊
安德鲁·威廉·尼尔森
罗伯特·卡梅伦·哈伯
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Abstract

多结光伏器件及其制备方法，其中多结光伏器件是具有两个或更多由半导体材料形成的光吸收元件的多结光伏器件，其包括：第一硅锗或硅锗锡材料元件，第二硅锗锡材料元件，其中，第一硅锗或硅锗锡材料元件和所述第二硅锗锡材料元件与砷化镓晶格匹配。

Description

多结光伏器件及其制备方法
本申请是申请日为2012年8月14日，申请号为CN201280049676.9的专利申请的分案申请。
技术领域
本发明涉及包括太阳能电池的光伏器件。
背景技术
一种公知的光电器件具有两个或多个串联连接的由垂直层结构的半导体材料形成的元件（cell），每个元件包含不同带隙的p-n结，这些结用于吸收照在器件（串叠型元件）上的光的不同光谱。当前使用的多结光伏器件大多数是在锗衬底上制造而得。
图1示出了这种器件的下部元件的典型结构。其中提供p型锗（Ge）衬底1，通过在锗衬底上生长III- V族半导体材料层3来制作器件的第一p-n结2 ，锗衬底和层3相接触于界面8。层3在本领域中被称为成核层。在处理时使用高温的条件下，来自成核层3的V族原子扩散并穿过界面进入锗衬底，并在低于锗衬底表面的位置处产生p-n结。该结形成的原因是由于V族原子充当了锗衬底的n型掺杂剂，所以当V族原子扩散到足够浓度时，形成n型区域4。（当然n型区域4的另一边界是III-V族材料和IV族材料之间的界面8。）III- V族层3设置为n型，使得III- V族层和Ⅳ族n型区域4之间为低阻接触。V族原子的扩散深度的控制对于限定p-n结优选为浅结的质量很重要。该扩散受约束于成核层3和任一另外的半导体层5 的生长和退火（及任何其它处理）的温度及持续时间。设置该另外的半导体层5以形成一个或更多另外的用于吸收不同光谱的p-n结。美国专利US6,380,601和US 2002/0040727公布了具有类似图1的底部元件的多结太阳能电池的例子。
S. Strite、M.S. Ünlü、K. Adomi和H. Morkoç于1990年（《应用物理学报》，56（17））发表论文“硅作为锗/砷化镓异质结的扩散阻挡层（Si as a diffusion barrier in Ge/GaAs heterojunctions）”。该论文的作者们感兴趣于光电晶体管和基于空穴的调制掺杂结构，并在论文中探讨了他们对长满锗的砷化镓（GaAs）外延层制成的二极管的调查。据称该基本二极管受影响于由不佳样品均匀性产生的微等离子体辅助故障，他们认为，不佳样品均匀性由GaAs的空位（由Ga和As依次向外扩散到Ge而产生）产生。为防止这一点，设置10埃（Å）厚的假晶硅中间层。（锗为p型且掺杂Ga，掺杂浓度为5×1018 cm-3。异质结处的GaAs掺杂硅的浓度较少，为5×1016 cm-3。）特别地，其可以受约束于预定深度。
太阳能电池用于产生电能，优选地从太阳光中产生电能。它们可直接受太阳光照射，或者利用聚光器收集较高强度的太阳光到电池上，从而提高其效率。
发明内容
根据本发明，提供一种半导体材料，包括：
IV族半导体材料层，所述材料不为硅，
由至少一种III族原子和至少一种V族原子组成的III-V族半导体材料层，其与所述IV族半导体层相接于一界面，
硅层，其或者位于所述III-V半导体层和所述IV族半导体层之间的所述界面上，或者位于所述IV族半导体层或所述III-V半导体层中，且与所述界面隔开，
位于所述IV族半导体层的n型V族掺杂区域，其与所述界面毗邻，并且受形成为III-V族半导体层的至少一种V族原子掺杂。
所述硅层的作用是控制所述V族原子进入所述IV族层的扩散（通过减少V族原子的方式），因此控制所述IV族层在其深度和浓度方面的掺杂。另外，通过改变所述硅层的浓度来改变不同需求的掺杂。以这种方式，所述IV族的掺杂可以根据需要控制。
面对所述硅层的特定一侧的所述IV族半导体层中的n型V族掺杂区域的一部分受形成为位于所述硅层的相反一侧的III-V族半导体部分的至少一种V族原子掺杂。
掺杂于面对所述硅层的特定一侧的所述IV族半导体层部分的至少一些所述V族原子来自于位于所述硅层的相反一侧的III-V族层部分。
所述IV族半导体层的n型V族掺杂区域受形成为与所述界面毗邻的所述III-V族半导体层的区域的至少一种V族原子掺杂。
所述半导体层的所述V族掺杂区域在所述IV族层中设有p-n结和p型区域。
所述界面处的所述III-V族材料为n型。
所述III-V族材料层是n型。
或者，所述IV族层的所述V族掺杂区域和III-V族层在所述界面处形成隧道二极管。所述界面处的所述III-V族材料可以是p-掺杂。
所述IV族半导体材料层可以是锗，或者硅-锗，或者硅-锗-锡。
所述III-V族材料可包括为铝、镓、铟中的一个或多个III族原子，以及包括为磷、砷、锑、铋中的一个或多个V族原子。所述III-V族材料可以包括选自包含InGaAsP、AlGaAs、AlGaAsP、GaAs、GaAsP、AlAs、InGaP、InGaAs、AlInGaAs、AlInGaP的组的材料。
所述IV族层可以包括介于所述硅层和所述III-V族半导体层之间的外延IV族半导体层。
所述III-V族半导体层可以包括介于所述硅层和所述IV族半导体层之间的外延III-V族半导体层。
所述IV族半导体层可以包括衬底层和生长于所述衬底层上的外延层。
优选地，所述硅层的厚度小于或等于7.5埃，或者所述硅层为小于或等于3原子层。所述硅层为小于或等于1个原子层，或者所述硅层小于1个原子层。
与所述界面毗邻的所述III-V族半导体层的掺杂浓度可以为大于1×1017个原子/立方厘米，或者大于1×1018个原子/立方厘米，或介于1×1018个原子/立方厘米和5×1018个原子/立方厘米之间。
所述IV族半导体层中的所述n型V族掺杂区域的V族原子的掺杂浓度可以为大于1×1017个原子/立方厘米，或者大于1×1018个原子/立方厘米，或者大于6×1018个原子/立方厘米。
所述IV族层的非V族原子掺杂的掺杂浓度可以是小于4×1018个原子/立方厘米，或者介于5×1016个原子/立方厘米和2×1018个原子/立方厘米之间，或者介于1×1017个原子/立方厘米和1×1018个原子/立方厘米。
所述半导体材料可以包括具有与所述IV族半导体层相接的界面的第二III-V族半导体材料层，所述界面位于所述IV族层与所述第一III-V族层相接的界面的相对侧，以及可以包括位于所述第二III-V半导体层和所述IV族层之间的所述界面的第二硅层。
本发明还提供了一种光伏器件，所述光伏器件包含光吸收元件，所述光吸收元件包括本发明的半导体材料。
所述光伏器件可包括多个光吸收元件，一个或更多所述光吸收元件包括本发明的半导体材料。所述多个元件中的一个元件的带隙与所述多个元件中的另一个元件的带隙不同。所述光吸收元件可以是光吸收p-n结二极管。所述光伏器件可以是太阳能电池。
本发明还提供了一种制备半导体材料的方法，包括：
提供IV族半导体材料层，所述材料不为硅，
提供由至少一种III族原子和至少一种V族原子组成的III-V族半导体材料层，其与所述第IV族半导体层相接于一界面，
提供硅层，其或者位于所述III-V族半导体层之间的所述界面，或者位于所述IV族半导体层或所述III-V族半导体层中，且与所述界面隔开，
扩散所述III-V族材料层的V族原子并越过所述硅层以与所述IV族材料掺杂，以便在与所述界面毗邻的所述IV族半导体层中形成n型V族掺杂区域。
所述V族原子的扩散可在所述IV族层中形成p-n结。
所述V族原子可以扩散进入所述IV族层的已经为n型的区域中，以形成具有高浓度n型掺杂剂的n型掺杂区域。
所述III-V层可直接生长于所述IV组上或者所述硅层上。
使用根据本发明的材料或根据本发明的方法制成的材料以从太阳光产生电力，这一方法包括：
提供这些材料形成的太阳能电池，和
让太阳光照射所述太阳能电池。所述方法可以包括聚集照射在太阳能电池上的太阳光的步骤。
根据本发明的第二方面，提供一种具有两个或更多由半导体材料形成的光吸收元件的多结光伏器件，包括：
第一硅锗或硅锗锡材料元件，
第二硅锗锡材料元件，
其中，所述第一硅锗或硅锗锡材料元件和所述第二硅锗锡材料元件与砷化镓晶格匹配。
所述多结光伏器件可以进一步包括砷化镓材料元件。
所述多结光伏器件可以进一步包括与砷化镓晶格匹配的磷化铟镓材料元件。
所述多结光伏器件可以进一步包括与砷化镓晶格匹配的铝砷化镓材料元件，或是与砷化镓晶格匹配的磷化铝铟镓材料元件。
所述多结光伏器件可包括砷化镓衬底，所述各元件的各半导体层位于所述衬底上且与所述衬底晶格匹配。或者，所述多结光伏器件可包括与砷化镓晶格匹配的衬底，所述各半导体层位于所述衬底上且与所述衬底晶格匹配。
所述多结光伏器件可以是太阳能电池。
优选地，所述第一元件是硅锗材料制成。
本发明的第二方面还提供了一种制备多结光伏器件的方法，包括：
提供砷化镓衬底或者是与砷化镓晶格匹配的另一种材料的衬底，
生长与所述衬底晶格匹配的第一硅锗或硅锗锡材料元件，
生长与所述第一光吸收元件晶格匹配的第二硅锗锡材料元件。
该方法可包括生长砷化镓材料元件。
该方法可包括生长与砷化镓晶格匹配的磷化铟镓元件。
该方法可以包括生长与砷化镓晶格匹配的铝砷化镓材料的光吸收层。
该方法可以包括生长与砷化镓晶格匹配的磷化铝铟镓元件。
所述方法可包括在两个相邻的所述元件之间设置至少一个另外的层，所述至少一个另外的层与砷化镓晶格匹配。
所述方法可包括去除所述衬底。
附图说明
现将参考附图来描述本发明的各实施例，其中：
图1为已知的多结光伏材料的下部元件的半导体层的横截面示意图，
图2为根据本发明第一实施例的多结光伏器件的下部元件的半导体层的横截面示意图，
图3为根据本发明第二实施例的多结光伏器件的下部元件的半导体层的横截面示意图，
图4为根据本发明第三实施例的多结光伏器件的下部元件的半导体层的横截面示意图，
图5为根据本发明第四实施例的多结光伏器件的下部元件的半导体层的横截面示意图，
图6为根据本发明第五实施例的多结光伏器件的下部元件的半导体层的横截面示意图，
图7为根据本发明第六实施例的多结光伏器件的下部元件的半导体层的横截面示意图，
图8为相比具有和不具有本发明的硅层的半导体层结构的二次离子质谱图的示意图，
图9为使用本发明的器件的另一实施例的示意图，
图9A和图9B示出了在图9的器件中使用本发明的实施例，
图10A至图10D示出了形成本发明的涉及在衬底之间进行SiGe层转移的实施例，
图11为使用本发明的器件的另一实施例的示意图，
图11A至图11D示出了使用本发明的实施例，以及
图12为使用本发明的隧道二极管的实施例，
图13是合金SiGeSn的带隙和晶格常数的曲线图，其示出了该合金可与GaAs和Ge晶格匹配及所得到的带隙。
具体实施方式
图2示出了根据本发明的第一实施例的光伏器件。其中显示了由下部元件的各层和假设存在的另一半导体层5的横截面，层5以虚线表示，其中可形成一个或更多另外的p-n结。通常该结构类似图1所示的结构。其中提供了p型IV族半导体衬底1，例如锗，以及生长于衬底上的n型III-V族半导体层3，衬底1与半导体层3相接于界面8。来自于III-V层3的V族原子也再次扩散进入形成与界面8相邻的n型区域4的IV族层，这样，在该区域与剩下的IV族材料的p型部分接触之处为p-n结2。但是，层3和IV族衬底1之间首先设置一薄硅层6。（下文将讨论可能的特定的IV族半导体材料，但该材料并非硅本身。下文还将讨论可能的III-V族材料。）
图3示出了类似第一实施例的第二实施例，不同的是在硅层6上生长III-V族材料的成核层3之前，首先在硅层6生长IV族半导体外延层7（除硅本身外）。一般地，该层 7可以在生长时首先被掺杂为p型或n型。
在这些实施例中，硅层6的作用是控制V族原子从层3进入IV族材料的扩散。硅充当V族扩散的阻挡层，因此在形成器件的相同处理条件下p-n结2较浅，即p-n结的位置更靠近IV族半导体和成核层之间的界面8。该阻挡层不是绝对的；其减少而不是完全消除，V族自III-V材料扩散入位于Si阻挡层的相对侧的IV族材料，该III-V材料是V族原子的来源。阻挡层厚度的设置可用来控制p-n结2的深度。
在这些实施例中，阻挡层6的优选的厚度是3个单硅层（7.5埃）或更小。的确，其可以是小于一个完整的单层。由于硅层处于应变状态，硅层的优选的最大厚度为3个单层（因为其尽量与IV族半导体晶格参数匹配）。超过该临界厚度，硅层中形成位错以释放该应变，且这些位错不利于器件的性能。该最多3个单层的范围也在光伏器件内产生优选的结的深度。
在第二实施例（图3）中，IV族外延层7的厚度应优选地不超过一定距离，其为在器件的加工中V族原子通过扩散进入IV族半导体材料的距离，因为超过该距离，V族原子穿越Si阻挡层的数量将是最小。一般来说，该距离最大为1微米，其取决于所使用的V族种类以及器件加工步骤中的温度。
（关于图3的实施例，有一点要注意，当p-n结2通常处于硅阻挡层6的远离III-V层的另一侧时，本发明一般包括这样的情况，其中阻挡层6限制了V族原子的扩散，该扩散不足以穿越该阻挡层以将IV族材料转为n型，p-n结位于阻挡层之上或在阻挡层周围*（*表示这一过程的p-n结的延伸大于阻挡层的几个单层）。）
图4和图5示出了分别具有与第一实施例和第二实施例（图2和图3）相同的层的第三实施例和第四实施例，但是不同的是，在生长硅层6和III-V层3之前，首先设置p型IV族半导体的外延层10。在该具体实施例中，外延层10生长在衬底1上，但可能具有中间层。这种具有层10作为外延层的方案也有助于精确地控制IV族半导体材料中的结的厚度和掺杂分布。优选地，层10的厚度足以使p-n结2形成于IV族外延层10中，如图所示，而不是形成于衬底1（或者是形成于IV族材料的中间层），但并不排除后者。然而，还要注意的是，衬底1不一定是IV族材料，因为IV族外延层10可以生长在其他材料上。
图6和图7示出了分别具有与第一实施例和第三实施例（图2和4）相同的层的第五实施例和第六实施例，但不同的是，在生长硅层6和主III-V层3之前，在IV族层上首先设置n型III-V族半导体材料外延层9。再次地，硅层充当阻挡层，以控制V族原子从层3扩散进入到处于阻挡层6的另一侧的IV族材料。 IV族材料也受扩散自层9的V族原子的掺杂。对于Si阻挡层的存在，在器件的加工条件下，为使IV族层中的掺杂程度与位于阻挡层另一侧的III-V族层具有明显差异，该III-V族外延层9应薄于一定距离，其为来自层3的V族原子扩散并穿过层9的距离。
IV族半导体材料的一种举例中，在该材料内形成了p-n结，此时该材料为锗。另外锗衬底是现成的。作为衬底的锗的优选取向略错位于（100）和（111）。（本领域公知衬底与准确的晶面是错位的。）
除了锗，也可以使用IV族半导体，例如硅-锗和硅-锗-锡。SiGe和SiGeSn不能作为基础衬底，但可以生长在晶格匹配的GaAs上。在本发明中，这种SiGe和SiGeSn也可以从其原始GaAs衬底上去除，并在使用前附着于更便宜的衬底。下文将描述这一过程的实施例。可以使用SixGe1-x，其中x高达至少0.04并且可能x=0.06或以上，但x的优选范围是0.01<=x<=0.03。对于x离开约为x=0.018的晶格匹配条件时每0.01的变化，将使SixGe1-x与GaAs相应的晶格错配为约0.04％。图13为合金SiGeSn的带隙和晶格常数的曲线图，示出了其与GaAs晶格匹配的SiGeSn的带隙范围为0.66 - 1.1eV。图13还示出了SiGeSn可以与Ge晶格匹配，并且由于Ge的晶格参数相当接近GaAs的晶格参数，SiGeSn可以与Ge晶格匹配的带隙范围类似于上面给出的SiGeSn与GaAs晶格匹配的范围。SiGeSn和GaAs晶格匹配，其中Si与Sn的比例为约4:1。例如当Si的比例为2%且Sn的比例为0.5%时，其提供了比SiGe与GaAs晶格匹配更大的带隙，当Si的比例为8 ％且Sn的比例为2％，该带隙较宽，而当这些比例更大时，该带隙可以进一步扩展——例如，在限制为80 ％的Si和20 ％的Sn时，材料的带隙为1.1eV左右。
正如本领域所知，成核层3可以由不同的III-V族材料制成，例如InGaAs、InGaP。其他材料可以是InGaAsP、AlGaAs、AlGaAsP、GaAs、GaAsP、AlAs、InGaP、InGaAs、AlInGaAs、AlInGaP等。这些也包括那些包含Sb（或可能是Bi）作为V族原子材料或者V族原子材料中的一个。正如本领域所知，大多数这些材料可以生长于锗、硅或硅-锗、硅-锗-锡中的至少一种上，且与其晶格匹配或几乎晶格匹配。
许多这些材料含有As和/或P的V族原子。这里，应当指出，As和P都从III-V族材料扩散进入到IV族材料，且IV族材料至少为Ge，As进一步扩散并且扩散速度比P快。
当存在一个以上的III-V外延层（例如，图6和图7所示实施例中的外延层3和9），优选地，这些层具有根据III族和V族原子的相同成分，该成分不仅构成基本材料，而且在沉积过程中提供了掺杂剂。然而， 差异是有可能的，并且在IV族区域中控制掺杂成分可能是有用的。事实上，并不排除一个层内的差异。
同样，当有一个以上的IV族的外延层（例如图5所示实施例），优选地，这些层具有根据IV族原子的相同成分，该成分不仅构成基本材料，而且在前述讨论的V族扩散之前提供掺杂剂，例如在IV族材料沉积时。然而，差异是有可能的。事实上，也不排除一个层内的成分和/或掺杂的差异。
然而，正如本领域中对待外延层的常见做法那样，即使外延层和衬底为相同的基本材料，优选为IV族外延层和衬底（图4、图5和图7）以具有不同的掺杂。
如上面所预示以及在GaAs上生长SiGe和SiGeSn的实施例，用于IV族层10的材料可以生长在非IV族材料的衬底上。
如下将描述可以使用的或者是优选的一些掺杂浓度。对于界面处的III-V层及IV族层，掺杂浓度通常大于1×1017个原子/立方厘米；更优选地，掺杂浓度大于1×1018个原子/立方厘米，并且更优选地，掺杂浓度介于1×1018个原子/立方厘米和5×1018个原子/立方厘米之间。形成为IV族材料内的掺杂物的已扩散的V族原子的数量通常大于1×1017个原子/立方厘米；优选地，大于1×1018个原子/立方厘米，且可以大于6×1018个原子/立方厘米。对于IV族层的剩余部分（未被V族原子显著扩散的部分），掺杂浓度通常小于4×1018个原子/立方厘米；优选地，介于5×1016个原子/立方厘米与2×1018个原子/立方厘米，更优选地，介于1×1017个原子/立方厘米与1×1018个原子/立方厘米。
硅层6和其它层可以使用常规技术生长。一些可能的方法见下文。
例如，硅层可以生长于常见的MOCVD反应器，MOCVD反应器也用于提供III-V层的外延（这种设备通常用于多结光伏器件的III-V外延）。这特别适合于但不限于第一种实施例（图2），因为锗衬底（其被视为IV族半导体材料的一种举例）可以被直接放置在MOCVD反应器中，然后其将用于依次生长硅层和III-V层。硅被作为这种反应器中的掺杂剂源，因此硅可用于直接将硅先于III-V成核层沉积在锗衬底上。
硅层6也可以在CVD沉积设备中外延生长，该设备用于锗、硅和硅-锗或硅-锗-锡的生长。这特别适合于但不限于第二种实施例（见图3），因为锗等衬底可以首先被放置在该设备内，然后依次生长硅层6和Ge外延层7。然后工件可被转移到MOCVD反应器（优选地使用集群设备装置，使得锗外延层7保持清洁）以沉积III-V层3。
MBE也可用于沉积III-V材料或硅。
图8是其底部元件(a)具有和(b)不具有本发明的界面处的硅层的InGaAs/Ge结的多结串叠元件设备的二次离子质谱图的比较示意图。纵轴是As原子在Ge中的浓度，单位为原子/立方厘米，横轴是进入Ge层的深度，单位为微米。该图清楚地表明，在具有硅层时，扩散进入InGaAs层的As掺杂剂被限制为进入Ge层1微米的深度((a))；而在没有硅层的控制中，但在同样的工艺条件的其他方面，As原子已经渗透到约4微米((b))。另外，在具有Si层的样品中As原子的浓度较低。这些观测数据表明，Si层充当了As扩散的阻挡层。类似的结果可通过具有不同V族原子的III-V半导体材料得到。
根据本发明，具有硅层的三结光伏结构的样品也已被测量，同样在开路电压（Voc）下，当受1-太阳照射时具有硅层的样品比不具有硅层的样品在最大功率输出方面提供了有用的增长。
图9示出了使用本发明的多结太阳能电池的另一种实施例，这次是对所有元件的描述。图中示出了器件的各元件的串叠布置（其中每个由不同半导体层组成，但这些半导体层不再详细说明）。根据本发明，该器件从GaAs衬底91开始，SiGe元件92生长于该衬底上（因此其包括具有p-n结的SiGe层、Si扩散阻挡层及其上提供掺杂的的III-V层（例如GaInP），图示的元件92中未详细示出这些层）。SiGe元件之上设置GaAs元件94和InGaP元件96。分别在SiGe元件和GaAs元件之间以及在GaAs元件和InGaP元件之间的隧道二极管93和95减少了元件间的阻抗。最后，窗口层97用于保护器件但允许光进入，且其上的金属接触线99用于收集该器件产生的电流。最后采用抗反射涂层98覆盖窗口。
图9A详细示出图9的底部元件92和衬底91的一种实施例（尽管当然该实施例的使用不局限于图9所示的具体实施例）。其中具有图4所示实施例的结构且衬底1为GaAs。衬底上生长p型SiGe的外延层10，其很大程度上（或精确地）与GaAs晶格匹配。外延层上生长Si扩散阻挡层6，层6上生长III-V成核层3，再次地，其很大程度上（或精确地）与SiGe晶格匹配。在层3的沉积条件以及随后的处理步骤的条件下，受限制于阻挡层6，V族原子从层3扩散进入SiGe并进行掺杂，以形成与界面8相邻的n型区域4，因此在SiGe层10中形成了p-n结2。类似的实施例中，SiGe层10替代为由SiGeSn组成。
在该器件中，SiGe（或SiGeSn）和来自GaAs衬底1的V族原子掺杂存在潜在问题：SiGe通过As原子从p型到n型的过掺杂在SiGe内靠近SiGe 10和衬底1之间的界面处形成了另一p-n结。
这可以通过两种方式来解决。首先，在该界面处设置另一个Si阻挡层14，以将扩散减少到一定水平使得SiGe保持为p型。（优选地，Si阻挡层6和14的厚度为7.5埃，或为3原子层。该限制为如前述的实施例，因为Si生长于晶格参数类似Ge的GaAs衬底。）
另一种避免该问题的方式是在执行后续加工步骤前，将SiGe转移到不同的衬底上。这种转移将在下文描述，并记载在我们的公布于2010年8月26日的公布号为WO2010094919的国际专利申请中，该国际专利申请通过引用的方式并入本文。
为此，可使用外延方法，使用含锗前体（例SiGe如GeH4、GeCl4等）和含硅前体（例如SiH4、SiH2Cl2、三氯氢硅、乙硅烷等）以及载气（如H2）的气体混合物，在GaAs衬底1上生长晶格匹配的SiGe层10。SiGe层10可以用p型掺杂剂进行原位掺杂，采用的气态或固态的掺杂源包括但不限于乙硼烷。层10可以在例如常压或者1托~1000托的减压和350°C~800°C的温度下生长。可以使用多种GaAs衬底，包括p型、n型和半绝缘型，而且晶片可以在外延前非原位地清洗或者在处理腔室内清洗。可以使用X射线衍射技术来测量SiGe层10的结晶度性质，例如检查晶格匹配，并且通常可以使用变角度椭偏光度法来监测层的厚度，但是也可以使用其他技术。
在该过程中，GaAs衬底和SiGe层10之间的材料组成变化提供了可作为良好蚀刻终止物的异质界面，使得GaAs衬底能够方便且精确地得到去除，从而留下SiGe层10的光滑表面。可以通过机械手段除去部分GaAs衬底，只要该机械手段可提供更快，或在其他方面更为便利或划算的制造方法。例如，如果GaAs衬底为500µm厚，其中约400µm可以通过磨光除去，通过该方法可以使得GaAs材料得以更容易地进行回收或再利用，且可以使用选择性湿法蚀刻来除去最终的100µm。
因为已经除去了衬底的厚度，使用这种方法得到的光伏电池结构体可具有较轻重量，这尤其在空间类应用中是重要的。有利的是，可以提供这样的替代性衬底，该衬底具有合适的弹性、热学性能或其它所需的机械或电气性能。用散热体来替代衬底能够从器件上更有效率地导热，因为衬底不再起到降低热流动的作用。该散热体或另一金属基体层可以直接起到至器件底部的传导电极的作用。
图10A - 10D示出了一种特定的技术。以GaAs衬底1开始，如图10A所示并如前文所述，外延生长SiGe层10。 然后使用层转移技术来除去除薄层外的全部GaAs衬底。该层转移可以使用专有剥离技术如SmartCut（RTM）或类似技术实现，其中在GaAs衬底中恰好位于SiGe层10的下方形成分离平面12。分离平面12可以使用离子束注入技术形成，以将氢原子或氦原子沉积在由束粒子能量确定的精确深度处，例如在深度可达1.5µm处，使得该技术在SiGe层的厚度接近此厚度时在现有情况下是实用的。
然后使替代性基体13与SiGe层10结合。如图10B所示，替代性基体可以是氧化的硅晶片，使得该SiGe层能够与SiO2层结合，但是还可使用诸如上述金属散热体层等其它基体。可使用的部分其它基体是金属、玻璃和半导体基体，其本身可以已经包含有两个以上选自金属、半导体和绝缘体材料的层，并且可以包括有源元件，如一个或多个光伏结。然后分离GaAs衬底的本体和上述结构体，并且例如通过如选择性湿法蚀刻除去少量剩余的GaAs层，以如图10C所示在诸如所述氧化的硅晶片等替代性基体上留下SiGe层10。随后可如图10D所示形成光伏器件的后续的各层，例如Si阻挡层6和III-V族层3以及后续的层5。
上述技术的一种变形是在下部SiGe层内恰好位于与衬底的界面上方处形成分离平面。在层转移后，被转移的SiGe已经露出，以进行必要的进一步制备。可至少部分地使用对SiGe有选择性而对GaAs无效的湿蚀刻（wet etch）来除去保留在GaAs衬底上的残余SiGe，以留下可再利用的GaAs衬底晶片。
多种不同的替代性基体可期望用于图10D中的结构体，包括金属、玻璃和半导体基体，其本身可以已经包含两个以上金属、半导体和绝缘体材料的层，并且可以包括有源元件，如一个或多个光伏结。在GaAs衬底上初始化形成的SiGe层为准确去除分离或剥离后的残余GaAs提供了理想的蚀刻终止物。
图11示出了使用本发明的多结太阳能电池的另一种实施例。其示出了具有五个元件的太阳能电池设备，再次地，所有元件为串叠连接。这些元件依次为衬底、Ge元件111、另一Ge元件112、GaInAs元件113、AlGaInAs 元件114和AlGaInP元件115（其覆盖有重度n型接触层116和金属线117）。在该设备中，本发明用于形成Ge元件112；其与在其上方的III-V族材料元件113相接于一界面，元件113提供了V族掺杂剂，因此元件112和113之间的界面处设置有Si扩散阻挡层6。
图11A详细示出了图11中的底部元件111、112的一种实施例，虽然当然其使用不限于图11的具体示例。
最低部的元件111具有p型IV族（如Ge）衬底1，其上生长n型IV族（如Ge）外延层，以形成第一p-n结。为使其与下一元件112相接触的阻抗低，随后沉积隧道二极管层16。在其顶部形成p型IV族材料（例如Ge）的外延层10，随后是硅扩散阻挡层6和III-V族外延层3，以便以上述各实施例的方式形成p-n结2，该结位于受从外延层3扩散穿过阻挡层6的 V族原子掺杂的外延层10的n型材料4和IV族层10的剩余部分之间，从而形成元件112。
图11B示出了类似于图11A的另一个实施例。然而，在该实施例中，第一元件不包括衬底，而是包括额外的生长于衬底1上的p型IV族外延层17（一般与衬底晶格匹配）以及生长于其上的n型IV族层15，二者形成第一元件的p-n结。
图11B所示实施例的一种具体示例中，衬底材料为GaAs（如图11B（和图11C）所标识）。然后，IV族层优选地为那些能够在衬底上按照基本上晶格匹配的方式生长的类型，例如为SiGe和SiGeSn。SiGe在与GaAs晶格匹配时的带隙为0.66eV，SiGeSn在与GaAs晶格匹配时的带隙大于0.66eV且可达~1.1eV。如果需要两个带隙大于0.66eV且保持与GaAs晶格匹配，那么最低部的元件111及下一元件112可以都由SiGeSn组成，但彼此具有不同组成，以提供期望的带隙。
图11C示出了类似于图11B的另一实施例，但在该实施例中，设置额外的Si扩散阻挡层14（像图9B的实施例），以防止当衬底是III-V材料（例如GaAs）时在IV族材料层17形成不必要的p-n结。
图11D示出了多结太阳能电池的另一实施例。结合图11B和11C的实施例，在GaAs衬底上设置第一SiGe或SiGeSn元件，在其上设置第二SiGeSn元件。在该实施例中，另外设置三个串叠的元件：在第二元件之上的第三GaAs元件，在第三元件之上的第四InGaP元件、以及在第四元件之上的第五AlGaAs或AlInGaP元件。所有的元件都与GaAs衬底晶格匹配。（虽然AlGaAs不具有与GaAs完全相同的晶格参数，但其几乎足够相等所以仍然晶格匹配，仅具有小的应变，其中AlGaAs层低于会发生为消除应力的位错的临界厚度。这适用于整个铝与镓的组成比例范围。该实施例中，其它材料具有与GaAs准确晶格匹配的组成，优选地使用这些组成。）一种举例中从第一到最后一个元件的带隙依次为：0.7eV、1.0eV、1.4eV、1.8eV、2.0eV。因此每个元件吸收照射在器件上的光的不同光谱部分。如果需要，该器件可以被提供为具有其它实施例中提及的Si阻挡层、隧道二极管、窗口层等。参照图10A至图10D所示，也可以除去衬底。另外，各元件的材料可以不生长于GaAs本身上，而是生长于另一与GaAs晶格匹配的衬底上。光吸收元件之间可以使用其他层，例如隧道二极管，并且优选地，这些层与这些元件晶格匹配，且优选地也与衬底晶格匹配。
图12示出了根据本发明的另一个方面的一种实施例中的各层。这里IV族10'和III-V族层3'之间的Si扩散阻挡层6限制了V族原子的通过阻挡层进入已经是n型的IV族材料的扩散，因此所产生的扩散区域4'为高n掺杂。在该实施例中，层3'和4'形成隧道二极管16。
图12所示实施例示出了与IV族光电管组合的隧道二极管（并且因此该实施例将使用于串叠光伏器件中）。提供p型IV族衬底1，在其上生长n型IV族外延层10'，其形成的结提供为光伏电池。在其上设置薄的Si扩散阻挡层6，且在阻挡层6上为III-V族材料的高度掺杂的层3'，其中的V族原子通过阻挡层扩散，以形成高度掺杂的n ++区域4'。在其上可以生长其它层5，例如其他的光伏电池，例如为III-V材料。高度掺杂n++ IV族区域4'和高度掺杂p++ III-V层3'形成低阻抗的隧道二极管16，从而允许由层1和10'之间的p-n结产生的光电流被无过度电阻损耗地引导到这些层上。
如前述的实施例，硅阻挡层不需要恰好位于IV族和III-V族材料之间的界面，但可以与其中的一侧相隔一定距离，并且该距离仍然可以影响V族原子的扩散。
在上述实施例中，各子元件可以替代地以相反的顺序生长在GaAs衬底上（或是与GaAs晶格匹配的衬底，或其它的与该结构体的晶格参数适配的衬底），以较宽带隙的元件开始，然后由带隙依次减小的元件结束，例如SiGe/SiGeSn元件。在最宽带隙的元件和衬底之间设置有牺牲层，允许去除该层元件，并转移到合适的载体或散热体，倒置以使最窄带隙的元件与衬底相邻，而最宽带隙的元件首先接收到入射光。
使用这些材料的器件一般为太阳能电池，其制备通常是首先提供具有必要的层的半导体材料，或者具有至少部分层的半导体材料。通常地，材料在整个半导体晶片上被均匀地制作。随后该材料被以光刻技术处理，以形成单独的设备并进行连接。通常是由从执行光刻和包装步骤的不同的制造商制造该材料。

Claims (17)

1.一种具有两个或更多由半导体材料形成的光吸收元件的多结光伏器件，包括：
第一硅锗或硅锗锡材料元件，
第二硅锗锡材料元件，
其中，所述第一硅锗或硅锗锡材料元件和所述第二硅锗锡材料元件与砷化镓晶格匹配。
2.如权利要求1所述的多结光伏器件，其特征在于，还包括砷化镓材料元件。
3.如权利要求1或2所述的多结光伏器件，其特征在于，还包括与砷化镓晶格匹配的磷化铟镓材料元件。
4.如权利要求1-3任一项所述的多结光伏器件，其特征在于，还包括与砷化镓晶格匹配的铝砷化镓材料元件。
5.如权利要求1-4任一项所述的多结光伏器件，其特征在于，还包括与砷化镓晶格匹配的磷化铝铟镓材料元件。
6.如权利要求1-5任一项所述的多结光伏器件，其特征在于包括砷化镓衬底，所述各元件的各半导体层位于所述衬底上并与所述衬底晶格匹配。
7.如权利要求1-6任一项所述的多结光伏器件，其特征在于包括与砷化镓晶格匹配的衬底，所述各半导体层位于所述衬底上并与所述衬底晶格匹配。
8.如权利要求1-7任一项所述的多结光伏器件，其特征在于，所述第一元件是硅锗材料制成。
9.如权利要求1-8任一项所述的多结光伏器件，其特征在于，所述多结光伏器件是太阳能电池。
10.一种制备多结光伏器件的方法，包括：
提供砷化镓衬底或者是与砷化镓晶格匹配的另一种材料的衬底，
生长与所述衬底晶格匹配的第一硅锗或硅锗锡材料元件，
生长与所述第一光吸收元件晶格匹配的第二硅锗锡材料元件。
11.如权利要求10所述的方法，其特征在于包括生长砷化镓材料元件。
12.如权利要求10或11所述方法，其特征在于包括生长与砷化镓晶格匹配的磷化铟镓元件。
13.如权利要求10-12任一项所述的方法，其特征在于包括生长与砷化镓晶格匹配的铝砷化镓元件。
14.如权利要求10-12任一项所述的方法，其特征在于包括生长与砷化镓晶格匹配的磷化铝铟镓元件。
15.如权利要求10-14任一项所述的方法，其特征在于包括在两个相邻的所述元件之间设置至少一个另外的层，所述至少一个另外的层与砷化镓晶格匹配。
16.如权利要求10-15任一项所述的方法，其特征在于包括去除所述衬底。
17.如权利要求10-16任一项所述的方法，其特征在于，所述第一元件是硅锗材料制成。
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