CN107845685A - The UMOS device architectures and preparation method of a kind of low gate-source capacitance - Google Patents
The UMOS device architectures and preparation method of a kind of low gate-source capacitance Download PDFInfo
- Publication number
- CN107845685A CN107845685A CN201711064656.XA CN201711064656A CN107845685A CN 107845685 A CN107845685 A CN 107845685A CN 201711064656 A CN201711064656 A CN 201711064656A CN 107845685 A CN107845685 A CN 107845685A
- Authority
- CN
- China
- Prior art keywords
- grid
- type
- oxygen
- polysilicon
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 55
- 239000001301 oxygen Substances 0.000 claims abstract description 55
- 229920005591 polysilicon Polymers 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 238000000407 epitaxy Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000012010 growth Effects 0.000 claims abstract description 11
- 238000012545 processing Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 19
- 230000008859 change Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The present invention relates to a kind of UMOS device architectures of low gate-source capacitance and preparation method, the structure includes：N-type substrate；It is arranged at the N-type epitaxy layer on the N-type substrate surface；It is arranged at the PXing Ti areas on the N-type epitaxy layer surface；It is arranged at the N+ type source regions of the p-type body surface；Groove through the N+ types source region and PXing Ti areas and in N-type epitaxy layer；It is grown on the bottom thickness oxygen grid of channel bottom；The bottom thickness oxygen grid are located in N-type epitaxy layer；The side wall grid oxygen being grown on bottom Hou Yangshan surfaces and trenched side-wall；It is formed at side wall grid oxygen surface and is filled in the polysilicon in groove；Both sides form grid structure by etching at the top of polysilicon；It is grown on side wall grid oxygen surface and is filled in the side thickness grid oxygen for the polysilicon segment being etched.The present invention on the basis of traditional UMOS flows processing step, need to only increase polysilicon etch again with two processing steps of side thickness gate oxide growth, just significantly reduce UMOS gate-source capacitance.
Description
Technical field
The invention belongs to IC design field, it is related to UMOS device architectures and the preparation side of a kind of low gate-source capacitance
Method.
Background technology
VDMOS device is widely used in fields such as power management module, motor controls.Compared to plane VDMOS structures,
Groove grid VDMOS (UMOS) can effectively eliminate the JFET areas resistance below grid, so that in mesolow device more widely
Use.The UMOS devices management conversion device important as switching component, its intrinsic capacity and parasitic capacitance directly affect
The switching loss of device.Because UMOS devices have higher grid area, therefore its gate capacitance also can be larger, optimization gate capacitance into
A big important subject is lost to reduce devices switch.The method of traditional reduction electric capacity is by reducing between grid leak
Electric capacity between electric capacity or grid and base is realized.By taking N-type UMOS as an example, have at present by disconnecting polysilicon strip and disconnecting
Certain p type island region is injected to change the method for depletion layer shape by place, or is injected by high energy particle and obtain end grid structure so as to subtract
The method of small effectively polysilicon length reduces gate-source capacitance.But these methods can not effectively reduce grid and N+ heavy-doped sources
The electric capacity of area's overlapping part.
The content of the invention
In order to overcome above mentioned problem, the present invention provides UMOS device architectures and the preparation that the present invention is a kind of low gate-source capacitance
Method, its object is to by increasing grid and N+ heavy doping source region overlapping part oxide thickness, to reduce the grid of UMOS devices
Source electric capacity.
An object of the present invention is achieved by the following technical solution：A kind of UMOS device junctions of low gate-source capacitance
Structure, including
N-type substrate 101；
It is arranged at the N-type epitaxy layer 102 on the N-type substrate surface；
It is arranged at the PXing Ti areas 103 on the N-type epitaxy layer surface；
It is arranged at the N+ type source regions of the p-type body surface；
Groove through the N+ types source region and PXing Ti areas and in N-type epitaxy layer；
It is grown on the bottom thickness oxygen grid 201 of channel bottom；The bottom thickness oxygen grid are located in N-type epitaxy layer；
The side wall grid oxygen 202 being grown on bottom Hou Yangshan surfaces and trenched side-wall；
The polysilicon 203 for being formed at side wall grid oxygen surface and being filled in groove；Both sides are by etching shape at the top of polysilicon
Into grid structure；
It is grown on side wall grid oxygen surface and is filled in the side thickness grid oxygen 205 for the polysilicon segment 204 being etched.
Further, the depth of two grooves is identical with N+ type source regions.
Further, the width of the groove is 100~120nm, and depth is 30~40nm.
Further, the thickness of the bottom thickness oxygen grid is 100~200nm.
Further, the thickness of the side wall grid oxygen is 60~80nm.
Further, the width of the grid structure is 280~320nm.
The second object of the present invention is achieved by the following technical solution, a kind of UMOS device junctions of low gate-source capacitance
The preparation method of structure, comprises the following steps
N-type substrate 101 is provided；
On the N-type substrate surface, N-type epitaxy layer 102 is set；
On the N-type epitaxy layer surface, PXing Ti areas 103 are set；
In the p-type body surface, N+ types source region 104 is set；
N+ types source region, PXing Ti areas and the N-type epitaxy layer are performed etching to be formed through whole N+ types source region, PXing Ti areas
And the groove in N-type epitaxy layer；
In the bottom grown bottom thickness grid oxygen 201 of groove, bottom thickness grid oxygen is located in N-type epitaxy layer；
Side wall grid oxygen 202 is grown on the surface of bottom thickness grid oxygen and trenched side-wall；
Polysilicon 203 is set on the surface of side wall grid oxygen, and the polysilicon is filled in groove；
Both sides at the top of polysilicon are performed etching to form grid structure；
Side thickness grid oxygen 205 is grown in the polysilicon segment 204 being etched.
As a result of above technical scheme, the present invention has following advantageous effects：
On the basis of traditional UMOS flows processing step, it only need to increase polysilicon and etch again and side thickness gate oxide growth
Two processing steps, just significantly reduce UMOS gate-source capacitance.
Brief description of the drawings
In order that the object, technical solutions and advantages of the present invention are clearer, the present invention is made below in conjunction with accompanying drawing into
The detailed description of one step, wherein：
Fig. 1 is the growth figure of bottom thickness grid oxygen；
Fig. 2 is the growth figure of side wall grid oxygen after the thickness gate oxide growth of bottom；
Fig. 3 is injection and the etching of polysilicon, forms grid structure；
Fig. 4 is polysilicon top etch；
Fig. 5 is the regrowth of etched portions grid oxygen, forms side thickness gate oxygen structure figure；
Fig. 6 is the gate-source capacitance simulated under traditional UMOS techniques；
Fig. 7 is the gate-source capacitance simulated under side thickness grid oxygen technique；
Component label instructions
101.N+ type substrates, 102.N type epitaxial layers, 103.P Xing Ti areas, 104.N+ type source regions, 201. bottom thickness grid oxygens,
202. side wall grid oxygens, 203. polysilicons, 204. polysilicon segments being etched, 205. side thickness grid oxygens.
Embodiment
Below with reference to accompanying drawing, the preferred embodiments of the present invention are described in detail；It should be appreciated that preferred embodiment
Only for the explanation present invention, the protection domain being not intended to be limiting of the invention.
Embodiment one
The gate capacitance of basic MOS structure is equal with the gate oxide situation under accumulation condition,
εOXFor the dielectric constant of semiconductor, tOXGate oxide thickness.Capacitance size inverse ratio is with gate oxide thickness in anti-
Than.
The characteristic input capacitance of N-channel UMOS devices is represented by：
xGNFor grid and N+The overlapping part oxide width of type source region, xGPFor grid and the overlapping part oxygen of p-type base
Change slice width degree, WCELLFor cellular width, WGFor grid width, tOXNFor grid and N+Type source region overlapping part oxidated layer thickness, tOXP
For grid and PXing Ti areas overlapping part oxidated layer thickness, tIEOXFor electrode insulation oxidated layer thickness in gate oxide thickness.
On grid source plus a malleation for exceeding device cut-in voltage, device are in the conduction state.Add one in drain-source
Positive bias, just form the electric current from drain-to-source flowing.At this moment, in grid and source electrode, grid is with draining, source electrode and leakage
Just multiple electric capacity are formed between pole.Wherein, gate capacitance is mainly by gate electrode and N+The overlapping part in type source region and PXing Ti areas is determined
It is fixed, and N+Type source region and PXing Ti areas are high-dopant concentration, can the approximate electric capacity determined by oxidation layer capacitance, and capacitance size
It is in inverse ratio with gate oxide thickness.Therefore, spirit of the invention is, by increasing grid and N+Type source region overlapping part aoxidizes thickness
Spend tOXNMethod reduce CN+, so as to reach the purpose for reducing gate-source capacitance.
To achieve the above object, the present invention provides the UMOS device architectures of new low gate-source capacitance, including
N-type substrate 101；
It is arranged at the N-type epitaxy layer 102 on the N-type substrate surface；
It is arranged at the PXing Ti areas 103 on the N-type epitaxy layer surface；
It is arranged at the N+ type source regions of the p-type body surface；
Groove through the N+ types source region and PXing Ti areas and in N-type epitaxy layer；
It is grown on the bottom thickness oxygen grid 201 of channel bottom；The bottom thickness oxygen grid are located in N-type epitaxy layer；
The side wall grid oxygen 202 being grown on bottom Hou Yangshan surfaces and trenched side-wall；
The polysilicon 203 for being formed at side wall grid oxygen surface and being filled in groove；Both sides are by etching shape at the top of polysilicon
Into grid structure；
It is grown on side wall grid oxygen surface and is filled in the side thickness grid oxygen 205 for the polysilicon segment 204 being etched.
Further, the depth of two grooves is identical with N+ type source regions.
Further, the width of the groove is 100~120nm, and depth is 30~40nm.
Further, the thickness of the bottom thickness oxygen grid is 100~200nm.
Further, the thickness of the side wall grid oxygen is 60~80nm.
Further, the width of the grid structure is 280~320nm.
In the present embodiment, selected device substrate is the N+ type substrates of heavy doping, and described drift region drifts about for N-type
Area, described body area are PXing Ti areas, and described source region is the N+ type source regions of heavy doping.Certainly, the device selected by the present invention is served as a contrast
Bottom, drift region, the doping type of body area and source region are not limited to this.
Embodiment two
The present invention also provides a kind of UMOS device preparation methods of low gate-source capacitance, and this method is in traditional UMOS flows technique
On the basis of step, only it need to increase by two processing steps, you can be effectively reduced the input capacitance of device, optimize time parameter.
This method processing step simply easily realizes, and reliable and stable.As shown in Fig. 1~5, this method specifically includes following steps：
N-type substrate 101 is provided；
On the N-type substrate surface, N-type epitaxy layer 102 is set；
On the N-type epitaxy layer surface, PXing Ti areas 103 are set；
In the p-type body surface, N+ types source region 104 is set；
N+ types source region, PXing Ti areas and the N-type epitaxy layer are performed etching to be formed through whole N+ types source region, PXing Ti areas
And the groove in N-type epitaxy layer；
In the bottom grown bottom thickness grid oxygen 201 of groove, bottom thickness grid oxygen is located in N-type epitaxy layer；
Side wall grid oxygen 202 is grown on the surface of bottom thickness grid oxygen and trenched side-wall；
Polysilicon 203 is set on the surface of side wall grid oxygen, and the polysilicon is filled in groove；
Both sides at the top of polysilicon are performed etching to form grid structure；
Side thickness grid oxygen 205 is grown in the polysilicon segment 204 being etched.
In the present embodiment, in etching polysilicon, etching width is 100~120nm.Certainly, to device selected by the present invention
The etching polysilicon width not limited to this of part.
As an example, the present invention uses the phosphorus substrate (the Ω cm of resistivity 0.002, crystal orientation 100) of heavy doping, it is lightly doped
Phosphorus extension (the Ω cm of resistivity 1.6,6 μm of thickness), the PXing Ti areas (B doping) of heavy doping, and the N+ type source regions (P of heavy doping
Doping).
As shown in figure 1, after completing etching groove, the growth of bottom thickness grid oxygen is carried out first, growth thickness is about 100~
200nm。
As shown in Fig. 2 after the completion of the thickness gate oxide growth of bottom, the growth of side wall gate oxide is carried out, thickness is 60~80nm.
As shown in figure 3, after the completion of side wall gate oxide growths, the injection deposition and etching of polysilicon are carried out, forms grid structure,
Polysilicon gate width is 280~320nm.
As shown in figure 4, being performed etching to polysilicon, high etch is extremely consistent with N+ type source regions, is 280~320nm, etching
Width is 100~120nm.
As shown in figure 5, carrying out the regrowth of gate oxide at the polysilicon etched, side thickness gate oxygen structure is formed.
The present invention is emulated using 60V N-channel UMOS, and cellular width is 2 μm.Simulation analysis are emulated using TCAD
Instrument, but it is not limited to this for the emulation tool of the present invention.
In the present embodiment, the test condition of gate-source capacitance is in Fig. 6 and Fig. 7：VGS=12V.Certainly, to selected by the present invention
Gate-source capacitance test condition not limited to this.
As shown in fig. 6, the electric capacity emulation carried out under traditional UMOS techniques etching technics, gate-source capacitance are up to CGS=
2.27e15F/μm。
As shown in fig. 7, the electric capacity emulation carried out under side thickness grid oxygen technique under the present invention, gate-source capacitance are up to CGS
=1.97e15F/ μm.
As an example, the present invention in traditional UMOS structures, by increasing by two processing steps, i.e., optimizes gate-source capacitance
About 13.2%.
Present invention process is simple and easy, and implementation degree is high, and new UMOS structures understand simply, reliable and stable, easily realizes.It is logical
The present invention is crossed, has effectively filled up in traditional UMOS techniques and has lacked the vacancy of capacitive method between optimization grid and N+ source regions, passed through height
The gate-source capacitance that feasible process significantly reduces UMOS is spent, the time parameter of device can be improved, the production with height
Industry value.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, it is clear that those skilled in the art
Member can carry out various changes and modification without departing from the spirit and scope of the present invention to the present invention.So, if the present invention
These modifications and variations belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to include these
Including change and modification.
Claims (7)
- A kind of 1. UMOS device architectures of low gate-source capacitance, it is characterised in that：IncludingN-type substrate (101)；It is arranged at the N-type epitaxy layer (102) on the N-type substrate surface；It is arranged at the PXing Ti areas (103) on the N-type epitaxy layer surface；It is arranged at the N+ type source regions of the p-type body surface；Groove through the N+ types source region and PXing Ti areas and in N-type epitaxy layer；It is grown on the bottom thickness oxygen grid (201) of channel bottom；The bottom thickness oxygen grid are located in N-type epitaxy layer；The side wall grid oxygen (202) being grown on bottom Hou Yangshan surfaces and trenched side-wall；It is formed at side wall grid oxygen surface and is filled in the polysilicon in groove (203)；Both sides are formed by etching at the top of polysilicon Grid structure；It is grown on side wall grid oxygen surface and is filled in the side thickness grid oxygen (205) for the polysilicon segment (204) being etched.
- A kind of 2. UMOS device architectures of low gate-source capacitance according to claim 1, it is characterised in that：The depth of two grooves It is identical with N+ type source regions.
- A kind of 3. UMOS device architectures of low gate-source capacitance according to claim 1, it is characterised in that：The width of the groove It is 30~40nm to spend for 100~120nm, depth.
- A kind of 4. UMOS device architectures of low gate-source capacitance according to claim 1, it is characterised in that：The bottom thickness oxygen The thickness of grid is 100~200nm.
- A kind of 5. UMOS device architectures of low gate-source capacitance according to claim 1, it is characterised in that：The side wall grid oxygen Thickness be 60~80nm.
- A kind of 6. UMOS device architectures of low gate-source capacitance according to claim 1, it is characterised in that：The grid structure Width be 280~320nm.
- A kind of 7. preparation method of the UMOS device architectures of low gate-source capacitance, it is characterised in that：Comprise the following stepsN-type substrate (101) is provided；On the N-type substrate surface, N-type epitaxy layer (102) is set；On the N-type epitaxy layer surface, PXing Ti areas (103) are set；In the p-type body surface, N+ types source region (104) is set；N+ types source region, PXing Ti areas and the N-type epitaxy layer are performed etching to be formed through whole N+ types source region, PXing Ti areas and position In the groove in N-type epitaxy layer；In the bottom grown bottom thickness grid oxygen (201) of groove, bottom thickness grid oxygen is located in N-type epitaxy layer；Side wall grid oxygen (202) is grown on the surface of bottom thickness grid oxygen and trenched side-wall；Polysilicon (203) is set on the surface of side wall grid oxygen, and the polysilicon is filled in groove；Both sides at the top of polysilicon are performed etching to form grid structure；In polysilicon segment (204) the growth side thickness grid oxygen (205) being etched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711064656.XA CN107845685A (en) | 2017-11-02 | 2017-11-02 | The UMOS device architectures and preparation method of a kind of low gate-source capacitance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711064656.XA CN107845685A (en) | 2017-11-02 | 2017-11-02 | The UMOS device architectures and preparation method of a kind of low gate-source capacitance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107845685A true CN107845685A (en) | 2018-03-27 |
Family
ID=61682300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711064656.XA Pending CN107845685A (en) | 2017-11-02 | 2017-11-02 | The UMOS device architectures and preparation method of a kind of low gate-source capacitance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107845685A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114914295A (en) * | 2022-06-30 | 2022-08-16 | 电子科技大学 | UMOS device with excellent forward and reverse conduction characteristics |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090072306A1 (en) * | 2007-09-03 | 2009-03-19 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| US20090078995A1 (en) * | 2007-09-20 | 2009-03-26 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN103839791A (en) * | 2012-11-21 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Preparation method for trench gate of trench type MOS device |
-
2017
- 2017-11-02 CN CN201711064656.XA patent/CN107845685A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090072306A1 (en) * | 2007-09-03 | 2009-03-19 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| US20090078995A1 (en) * | 2007-09-20 | 2009-03-26 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN103839791A (en) * | 2012-11-21 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Preparation method for trench gate of trench type MOS device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114914295A (en) * | 2022-06-30 | 2022-08-16 | 电子科技大学 | UMOS device with excellent forward and reverse conduction characteristics |
| CN114914295B (en) * | 2022-06-30 | 2023-05-02 | 电子科技大学 | UMOS device with excellent forward and reverse conduction characteristics |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9240469B2 (en) | Transverse ultra-thin insulated gate bipolar transistor having high current density | |
| CN102769037B (en) | Structure for reducing surface electric field and LDMOS device | |
| CN104064475A (en) | High Mobility Power Metal-oxide Semiconductor Field-effect Transistors | |
| CN107123684A (en) | One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor | |
| CN104658901A (en) | Preparation method for split gate trench MOSFET(metal-oxide-semiconductor-field-effect-transistor) | |
| CN107785411A (en) | It is integrated with the device and its manufacture method of junction field effect transistor | |
| CN103515443B (en) | A kind of super junction power device and manufacture method thereof | |
| US20020017682A1 (en) | Semiconductor device | |
| CN105304693B (en) | A kind of manufacturing method of LDMOS device | |
| CN204905261U (en) | Withstand voltage structure of horizontal power device of SOI | |
| CN108389895A (en) | Integrated power device based on superjunction and its manufacturing method | |
| CN107845685A (en) | The UMOS device architectures and preparation method of a kind of low gate-source capacitance | |
| CN109698196B (en) | Power semiconductor device | |
| CN104518008B (en) | A kind of technotron | |
| CN203707141U (en) | Integrated finger-gate vertical-channel SOI LDMOS unit | |
| CN115663030A (en) | Silicon carbide power device and switching device | |
| CN112466955B (en) | Thin-layer SOI-LDMOS device with in-vivo conductive channel | |
| CN112420846B (en) | Transverse super-junction thin-layer SOI-LDMOS device with surface and body double channels | |
| CN104518027A (en) | LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN108054194A (en) | A kind of semiconductor devices Withstand voltage layer with three-dimensional variety lateral doping | |
| KR101685572B1 (en) | SiC MOSFET for decreasing electric field of bottom oxide and method for manufacturing thereof | |
| CN108258040A (en) | Igbt with wide band gap semiconducter substrate material and preparation method thereof | |
| CN103700701B (en) | The floating front gate P-MOSFET RF switching devices in backgate leakage/source based on SOI technology half | |
| Chen et al. | Study of 4H–SiC trench MOSFET structures | |
| CN103762237A (en) | Transverse power device with field plate structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20210115 Address after: 400060 Chongqing Nanping Nan'an District No. 14 Huayuan Road Applicant after: The 24th Research Institute of China Electronics Technology Group Corp. Address before: 401332 367, West Wing Road, Xiyong Town, Shapingba District, Chongqing Applicant before: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION CHONGQING ACOUSTIC-OPTIC-ELECTRONIC Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180327 |
|
| RJ01 | Rejection of invention patent application after publication |