CN115663030A - Silicon carbide power device and switching device - Google Patents
Silicon carbide power device and switching device Download PDFInfo
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- CN115663030A CN115663030A CN202211587488.3A CN202211587488A CN115663030A CN 115663030 A CN115663030 A CN 115663030A CN 202211587488 A CN202211587488 A CN 202211587488A CN 115663030 A CN115663030 A CN 115663030A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a silicon carbide power device and a switching device. The silicon carbide power device comprises at least one unit cell, wherein the unit cell comprises a substrate, and a drain electrode is positioned on a first surface of the substrate; the epitaxial layer is positioned on the second surface of the substrate; the gate dielectric layer is positioned on the surface of the epitaxial layer far away from the substrate; the grid electrode is positioned on the surface of the grid dielectric layer far away from the epitaxial layer; the grid dielectric layer comprises a first insulation region and a second insulation region, the silicon carbide power device is in a turn-off state, when the applied voltage is larger than a preset high voltage, the electric field peak value of the grid dielectric layer is located in the second insulation region, and the product of the safe electric field intensity and the dielectric constant of the second insulation region is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulation region. The technical scheme provided by the embodiment of the invention improves the breakdown voltage of the silicon carbide power device, and can reduce the on-resistance of the silicon carbide power device by using the epitaxial layer with higher doping concentration or the junction field effect transistor region with larger width.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a silicon carbide power device and a switch device.
Background
Silicon Carbide (SiC) power devices have become one of the most feasible candidates for next-generation power semiconductor devices due to their low on-resistance characteristics and excellent high-temperature, high-frequency, and high-voltage properties, compared to conventional Silicon devices. In addition, the silicon carbide power device can reduce the use of system elements for system designers, thereby further reducing the complexity and cost of system design. Meanwhile, the silicon carbide power device is beneficial to obviously reducing the energy consumption of equipment, thereby being beneficial to designing environment-friendly products and systems capable of reducing carbon emission.
For silicon carbide power devices, breakdown voltage and on-resistance are two most important static parameters, and it is generally desirable that the devices have higher breakdown voltage and lower on-resistance, but this is a contradiction in design.
In the prior art, on-resistance of the silicon carbide power device cannot be reduced by using an epitaxial layer with higher doping concentration or a Junction Field-Effect Transistor (JFET) region with larger width on the basis of improving breakdown voltage of the silicon carbide power device.
Disclosure of Invention
The invention provides a silicon carbide power device and a switch device, which are used for reducing the on-resistance of the silicon carbide power device by using an epitaxial layer with higher doping concentration or a junction field effect transistor region with larger width on the basis of improving the breakdown voltage of the silicon carbide power device.
According to an aspect of the present invention, there is provided a silicon carbide power device including at least one cell,
the unit cell comprises a substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged;
the drain electrode is positioned on the first surface of the substrate;
the epitaxial layer is positioned on the second surface of the substrate;
the epitaxial layer is provided with a drift region, a first body region, a junction field effect transistor region and a second body region, the first body region is provided with a first source region, and the second body region is provided with a second source region;
the gate dielectric layer is positioned on the surface of the epitaxial layer far away from the substrate;
the grid electrode is positioned on the surface of the grid dielectric layer far away from the epitaxial layer;
the gate dielectric layer comprises a first insulating region and a second insulating region, the silicon carbide power device is in a turn-off state, when an applied voltage is higher than a preset high voltage, the electric field peak value of the gate dielectric layer is located in the second insulating region, and the product of the safe electric field intensity and the dielectric constant of the second insulating region is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region.
Optionally, the electric field strength of the second insulating region is greater than the safe electric field strength of the first insulating region.
Optionally, the first insulating region includes a first sub insulating region and a second sub insulating region, and the second insulating region is located between the first sub insulating region and the second sub insulating region in a direction perpendicular to a direction in which the gate dielectric layer points to the epitaxial layer.
Optionally, an orthographic projection of the second insulating region on the epitaxial layer and an orthographic projection of the first body region on the epitaxial layer are not overlapped;
the orthographic projection of the second insulation region on the epitaxial layer and the orthographic projection of the second body region on the epitaxial layer are not overlapped.
Optionally, the dielectric constant of the second insulating region is greater than the dielectric constant of the first insulating region.
Optionally, the thickness of the second insulating region is greater than the thickness of the first insulating region.
Optionally, the thickness of the second insulating region is equal to the thickness of the first insulating region.
Optionally, the material of the first insulating region is silicon dioxide.
Optionally, the gate dielectric layer covers a portion of the first body region, a portion of the first source region, the junction field effect transistor region, a portion of the second body region, and a portion of the second source region.
According to another aspect of the present invention there is provided a switching device comprising a silicon carbide power device as described in any of the above embodiments.
According to the technical scheme provided by the embodiment, when the silicon carbide power device is in a turn-off state and the applied voltage is greater than the preset high voltage, the product of the safe electric field intensity and the dielectric constant of the second insulating region (the region where the electric field peak value is located, namely, the region which is most easily punctured) is set to be greater than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region, namely, the voltage endurance capability of the region which is most easily punctured is improved, the breakdown voltage of the silicon carbide power device is further improved, and meanwhile, the problem of reliability of the gate dielectric layer can be avoided. In this embodiment, the on-resistance of the silicon carbide power device may also be reduced by using an epitaxial layer with a higher doping concentration (including a drift region, a first body region, a junction field effect transistor region, a second body region, a first source region, and a second source region with a higher doping concentration) or a junction field effect transistor region with a larger width. It should be noted that the breakdown voltage of the silicon carbide power device can be greatly increased by setting the product of the safe electric field strength and the dielectric constant of the second insulating region (the region where the electric field peak value is located, i.e., the region which is most easily broken down) to be greater than the product of the breakdown electric field strength and the dielectric constant of the first insulating region, and then the value of the breakdown voltage reduction of the silicon carbide power device caused by reducing the on-resistance of the silicon carbide power device by using the epitaxial layer with higher doping concentration or the junction field effect transistor region with larger width can be disregarded. And compared with devices such as a traditional Si-Insulated Gate Bipolar Transistor (IGBT), the silicon carbide power device has a faster switching speed, so that the switching loss of the device is smaller. However, higher voltage change rates (higher values of dv/dt) and higher values of current change rates (higher values of di/dt) present the problem of being more sensitive to parasitic parameters. For the dynamic parameter index of the silicon carbide power device, the parasitic capacitance, especially the gate-to-drain capacitance (Cgd), will have adverse effects on the misconduction of the silicon carbide power device. According to the technical scheme provided by the embodiment, the product of the safe electric field intensity and the dielectric constant of the second insulating region (the region where the electric field peak value is located, namely the region which is most easily punctured) is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region, so that the voltage endurance capacity of the region which is most easily punctured is improved, the gate leakage capacitance (Cgd) of the silicon carbide power device can be reduced in a certain range, and further the parasitic capacitance of the silicon carbide power device is reduced.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a silicon carbide power device provided in accordance with an embodiment of the present invention;
figure 2 is a schematic diagram of another silicon carbide power device provided in accordance with an embodiment of the present invention;
fig. 3 is a schematic diagram of a structure of another silicon carbide power device provided in accordance with an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In order to reduce the on-resistance of the silicon carbide power device by using an epitaxial layer with higher doping concentration or a junction field effect transistor region with larger width on the basis of improving the breakdown voltage of the silicon carbide power device, the embodiment of the invention provides the following technical scheme:
referring to fig. 1, fig. 1 is a schematic structural diagram of a silicon carbide power device provided according to an embodiment of the present invention, the silicon carbide power device including at least one cell, in which two cells are exemplarily shown, each cell including a substrate 001, the substrate 001 including a first surface 1a and a second surface 1b disposed opposite to each other; a drain electrode 002, the drain electrode 002 being located at the first surface 1a of the substrate 001; an epitaxial layer 003, the epitaxial layer 003 being located at the second surface 1b of the substrate 001; the epitaxial layer 003 is provided with a drift region 30, a first body region 31, a junction field effect transistor region 32 and a second body region 33, the first body region 31 is provided with a first source region 34, and the second body region 33 is provided with a second source region 35; the gate dielectric layer 004 is positioned on the surface of the epitaxial layer 003 far away from the substrate 001; the grid electrode 005 is positioned on the surface of the grid dielectric layer 004 away from the epitaxial layer 003; the gate dielectric layer 004 comprises a first insulating region 40 and a second insulating region 41, the silicon carbide power device is in an off state, when an applied voltage is higher than a preset high voltage, an electric field peak value of the gate dielectric layer 004 is located in the second insulating region 41, and a product of a safe electric field intensity and a dielectric constant of the second insulating region 41 is larger than a product of a breakdown electric field intensity and the dielectric constant of the first insulating region 40.
For silicon carbide power devices, the limiting factor for breakdown voltage is the electric field strength at the gate dielectric layer 004. Illustratively, when the gate dielectric layer 004 is made of silicon dioxide, the electric field strength in the gate dielectric layer 004 can be increased to 2.5 times of the initial electric field strength along with the increase of the turn-off voltage, and finally the peak value of the electric field strength of the gate dielectric layer 004 can even exceed the bearable complete electric field strength (4 MV/cm) of the silicon dioxide for maintaining the long-term reliability, so that the reliability of the silicon carbide power device is problematic.
In this embodiment, through finite element analysis, when the sic power device is in an off state and the applied voltage is greater than the preset high voltage, the gate dielectric layer 004 has a region where the electric field peak exists, and the region where the electric field peak exists is the region most likely to be broken down. In the present embodiment, a region where the electric field peaks is referred to as a second insulating region 41, and the remaining region is referred to as a first insulating region 40.
According to the technical scheme provided by the embodiment, when the silicon carbide power device is in a turn-off state and the applied voltage is greater than the preset high voltage, the product of the safe electric field intensity and the dielectric constant of the second insulating region 41 (the region where the electric field peak value is located, namely, the region which is most easily punctured) is set to be greater than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region 40, namely, the voltage withstanding capability of the region which is most easily punctured is improved, further, the breakdown voltage of the silicon carbide power device is improved, and meanwhile, the problem of reliability of the gate dielectric layer 004 can be avoided. And in this embodiment, the on-resistance of the silicon carbide power device can also be reduced by using the epitaxial layer 003 (including the drift region 30, the first body region 31, the junction field effect transistor region 32, the second body region 33, the first source region 34, and the second source region 35 of higher doping concentration) or the junction field effect transistor region 32 of larger width. It should be noted that the breakdown voltage of the sic power device can be greatly increased by setting the product of the safe electric field strength and the dielectric constant of the second insulating region 41 (the region where the electric field peak is located, i.e., the region most likely to be broken down) to be greater than the product of the breakdown electric field strength and the dielectric constant of the first insulating region 40, and thus, the value of the breakdown voltage reduction of the sic power device due to the reduction of the on-resistance of the sic power device by using the epitaxial layer 003 with a higher doping concentration or the jfet region 32 with a larger width can be disregarded. And compared with the traditional devices such as the Si-IGBT, the silicon carbide power device has higher switching speed, so that the switching loss of the device is smaller. However, higher voltage change rates (higher values of dv/dt) and higher values of current change rates (higher values of di/dt) present the problem of being more sensitive to parasitic parameters. For the dynamic parameter index of the silicon carbide power device, the parasitic capacitance, especially the gate-to-drain capacitance (Cgd), will have adverse effects on the misconduction of the silicon carbide power device. According to the technical scheme provided by the embodiment, the product of the safe electric field intensity and the dielectric constant of the second insulating region 41 (the region where the electric field peak value is located, namely the region which is most easily punctured) is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region 40, so that the withstand voltage of the region which is most easily punctured is improved, the gate leakage capacitance (Cgd) of the silicon carbide power device can be reduced within a certain range, and the parasitic capacitance of the silicon carbide power device is further reduced.
Optionally, on the basis of the above technical solution, as shown in fig. 1, the electric field intensity of the second insulating region 41 is greater than the safe electric field intensity of the first insulating region 40.
With the increase of the turn-off voltage, on the basis that the product of the safe electric field intensity and the dielectric constant of the second insulating region 41 (the region where the electric field peak value is located, namely, the region which is most easily punctured) is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region 40, the electric field intensity of the second insulating region 41 is set to be larger than the safe electric field intensity of the first insulating region 40, so that the voltage endurance capability of the region which is most easily punctured can be further improved, the breakdown voltage of the silicon carbide power device is further improved, and meanwhile, the problem of reliability of the gate dielectric layer 004 can be avoided. The on-resistance of the silicon carbide power device may also be reduced by using a higher doping concentration epitaxial layer 003 (including higher doping concentration drift region 30, first body region 31, junction field effect transistor region 32, second body region 33, first source region 34, and second source region 35) or a wider width junction field effect transistor region 32. And the voltage endurance capability of the area which is most easy to break down is improved, and the gate-to-drain capacitance (Cgd) of the silicon carbide power device can be reduced within a certain range, so that the parasitic capacitance of the silicon carbide power device is reduced.
Alternatively, on the basis of the above technical solution, as shown in fig. 2, fig. 2 is a schematic structural diagram of another silicon carbide power device provided according to an embodiment of the present invention, where the first insulating region 40 includes a first sub-insulating region 40a and a second sub-insulating region 40b, and the second insulating region 41 is located between the first sub-insulating region 40a and the second sub-insulating region 40b in a direction perpendicular to the gate dielectric layer 004 and pointing to the epitaxial layer 003.
Through finite element analysis, when the silicon carbide power device is in an off state and the applied voltage is greater than a preset high voltage, the gate dielectric layer 004 has a region where the electric field peak value is located, and the region where the electric field peak value is located is the region which is most easily broken down. Through analysis, the region where the electric field peak is located in the middle region of the gate dielectric layer 004, namely the second insulating region 41.
Optionally, on the basis of the above technical solutions, as shown in fig. 1 and fig. 2, an orthographic projection of the second insulating region 41 on the epitaxial layer 003 and an orthographic projection of the first body region 31 on the epitaxial layer do not overlap; the orthographic projection of the second insulation regions 41 in the epitaxial layer 003 and the orthographic projection of the second body regions 33 in the epitaxial layer do not overlap.
Through finite element analysis, when the silicon carbide power device is in an off state and the applied voltage is greater than a preset high voltage, the gate dielectric layer 004 has a region where the electric field peak value is located, and the region where the electric field peak value is located is the region which is most easily broken down. Through analysis, the orthographic projection of the region where the electric field peak value is located on the epitaxial layer 003 is not overlapped with the orthographic projection of the first body region 31 on the epitaxial layer, and the orthographic projection of the region where the electric field peak value is located on the epitaxial layer 003 is not overlapped with the orthographic projection of the second body region 33 on the epitaxial layer.
Optionally, on the basis of the above technical solution, as shown in fig. 1 and fig. 2, the dielectric constant of the second insulating region 41 is greater than the dielectric constant of the first insulating region 40.
Specifically, on the basis that the product of the safe electric field intensity and the dielectric constant of the second insulating region 41 (the region where the electric field peak value is located, that is, the region which is most easily punctured) is greater than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region 40, the dielectric constant of the second insulating region 41 is set to be greater than the dielectric constant of the first insulating region 40, so that the withstand voltage and the breakdown voltage of the silicon carbide power device can be further improved, and meanwhile, the reliability problem of the gate dielectric layer 004 can be avoided. The on-resistance of the silicon carbide power device can also be reduced by using a higher doping concentration epitaxial layer 003 (including a higher doping concentration drift region 30, first body region 31, junction field effect transistor region 32, second body region 33, first source region 34, and second source region 35) or a junction field effect transistor region 32 of greater width. And the voltage endurance capability of the area which is most easy to break down is improved, and the gate-to-drain capacitance (Cgd) of the silicon carbide power device can be reduced within a certain range, so that the parasitic capacitance of the silicon carbide power device is reduced.
Optionally, on the basis of the above technical solution, as shown in fig. 3, fig. 3 is a schematic structural diagram of another silicon carbide power device provided according to an embodiment of the present invention, and a thickness of the second insulation region 41 is greater than a thickness of the first insulation region 40.
Specifically, on the basis that the product of the safe electric field intensity and the dielectric constant of the second insulating region 41 (the region where the electric field peak value is located, namely, the region which is most easily punctured) is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region 40, the thickness of the second insulating region 41 is larger than the thickness of the first insulating region 40, so that the withstand voltage and the breakdown voltage of the silicon carbide power device can be further improved, and meanwhile, the problem of reliability of the gate dielectric layer 004 can be avoided. The on-resistance of the silicon carbide power device can also be reduced by using a higher doping concentration epitaxial layer 003 (including a higher doping concentration drift region 30, first body region 31, junction field effect transistor region 32, second body region 33, first source region 34, and second source region 35) or a junction field effect transistor region 32 of greater width. And the voltage endurance capability of the area which is most easily broken down is improved, and the gate-to-drain capacitance (Cgd) of the silicon carbide power device can be reduced in a certain range, so that the parasitic capacitance of the silicon carbide power device is reduced.
Alternatively, on the basis of the above technical solutions, as shown in fig. 1 and 2, the thickness of the second insulation region 41 is equal to the thickness of the first insulation region 40.
Specifically, on the basis that the product of the safe electric field intensity and the dielectric constant of the second insulating region 41 (the region where the electric field peak is located, i.e., the region most prone to breakdown) is greater than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region 40, the thickness of the second insulating region 41 is equal to the thickness of the first insulating region 40, and the requirements of the withstand voltage and the breakdown voltage of the silicon carbide power device can be ensured.
Optionally, on the basis of the above technical solution, the material of the first insulating region 40 is silicon dioxide.
The first insulation region 40 is not a region where an electric field peak value is located, namely, not a region which is most easily broken down, the material of the first insulation region 40 is silicon dioxide, the silicon dioxide is low in price, and the preparation cost of the silicon carbide power device can be reduced as much as possible on the basis that the silicon carbide power device is not broken down.
Optionally, on the basis of the above technical solution, as shown in fig. 1 to fig. 3, the gate dielectric layer 004 covers a portion of the first body region 31, a portion of the first source region 34, the junction field effect transistor region 32, a portion of the second body region 33, and a portion of the second source region 35.
The embodiment of the present invention further provides a switching device, which includes any of the silicon carbide power devices described in the above technical solutions, and therefore, the switching device has the beneficial effects of the silicon carbide power device, which are not described herein again.
It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired result of the technical solution of the present invention can be achieved.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A silicon carbide power device comprising at least one cell, wherein the cell is configured to be electrically connected to the power device,
the unit cell comprises a substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged;
the drain electrode is positioned on the first surface of the substrate;
the epitaxial layer is positioned on the second surface of the substrate;
the epitaxial layer is provided with a drift region, a first body region, a junction field effect transistor region and a second body region, the first body region is provided with a first source region, and the second body region is provided with a second source region;
the gate dielectric layer is positioned on the surface of the epitaxial layer far away from the substrate;
the grid electrode is positioned on the surface of the grid dielectric layer far away from the epitaxial layer;
the gate dielectric layer comprises a first insulating region and a second insulating region, the silicon carbide power device is in a turn-off state, when an applied voltage is higher than a preset high voltage, the electric field peak value of the gate dielectric layer is located in the second insulating region, and the product of the safe electric field intensity and the dielectric constant of the second insulating region is larger than the product of the breakdown electric field intensity and the dielectric constant of the first insulating region.
2. The silicon carbide power device of claim 1, wherein the second insulating region has an electric field strength greater than a safe electric field strength of the first insulating region.
3. The silicon carbide power device of claim 1, wherein the first insulating region comprises a first sub-insulating region and a second sub-insulating region, and the second insulating region is located between the first sub-insulating region and the second sub-insulating region in a direction perpendicular to the direction in which the gate dielectric layer is directed toward the epitaxial layer.
4. The silicon carbide power device of claim 1 or 3, wherein the orthographic projection of the second insulating region on the epitaxial layer and the orthographic projection of the first body region on the epitaxial layer do not overlap;
the second insulation region has no overlap in the orthographic projection of the epitaxial layer and the orthographic projection of the second body region on the epitaxial layer.
5. The silicon carbide power device of claim 1, wherein the second insulating region has a dielectric constant greater than a dielectric constant of the first insulating region.
6. The silicon carbide power device of claim 1, wherein the second insulating region has a thickness greater than a thickness of the first insulating region.
7. The silicon carbide power device of claim 1, wherein the thickness of the second insulating region is equal to the thickness of the first insulating region.
8. The silicon carbide power device of claim 1, wherein the material of the first insulating region is silicon dioxide.
9. The silicon carbide power device of claim 1, wherein the gate dielectric layer covers a portion of the first body region, a portion of the first source region, the junction field effect transistor region, a portion of the second body region, and a portion of the second source region.
10. A switching device comprising the silicon carbide power device of any one of claims 1-9.
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| CN115810656A (en) * | 2023-02-01 | 2023-03-17 | 江苏长晶科技股份有限公司 | Silicon carbide MOSFET device, preparation method thereof and chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102779852A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure |
| CN104952917A (en) * | 2015-07-03 | 2015-09-30 | 电子科技大学 | SiC VDMOS (vertical double-diffused metal oxide semiconductor) device |
| CN115312586A (en) * | 2022-09-01 | 2022-11-08 | 江苏长晶科技股份有限公司 | Silicon carbide power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102779852A (en) * | 2012-07-18 | 2012-11-14 | 电子科技大学 | SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure |
| CN104952917A (en) * | 2015-07-03 | 2015-09-30 | 电子科技大学 | SiC VDMOS (vertical double-diffused metal oxide semiconductor) device |
| CN115312586A (en) * | 2022-09-01 | 2022-11-08 | 江苏长晶科技股份有限公司 | Silicon carbide power device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115810656A (en) * | 2023-02-01 | 2023-03-17 | 江苏长晶科技股份有限公司 | Silicon carbide MOSFET device, preparation method thereof and chip |
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