CN107706234A - Contact hole and its manufacture method - Google Patents
Contact hole and its manufacture method Download PDFInfo
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- CN107706234A CN107706234A CN201710903978.2A CN201710903978A CN107706234A CN 107706234 A CN107706234 A CN 107706234A CN 201710903978 A CN201710903978 A CN 201710903978A CN 107706234 A CN107706234 A CN 107706234A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 28
- 239000010937 tungsten Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004411 aluminium Substances 0.000 claims abstract description 17
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- 230000008030 elimination Effects 0.000 abstract description 2
- 238000003379 elimination reaction Methods 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of contact hole, including：The interlayer film of surface of silicon is formed at, the opening of the contact hole formed after being removed in interlayer film formed with interlayer film.Contact hole opening side formed with tungsten side wall, the bottom of the opening of contact hole surface of silicon formed with metal adhesion layer.Metallic aluminium and composition contact hole are filled with opening in contact.The invention also discloses a kind of manufacture method of contact hole.The present invention can improve the fillibility of the metal of contact hole and the metal and substrate silicon of elimination contact hole dissolve each other, and improve product quality.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of contact hole.The invention further relates to one
The manufacture method of kind contact hole.
Background technology
Insulated gate bipolar transistor (IGBT, Insulated Gate Bipolar Transistor), is by ambipolar
The compound full-control type voltage driven type power semiconductor device of triode (BJT) and insulating gate type field effect tube (MOSFET) composition
Part, have MOSFET high input impedance and power transistor (GTR) i.e. high voltage withstanding, high current bipolar junction transistor concurrently
Advantage of both low conduction voltage drop.DC voltage is highly suitable to be applied for as 600V and the converter system such as alternating current of the above
The fields such as machine, frequency converter, Switching Power Supply, lighting circuit, Traction Drive.
For IGBT techniques, good contact hole structure is greatly improved to the reliability of device.Poor contact
Pore structure is possible to that metal filled property difference or front metal can be caused to dissolve each other with substrate silicon materials, forms spike (spiking),
Electric current ultimately results in product failure in device skewness.
As shown in figure 1, it is existing IGBT structural representation；Existing IGBT includes：
It is formed at the drift region 9 formed by n-type doping area on the surface of silicon substrate 9.
Body area 6, it is formed from the p-well composition on the surface of drift region 9.
Back side p-type implanted layer 10, it is formed at the back side of the drift region 9.
Grid structure, the surface of body area 6 for covering the body area 6 and being covered by the grid structure are used to form connection
The source region 5 and the raceway groove of the drift region 9.In Fig. 1, the grid structure is trench gate structure；The body area 6 is positioned at whole
The surface of the drift region 9.The trench gate includes the groove through the body area 6, in the side of the groove and bottom table
Face is formed with such as gate oxide of gate dielectric layer 8, in the trench filled with polysilicon gate 7；The polysilicon gate 7 covers from side
Cover the body area 6.
Source region 5, be formed at the surface of body area 6 and with the side autoregistration of the grid structure.
Body area draw-out area 4 is formed at the surface of body area 6.
The interlayer film 2 on the surface of silicon substrate 9 is formed at, shape after being removed in the interlayer film 2 formed with the interlayer film 2
Into contact hole opening.
On the surface of the silicon substrate 9 of the bottom of the opening of the contact hole formed with metal adhesion layer 3.
Filled with contact hole described in metallic aluminium and composition in opening in the contact.In Fig. 1, the gold of the contact hole
Category aluminium is directly filled by the front metal layer 1 to be formed.
The bottom of the contact hole be formed at the surface of silicon substrate 9 by N+ district's groups into source region 5 and by P+ district's groups
Into body area draw-out area 4 contact.The top of the contact hole formed with the contact hole be in contact by front metal layer 1
The electrode of composition is emitter stage.
Contact hole shown in Fig. 1 is possible to that metal filled property difference or front metal can be caused to dissolve each other with substrate silicon materials,
Spike is formed, electric current ultimately results in product failure in device skewness.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of contact hole, can improve contact hole metal fillibility with
And the metal and substrate silicon of elimination contact hole dissolve each other, and improve product quality.Therefore, the present invention also provides a kind of manufacture of contact hole
Method.
In order to solve the above technical problems, contact hole provided by the invention includes：
The interlayer film of surface of silicon is formed at, is formed after being removed in the interlayer film formed with the interlayer film
The opening of contact hole.
The contact hole opening side formed with tungsten side wall, the institute in the bottom of the opening of the contact hole
Surface of silicon is stated formed with metal adhesion layer.
Filled with contact hole described in metallic aluminium and composition in opening in the contact.
Further improve be, the bottom of the contact hole and is formed at the N+ areas of the surface of silicon and P+ areas connect
Touch.
Further improve be, the top of the contact hole formed with the contact hole be in contact by front metal
The electrode of layer composition.
Further improve is that the contact hole is IGBT emitter stage contact hole.
The bottom of the emitter stage contact hole with by N+ district's groups into source region and by P+ district's groups into body area draw-out area connect
Touch.
The top of the emitter stage contact hole and the emitter stage being made up of front metal layer contact.
Further improve is that the IGBT also includes：
It is formed at the drift region formed by n-type doping area of the surface of silicon.
Body area, it is formed from the p-well composition on the drift region surface.
Back side p-type implanted layer, it is formed at the back side of the drift region.
Grid structure, the body surface for covering the body area and being covered by the grid structure are used to form connection institute
State the raceway groove of source region and the drift region.
The source region be formed at the body surface and with the side autoregistration of the grid structure.
Body area draw-out area is formed at the body surface.
Further improve is that the grid structure is trench gate structure；The body area is located at the whole drift region
Surface.
The trench gate includes the groove through the body area, is situated between in the side of the groove and lower surface formed with grid
Matter layer, in the trench filled with polysilicon gate；The polysilicon gate covers the body area from side.
Further improve is that the grid structure is planar gate structure；The body area is located at the selected of the drift region
The surface in region.
The planar gate includes being formed at the gate dielectric layer of the body surface, the surface of the gate dielectric layer formed with
Polysilicon gate, the polysilicon gate cover the body area from top.
In order to solve the above technical problems, the manufacture method of contact hole provided by the invention comprises the following steps：
Step 1: form interlayer film in surface of silicon.
Step 2: it is lithographically formed the forming region that photoetching offset plate figure defines the contact hole.
Opened Step 3: performed etching using the photoetching offset plate figure as mask to the interlayer film and to form the contact hole
Mouthful.
Step 4: remove the photoetching offset plate figure.
Step 5: deposit metal adhesion layer.
Step 6: deposit tungsten, the tungsten be formed at side and the lower surface of the opening of the contact hole with
And the interlayer film surface outside the opening of the contact hole.
Step 7: carrying out comprehensive etching of the tungsten, gold is formed in the side of the opening of the contact hole after etching
Belong to tungsten side wall, the tungsten on the interlayer film surface outside the lower surface and opening of the opening of the contact hole is all removed.
Step 8: the opening in the contact is filled and forms the contact hole by deposit metallic aluminium.
Further improve be, the bottom of the contact hole and is formed at the N+ areas of the surface of silicon and P+ areas connect
Touch.
The further top for being to be additionally included in the contact hole of improving is formed and the contact hole is in contact by front
The step of electrode of metal level composition.
Further improve is that the contact hole is IGBT emitter stage contact hole.
The bottom of the emitter stage contact hole with by N+ district's groups into source region and by P+ district's groups into body area draw-out area connect
Touch.
The top of the emitter stage contact hole and the emitter stage being made up of front metal layer are in contact.
Further improve is the step of also including forming the IGBT as follows before forming the interlayer film：
Step 11, the drift region formed in surface of silicon formation by n-type doping area.
Step 12, form p-well on the drift region surface and body area is formed by the p-well.
Step 13, grid structure is formed, the grid structure covers the body area and the institute covered by the grid structure
Body surface is stated to be used to form the raceway groove for connecting the source region and the drift region.
Step 14, progress N+ ion implantings form the source region, the source region and the grid knot in the body surface
The side autoregistration of structure.
Step 15, progress P+ ion implantings form body area draw-out area in the body surface.
After emitter stage formation, in addition to following back process：
Step 9: the silicon substrate is thinned, carries out back side P+ ion implantings and form back side p-type implanted layer, it is described
Back side p-type implanted layer and the back face of the drift region touch.
Step 10: form metal layer on back.
Further improve is that the grid structure is trench gate structure；The body area is located at the whole drift region
Surface；The step of forming the grid structure includes：
Form the groove through the body area.
Gate dielectric layer is formed in the side of the groove and lower surface.
Polysilicon gate is filled with the trench；The polysilicon gate covers the body area from side.
Further improve is that the grid structure is planar gate structure；The body area is located at the selected of the drift region
The surface in region；The step of forming the grid structure includes：
Sequentially form gate dielectric layer and polysilicon gate.
Lithographic definition goes out the forming region of the grid structure, and the polysilicon gate and the gate dielectric layer are carried out successively
Etching forms the grid structure；The polysilicon gate of the grid structure covers the body area from top.
Further improve is that the gate dielectric layer is gate oxide.
Further improvement is that the thickness of the tungsten deposited in step 6 is 0.4 micron~1.5 microns.
The present invention has done special design to the structure of contact hole, is not directly to fill out after the opening of contact hole is formed
Metallic aluminium is filled, but the side of the opening in contact hole forms tungsten side wall, tungsten side wall can be in the opening of contact hole
Place forms good contact, so as to eliminate the technical problem for causing metal filled property difference during directly filling metallic aluminium；It is meanwhile logical
The formation of tungsten side wall is crossed, also prevents metallic aluminium from easily forming the phenomenon that aluminium silicon dissolves each other by the open side bottom of contact hole
Occur, so as to prevent the formation of prong, allow current to, uniformly through contact hole, improve product quality, prevent product failure, from
And improve product yield.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is existing IGBT structural representation；
Fig. 2 is IGBT of embodiment of the present invention structural representation.
Embodiment
Contact hole of the embodiment of the present invention with the emitter stage contact hole applied to IGBT in order to illustrate, as shown in Fig. 2 being
IGBT of embodiment of the present invention structural representation；Contact hole of the embodiment of the present invention includes：
The interlayer film 2 on the surface of silicon substrate 9 is formed at, shape after being removed in the interlayer film 2 formed with the interlayer film 2
Into contact hole opening.
The contact hole opening side formed with tungsten side wall 12, in the bottom of the opening of the contact hole
The surface of silicon substrate 9 is formed with metal adhesion layer 3.
Filled with contact hole described in metallic aluminium and composition in opening in the contact.It is described in the embodiment of the present invention
The metallic aluminium of contact hole is directly filled by the front metal layer 1 and formed.
The bottom of the contact hole and N+ areas or the contact of P+ areas for being formed at the surface of silicon substrate 9.In the contact hole
Top formed with the electrode being made up of front metal layer 1 being in contact with the contact hole.It is described to connect in the embodiment of the present invention
Contact hole is IGBT emitter stage contact hole.The bottom of the emitter stage contact hole with by N+ district's groups into source region 5 and by P+ areas
The body area draw-out area 4 of composition contacts.The top of the emitter stage contact hole and the emitter stage being made up of front metal layer 1 contact.
The IGBT also includes：
It is formed at the drift region 9 formed by n-type doping area on the surface of silicon substrate 9.
Body area 6, it is formed from the p-well composition on the surface of drift region 9.
Back side p-type implanted layer 10, it is formed at the back side of the drift region 9.
Grid structure, the surface of body area 6 for covering the body area 6 and being covered by the grid structure are used to form connection
The source region 5 and the raceway groove of the drift region 9.
The source region 5 be formed at the surface of body area 6 and with the side autoregistration of the grid structure.
Body area draw-out area 4 is formed at the surface of body area 6.
In the embodiment of the present invention, the grid structure is trench gate structure；The body area 6 is located at the whole drift region 9
Surface.The trench gate includes the groove through the body area 6, is situated between in the side of the groove and lower surface formed with grid
Matter layer 8, in the trench filled with polysilicon gate 7；The polysilicon gate 7 covers the body area 6 from side.In other implementations
In example, the grid structure is planar gate structure；The body area 6 is located at the surface of the selection area of the drift region 9.It is described flat
Face grid include being formed at the gate dielectric layer 8 on the surface of body area 6, on the surface of the gate dielectric layer 8 formed with polysilicon gate 7,
The polysilicon gate 7 covers the body area 6 from top.
The embodiment of the present invention has done special design to the structure of contact hole, after the opening of contact hole is formed, is not
Metallic aluminium is directly filled, but the side of the opening in contact hole forms tungsten side wall 12, tungsten side wall 12 can connect
The opening of contact hole forms good contact, causes the technology of metal filled property difference to be asked during directly filling metallic aluminium so as to eliminate
Topic；Meanwhile by the formation of tungsten side wall 12, also prevent metallic aluminium from easily forming aluminium by the open side bottom of contact hole
The phenomenon that silicon dissolves each other occurs, and so as to prevent the formation of prong, allows current to, uniformly through contact hole, improve product quality, prevents
Only product failure, so as to improve product yield.
The manufacture method of contact hole of the embodiment of the present invention comprises the following steps：
Step 1: form interlayer film 2 on the surface of silicon substrate 9.
Step 2: it is lithographically formed the forming region that photoetching offset plate figure defines the contact hole.
Opened Step 3: performed etching using the photoetching offset plate figure as mask to the interlayer film 2 and to form the contact hole
Mouthful.
Step 4: remove the photoetching offset plate figure.
Step 5: deposit metal adhesion layer 3.
Step 6: deposit tungsten, the tungsten be formed at side and the lower surface of the opening of the contact hole with
And the surface of the interlayer film 2 outside the opening of the contact hole.Preferably, the thickness of the tungsten of deposit is 0.4 micron
~1.5 microns.
Step 7: carrying out comprehensive etching of the tungsten, gold is formed in the side of the opening of the contact hole after etching
Belong to tungsten side wall 12, the tungsten on the surface of the interlayer film 2 outside the lower surface and opening of the opening of the contact hole is all gone
Remove.
Step 8: the opening in the contact is filled and forms the contact hole by deposit metallic aluminium.The contact hole
Bottom and N+ areas or the contact of P+ areas for being formed at the surface of silicon substrate 9.It is additionally included in top formation and the institute of the contact hole
The step of stating the electrode being made up of front metal layer 1 that contact hole is in contact.
In present invention method, the contact hole is IGBT emitter stage contact hole.The emitter stage contact hole
Bottom with by N+ district's groups into source region 5 and by P+ district's groups into body area draw-out area 4 contact.The top of the emitter stage contact hole
It is in contact with the emitter stage being made up of front metal layer 1.Also include forming the IGBT as follows before the interlayer film 2 is formed
The step of：
Step 11, the drift region 9 formed in the surface of silicon substrate 9 formation by n-type doping area.
Step 12, form p-well on the surface of drift region 9 and body area 6 is formed by the p-well.
Step 13, grid structure is formed, the grid structure covers the body area 6 and the institute covered by the grid structure
The surface of Shu Ti areas 6 is used to form the raceway groove for connecting the source region 5 and the drift region 9.
In present invention method, the grid structure is trench gate structure；The body area 6 is located at the whole drift
The surface in area 9；The step of forming the grid structure includes：
Form the groove through the body area 6.
Gate dielectric layer 8 is formed in the side of the groove and lower surface.Preferably, the gate dielectric layer 8 is gate oxidation
Layer.
Polysilicon gate 7 is filled with the trench；The polysilicon gate 7 covers the body area 6 from side.
Also can be in other embodiments method：The grid structure is planar gate structure；The body area 6 is located at the drift
Move the surface of the selection area in area 9；The step of forming the grid structure includes：
Sequentially form gate dielectric layer 8 and polysilicon gate 7.Preferably, the gate dielectric layer 8 is gate oxide.
Lithographic definition goes out the forming region of the grid structure, and the polysilicon gate 7 and the gate dielectric layer 8 are entered successively
Row etching forms the grid structure；The polysilicon gate 7 of the grid structure covers the body area 6 from top.
Step 14, progress N+ ion implantings form the source region 5, the source region 5 and the grid on the surface of body area 6
The side autoregistration of structure.
Step 15, progress P+ ion implantings form body area draw-out area 4 on the surface of body area 6.
After emitter stage formation, in addition to following back process：
Step 9: the silicon substrate 9 is thinned, carries out back side P+ ion implantings and form back side p-type implanted layer 10, institute
The back face for stating back side p-type implanted layer 10 and the drift region 9 touches.
Step 10: form metal layer on back.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (15)
- A kind of 1. contact hole, it is characterised in that including：The interlayer film of surface of silicon is formed at, the contact formed after being removed in the interlayer film formed with the interlayer film The opening in hole；The contact hole opening side formed with tungsten side wall, the silicon in the bottom of the opening of the contact hole Substrate surface is formed with metal adhesion layer；Filled with contact hole described in metallic aluminium and composition in opening in the contact.
- 2. contact hole as claimed in claim 1, it is characterised in that：The bottom of the contact hole and it is formed at the silicon substrate table Mian N+ areas and the contact of P+ areas.
- 3. contact hole as claimed in claim 1, it is characterised in that：The top of the contact hole formed with the contact hole The electrode being made up of front metal layer being in contact.
- 4. contact hole as claimed in claim 1, it is characterised in that：The contact hole is IGBT emitter stage contact hole；The bottom of the emitter stage contact hole with by N+ district's groups into source region and by P+ district's groups into body area draw-out area contact；The top of the emitter stage contact hole and the emitter stage being made up of front metal layer contact.
- 5. contact hole as claimed in claim 4, it is characterised in that the IGBT also includes：It is formed at the drift region formed by n-type doping area of the surface of silicon；Body area, it is formed from the p-well composition on the drift region surface；Back side p-type implanted layer, it is formed at the back side of the drift region；Grid structure, the body surface for covering the body area and being covered by the grid structure are used to form the connection source Area and the raceway groove of the drift region；The source region be formed at the body surface and with the side autoregistration of the grid structure；Body area draw-out area is formed at the body surface.
- 6. contact hole as claimed in claim 5, it is characterised in that：The grid structure is trench gate structure；The body position In the surface of the whole drift region；The trench gate includes the groove through the body area, in the side of the groove and lower surface formed with gate medium Layer, in the trench filled with polysilicon gate；The polysilicon gate covers the body area from side.
- 7. contact hole as claimed in claim 5, it is characterised in that：The grid structure is planar gate structure；The body position In the surface of the selection area of the drift region；The planar gate includes being formed at the gate dielectric layer of the body surface, on the surface of the gate dielectric layer formed with polycrystalline Si-gate, the polysilicon gate cover the body area from top.
- 8. a kind of manufacture method of contact hole, it is characterised in that comprise the following steps：Step 1: form interlayer film in surface of silicon；Step 2: it is lithographically formed the forming region that photoetching offset plate figure defines the contact hole；Step 3: perform etching the opening to form the contact hole to the interlayer film as mask using the photoetching offset plate figure；Step 4: remove the photoetching offset plate figure；Step 5: deposit metal adhesion layer；Step 6: deposit tungsten, the tungsten are formed at side and lower surface and the institute of the opening of the contact hole State the interlayer film surface outside the opening of contact hole；Step 7: carrying out comprehensive etching of the tungsten, the side of the opening after etching in the contact hole forms tungsten Side wall, the tungsten on the interlayer film surface outside the lower surface and opening of the opening of the contact hole are all removed；Step 8: the opening in the contact is filled and forms the contact hole by deposit metallic aluminium.
- 9. the manufacture method of contact hole as claimed in claim 8, it is characterised in that：The bottom of the contact hole and it is formed at institute State N+ areas and the contact of P+ areas of surface of silicon.
- 10. the manufacture method of contact hole as claimed in claim 8, it is characterised in that：It is additionally included in the top of the contact hole The step of forming the electrode being made up of front metal layer being in contact with the contact hole.
- 11. the manufacture method of contact hole as claimed in claim 8, it is characterised in that：The contact hole is IGBT emitter stage Contact hole；The bottom of the emitter stage contact hole with by N+ district's groups into source region and by P+ district's groups into body area draw-out area contact；The top of the emitter stage contact hole and the emitter stage being made up of front metal layer are in contact.
- 12. the manufacture method of contact hole as claimed in claim 11, it is characterised in that also include before forming the interlayer film The step of forming the IGBT as follows：Step 11, the drift region formed in surface of silicon formation by n-type doping area；Step 12, form p-well on the drift region surface and body area is formed by the p-well；Step 13, grid structure is formed, the grid structure covers the body area and the body covered by the grid structure Area surface is used to form the raceway groove for connecting the source region and the drift region；Step 14, carry out N+ ion implantings and form the source region in the body surface, the source region and the grid structure Side autoregistration；Step 15, progress P+ ion implantings form body area draw-out area in the body surface；After emitter stage formation, in addition to following back process：Step 9: the silicon substrate is thinned, carries out back side P+ ion implantings and form back side p-type implanted layer, the back side P Type implanted layer and the back face of the drift region touch；Step 10: form metal layer on back.
- 13. the manufacture method of contact hole as claimed in claim 12, it is characterised in that：The grid structure is trench gate knot Structure；The body area is located at the surface of the whole drift region；The step of forming the grid structure includes：Form the groove through the body area；Gate dielectric layer is formed in the side of the groove and lower surface；Polysilicon gate is filled with the trench；The polysilicon gate covers the body area from side.
- 14. the manufacture method of contact hole as claimed in claim 12, it is characterised in that：The grid structure is planar gate knot Structure；The body area is located at the surface of the selection area of the drift region；The step of forming the grid structure includes：Sequentially form gate dielectric layer and polysilicon gate；Lithographic definition goes out the forming region of the grid structure, and the polysilicon gate and the gate dielectric layer are performed etching successively Form the grid structure；The polysilicon gate of the grid structure covers the body area from top.
- 15. the manufacture method of contact hole as claimed in claim 8, it is characterised in that：The tungsten deposited in step 6 Thickness be 0.4 micron~1.5 microns.
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| CN201710903978.2A CN107706234A (en) | 2017-09-29 | 2017-09-29 | Contact hole and its manufacture method |
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| CN201710903978.2A CN107706234A (en) | 2017-09-29 | 2017-09-29 | Contact hole and its manufacture method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111508837A (en) * | 2020-04-23 | 2020-08-07 | 中国科学院微电子研究所 | Manufacturing method of N-channel SiC IGBT device |
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| JPH05347269A (en) * | 1992-06-16 | 1993-12-27 | Sony Corp | Manufacture of semiconductor device |
| CN101930977A (en) * | 2009-06-19 | 2010-12-29 | 万国半导体股份有限公司 | Power metal oxide semiconductor field effect transistor (MOSFET) device with tungsten spacing layer in contact hole and preparation method thereof |
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
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2017
- 2017-09-29 CN CN201710903978.2A patent/CN107706234A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05347269A (en) * | 1992-06-16 | 1993-12-27 | Sony Corp | Manufacture of semiconductor device |
| CN101930977A (en) * | 2009-06-19 | 2010-12-29 | 万国半导体股份有限公司 | Power metal oxide semiconductor field effect transistor (MOSFET) device with tungsten spacing layer in contact hole and preparation method thereof |
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111508837A (en) * | 2020-04-23 | 2020-08-07 | 中国科学院微电子研究所 | Manufacturing method of N-channel SiC IGBT device |
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