CN107704013A - A kind of whole CMOS reference circuit in Internet of Things - Google Patents
A kind of whole CMOS reference circuit in Internet of Things Download PDFInfo
- Publication number
- CN107704013A CN107704013A CN201711004110.5A CN201711004110A CN107704013A CN 107704013 A CN107704013 A CN 107704013A CN 201711004110 A CN201711004110 A CN 201711004110A CN 107704013 A CN107704013 A CN 107704013A
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- pipes
- grid
- circuit
- drain electrode
- nmos tube
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses the whole CMOS reference circuit in a kind of Internet of Things, including：One start-up circuit, the reference circuit is driven by single NMOS tube；One operational amplification circuit, using self biased differential structure, at utmost reduce because curent change is on influence caused by circuit；One core reference circuit, using cascode structure, the precision of caused reference voltage is also very high, resistance is used due to no in whole circuit, also without triode, entirely MOS transistor is used, so the area of overall circuit is very small.
Description
Technical field
The present invention relates to the whole CMOS reference circuit in reference voltage circuit field, more particularly to a kind of Internet of Things.
Background technology
In the application of Internet of Things and most of wireless telecommunications, associated receiver circuitry or radiating circuit etc. are all that needs are low
Power consumption, therefore the reference circuit that can produce low-power consumption is very crucial and very necessary for whole application.Benchmark electricity
Pith of the road as analog circuit, the normal work within the scope of a wider temperature is generally required, therefore do not required nothing more than
It is low in energy consumption, it is also necessary to stable performance, to there is preferable temperature characterisitic.Traditional mode can be set using band-gap reference circuit
Meter, but its power consumption is relatively large, and need to use resistance and triode, cause chip area larger.
The content of the invention
It is complete in a kind of Internet of Things it is a primary object of the present invention to provide to overcome the above-mentioned problems of the prior art
CMOS reference circuits, suitable for the circuit system of low-power consumption.
In view of the above and other objects, the present invention provides the whole CMOS reference circuit in a kind of Internet of Things, it is comprised at least：
One start-up circuit, the reference circuit is driven by single NMOS tube；
One operational amplification circuit, using self biased differential structure, at utmost reduce because curent change is on influence caused by circuit；
One core reference circuit, using cascode structure, the precision of caused reference voltage is also very high, due to whole circuit
In not using resistance, triode is not also used, so the area of overall circuit is also very small.
The start-up circuit is made up of the tenth NMOS tube NM10.
The operational amplification circuit is by the first PMOS PM1, the second PMOS PM2, the 3rd PMOS PM3, the first NMOS
Pipe NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 are formed；The source electrode of PM1 pipes, PM2 source electrode and
The source electrode of PM3 pipes is all connected with supply voltage VDD；The grid of PM1 pipes is managed with the drain electrode of PM1 pipes, the drain electrode of NM1 pipes and PM2
Grid be connected；The drain electrode of PM2 pipes is connected with the drain electrode of NM2 pipes, the drain electrode of the grid and NM10 pipes of PM3 pipes；PM3 pipes
Drain electrode is connected with the grid of the grid of NM10 pipes, the drain electrode of NM4 pipes, the grid of NM4 pipes, NM3 pipes, and its node label is VC；
The grid of NM1 pipes is connected with NM10 pipe source electrodes, and its node label is VB；The source electrode of NM1 pipes is managed with the source electrode of NM2 pipes and NM3
Drain electrode be connected；The source electrode of NM3 pipes and the source ground of NM4 pipes.
The core reference circuit is by the 4th PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, the 5th NMOS
Pipe NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 are formed；The source of PM4 pipes
The source electrode of pole, the source electrode of PM5 pipes and PM6 pipes is all connected with supply voltage VDD；The grid of PM4 pipes, the grid and PM6 of PM5 pipes
Grid of the grid of pipe all with PM3 pipes is connected；The drain electrode of grid, NM5 pipe and the grid of NM5 pipe of the drain electrode of PM4 pipes with NM2 pipes
Pole is connected, and its node label is VA；Drain electrode and the source electrode of NM10 pipes, the drain electrode of NM7 pipes, grid, the NM8 of NM7 pipes of PM5 pipes
The drain electrode of pipe is connected with the grid of NM8 pipes；The source electrode of NM7 pipes is connected with the drain electrode of the grid and NM6 pipes of NM6 pipes；PM6 is managed
Drain electrode be connected with the drain electrode of the grid and NM9 pipes of NM9 pipes, output end of its node as reference voltage V REF；NM5 pipes
Source electrode, the source electrode of NM6 pipes, the source ground of the source electrode of NM8 pipes and NM9 pipes.
Brief description of the drawings
The accompanying drawing for forming the part of the application is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate to be used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the whole CMOS reference circuit figure in a kind of Internet of Things of the present invention.
Embodiment
With reference to shown in Fig. 1, in the following embodiments, the whole CMOS reference circuit, it is comprised at least：One starts electricity
Road, the reference circuit is driven by single NMOS tube；One operational amplification circuit, using self biased differential structure, at utmost
Reduce because curent change is on influence caused by circuit；One core reference circuit, using cascode structure, caused benchmark electricity
The precision of pressure is also very high, due to, without resistance is used, triode also not being used, so the face of overall circuit in whole circuit
Product is also very small.
Described start-up circuit is made up of single NMOS tube NM10, and the source electrode of NM10 pipes is connected with node VB, grid voltage
VG is constantly drawn high, until VGS>VTH, NM10 pipes are turned on, the low current for producing a pA rank flows through NM4 pipes, tail current pipe
Image current is input in operational amplification circuit so as to drive differential pair to work NM3 again.When the input of differential pair reaches stabilization
Voltage level, the source voltage of NM10 pipes rise, and its final source voltage is more than grid voltage, and transistor NM10 pipes are closed, electricity
Complete to start in road.
The operational amplification circuit is by the first PMOS PM1, the second PMOS PM2, the 3rd PMOS PM3, the first NMOS
Pipe NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 are formed；Using self biased differential structure, pass through
The transistor NM3 pipes and NM4 pipes of current-mirror structure drive output current as the input current of itself to realize automatic biasing, wherein
NM1 pipes and NM2 pipes, PM1 pipes are identical with the size of PM2 pipes, and the load of its current-mirror structure further improves voltage gain, reduces
Power source change dependence.
The core reference circuit is by the 4th PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, the 5th NMOS
Pipe NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 are formed；The computing is put
Big circuit causes node VA voltages to be equal to node VB, and therefore, negative temperature characteristic, transistor NM6 is presented in the voltage on transistor NM5
On voltage positive temperature characterisitic is presented, transistor NM7, NM8, NM9 equivalent to passive resistance, by adjust NM7 pipes, NM8 pipes,
NM9 physical dimension and NM5 pipe, the area of NM6 pipes can realize temperature-compensating.
The present invention proposes a kind of whole CMOS reference circuit, compared with other circuits, without using resistance in circuit, does not also make
It is simpler with triode, structure.The circuit is designed using 0.18 μm of CMOS technology, can provide 900mV output voltage, temperature
It is 15ppm/ DEG C to spend coefficient, and electric current during 1.8V is 5.6uA, and the performance of circuit is greatly improved under conditions of limited area.
Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment
Scope.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, easily carry out various modifications or embodiment can be combined, these also should be regarded as protection scope of the present invention.
Claims (2)
1. the whole CMOS reference circuit in a kind of Internet of Things, including：
One start-up circuit, the reference circuit is driven by single NMOS tube；
One operational amplification circuit, using self biased differential structure, at utmost reduce because curent change is on influence caused by circuit；
One core reference circuit, using cascode structure, the precision of caused reference voltage is also very high, due to whole circuit
In use resistance, to use triode, entirely MOS transistor, so the area of overall circuit is very small yet.
2. full COMS reference circuits as claimed in claim 1, it is characterised in that：The start-up circuit is by the tenth NMOS tube NM10
Form；Low-power consumption COMS reference circuits as claimed in claim 1, it is characterised in that：The operational amplification circuit is by first
PMOS PM1, the second PMOS PM2, the 3rd PMOS PM3, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube
NM3 and the 4th NMOS tube NM4 is formed；The source electrode of the source electrode of PM1 pipes, PM2 source electrode and PM3 pipes is all connected with supply voltage VDD
Connect；The grid of PM1 pipes is connected with the grid of the drain electrode of PM1 pipes, the drain electrode of NM1 pipes and PM2 pipes；The drain electrode of PM2 pipes is managed with NM2
Drain electrode, the drain electrode of grid and NM10 pipes of PM3 pipes is connected；The drain electrode of PM3 pipes and the drain electrode of the grid, NM4 pipes of NM10 pipes,
Grid, the grid of NM3 pipes of NM4 pipes are connected, and its node label is VC；The grid of NM1 pipes is connected with NM10 pipe source electrodes, its
Node label is VB；The source electrode of NM1 pipes is connected with the drain electrode of the source electrode and NM3 pipes of NM2 pipes；The source electrodes of NM3 pipes and NM4 pipes
Source ground；Low-power consumption COMS reference circuits as claimed in claim 1, it is characterised in that：The core reference circuit is by
Four PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS
Pipe NM7, the 8th NMOS tube NM8 and the 9th NMOS tube NM9 are formed；The source electrode of the source electrode of PM4 pipes, the source electrode of PM5 pipes and PM6 pipes is all
It is connected with supply voltage VDD；Grid of the grid of the grid of PM4 pipes, the grid of PM5 pipes and PM6 pipes all with PM3 pipes is connected
Connect；The drain electrode of grid, NM5 pipe and the grid of NM5 pipe of the drain electrode of PM4 pipes with NM2 pipes are connected, and its node label is VA；PM5
The drain electrode of pipe is connected with the grid of the source electrode of NM10 pipes, the drain electrode of NM7 pipes, the grid of NM7 pipes, the drain electrode of NM8 pipes and NM8 pipes
Connect；The source electrode of NM7 pipes is connected with the drain electrode of the grid and NM6 pipes of NM6 pipes；The drain electrode of PM6 pipes and the grid and NM9 of NM9 pipes
The drain electrode of pipe is connected, output end of its node as reference voltage V REF；The source electrode of NM5 pipes, the source electrode of NM6 pipes, NM8 pipes
The source ground of source electrode and NM9 pipes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711004110.5A CN107704013A (en) | 2017-10-25 | 2017-10-25 | A kind of whole CMOS reference circuit in Internet of Things |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711004110.5A CN107704013A (en) | 2017-10-25 | 2017-10-25 | A kind of whole CMOS reference circuit in Internet of Things |
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| Publication Number | Publication Date |
|---|---|
| CN107704013A true CN107704013A (en) | 2018-02-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711004110.5A Pending CN107704013A (en) | 2017-10-25 | 2017-10-25 | A kind of whole CMOS reference circuit in Internet of Things |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111930172A (en) * | 2020-09-03 | 2020-11-13 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | Single-operational-amplifier self-biased cascode band-gap reference circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201689355U (en) * | 2009-11-09 | 2010-12-29 | 天津南大强芯半导体芯片设计有限公司 | Unsymmetrical bias voltage compensating band-gap reference circuit |
| CN103713684A (en) * | 2013-12-18 | 2014-04-09 | 深圳先进技术研究院 | Voltage reference source circuit |
| CN103853228A (en) * | 2012-12-07 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Reference voltage generating circuit |
| CN104133519A (en) * | 2014-07-30 | 2014-11-05 | 中国科学院微电子研究所 | Low-voltage band-gap reference generating circuit applied to three-dimensional storage field |
| CN104977972A (en) * | 2015-07-08 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Low pressure and low power-consumption band-gap reference circuit |
-
2017
- 2017-10-25 CN CN201711004110.5A patent/CN107704013A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201689355U (en) * | 2009-11-09 | 2010-12-29 | 天津南大强芯半导体芯片设计有限公司 | Unsymmetrical bias voltage compensating band-gap reference circuit |
| CN103853228A (en) * | 2012-12-07 | 2014-06-11 | 上海华虹集成电路有限责任公司 | Reference voltage generating circuit |
| CN103713684A (en) * | 2013-12-18 | 2014-04-09 | 深圳先进技术研究院 | Voltage reference source circuit |
| CN104133519A (en) * | 2014-07-30 | 2014-11-05 | 中国科学院微电子研究所 | Low-voltage band-gap reference generating circuit applied to three-dimensional storage field |
| CN104977972A (en) * | 2015-07-08 | 2015-10-14 | 北京兆易创新科技股份有限公司 | Low pressure and low power-consumption band-gap reference circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111930172A (en) * | 2020-09-03 | 2020-11-13 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | Single-operational-amplifier self-biased cascode band-gap reference circuit |
| CN111930172B (en) * | 2020-09-03 | 2022-04-15 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | Single-operational-amplifier self-biased cascode band-gap reference circuit |
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Application publication date: 20180216 |