CN101598954B - Reference voltage source circuit for enhancement type MOS tube - Google Patents

Abstract

The invention provides a reference voltage source circuit for an enhancement type MOS tube, which only comprises three components, namely an NMOS tube, a PMOS tube and a resistor without a depletion type NMOS tube and a longitudinal PNP tube, and mainly uses the characteristics of different linear temperature coefficients of threshold voltages of the NMOS and PMOS tubes to perform temperature compensation so as to obtain a reference voltage source with smaller temperature coefficient. The reference voltage source circuit consists of a starting circuit, a reference current source circuit and a reference voltage generating circuit, wherein the starting circuit is connected with the reference current source circuit to start the reference current source circuit; the reference current source circuit is connected between the starting circuit and the reference voltage generating circuit, is started by the starting circuit, and provides bias current for the reference voltage generating circuit; and the reference voltage generating circuit is connected with the reference current source circuit which provides the bias current for the reference voltage generating circuit through a mirror image circuit, and the reference voltage generating circuit generates and outputs reference voltage.

Description

A kind of reference voltage source circuit for enhancement type MOS tube

Affiliated technical field

The present invention is a kind of reference voltage source circuit, in the CMOS of standard technology, uses the enhancement mode metal-oxide-semiconductor to realize that this reference voltage has higher PSRR and less temperature coefficient, can be used for popular now 1.8V supply voltage system.

Background technology

At present, reference voltage source mainly contains two kinds, and a kind of is the reference voltage source that adopts depletion type MOS tube, and another kind is the longitudinal P NP pipe racks crack reference voltage source of employing and MOS process compatible.Though first kind of reference voltage source realizes that simply power consumption is little, incompatible depletion type MOS tube in the CMOS technology of a lot of standards.Second kind of reference voltage source is owing to complicated circuit, and power consumption is big, and the chip area that takies is more uneconomical, and is difficult to popular now low supply voltage system.

Summary of the invention

The invention provides a kind of reference voltage source circuit for enhancement type MOS tube; Only comprise NMOS pipe, PMOS pipe and three kinds of components and parts of resistance in the circuit structure; Depletion type NMOS manages and longitudinal P NP pipe and do not comprise; Mainly utilize NMOS to carry out Temperature Compensation, obtain the reference voltage source of less temperature coefficient with the characteristic of the different linear temperature coefficients of PMOS pipe threshold voltage.

A kind of reference voltage source circuit for enhancement type MOS tube of the present invention is by start-up circuit, and reference current source circuit and reference voltage generating circuit are formed, wherein,

Start-up circuit is connected in reference current source circuit, to start reference current source circuit;

Reference current source circuit is connected between start-up circuit and the reference voltage generating circuit, is activated circuit and starts, for reference voltage generating circuit provides bias current;

Reference voltage generating circuit is connected with reference current source circuit, for it bias current is provided through mirror image circuit by reference current source circuit, and this circuit produces output reference voltage.

Start-up circuit has two NMOS pipes, and (M0 M2) forms with a PMOS pipe (M1).

The PMOS pipe (M1) of start-up circuit connects for diode, source termination power voltage, and the drain terminal of a NMOS pipe (M0) connects the drain terminal and the grid end of PMOS pipe (M1), source end ground connection, the drain terminal and the grid end of the grid termination PMOS pipe (M1) of another NMOS pipe (M2).

Reference current source circuit is a K multiplication reference current source circuit.

Reference current source circuit is the K multiplication reference current source circuit of band feedback, and feedback is improved the sensitivity of reference current to supply voltage in order to improve the output resistance of metal-oxide-semiconductor.

Reference voltage generating circuit comprises mirror image PMOS pipe (M14), source termination power voltage, and grid termination start-up circuit and reference current source circuit are used for the reference current that the mirror image reference current source circuit produced, and think that reference voltage generating circuit provides bias current.

Reference voltage generating circuit also comprises:

First resistor (R2), an end ground connection, another termination output NMOS (M16) pipe and

Second resistor (R1), the source end of another termination PMOS (M15) pipe;

Output pmos (M15), the grid end links to each other with drain terminal, is connected to output reference voltage;

Output NMOS pipe (M16), drain terminal connects output reference voltage, source end ground connection.

Description of drawings

Fig. 1 is the circuit structure block diagram that the present invention strengthens the metal-oxide-semiconductor reference voltage source circuit

Fig. 2 is the circuit diagram that the present invention strengthens the metal-oxide-semiconductor reference voltage source circuit

Main components and parts explanation

M0-M16: enhancement mode metal-oxide-semiconductor

R1-R3: resistor

Embodiment

Fig. 1 has provided the structural principle block diagram of the reference voltage source circuit for enhancement type MOS tube of being invented.Circuit shown in Figure 2 is the concrete implementation of Fig. 1 principle.The objective of the invention is to realize like this: start-up circuit is used for starting K multiplication reference current circuit, makes it when power supply electrifying, break away from the degeneracy bias point; K multiplication reference current circuit produces a PTAT current source, is that reference voltage circuit provides bias current through mirror image; Reference voltage circuit produces the less reference voltage of temperature coefficient.

After connecting power supply VDD; M1 is that diode connects, its leakage (and grid) current potential between VDD and VDD-Vthp, nmos switch pipe M2 conducting this moment; So M6/M7 breaks away from the state that the grid current potential is VDD; M4/M5 breaks away from the state that the grid current potential is GND, and reference current circuit is able to start, and after this M2 ends.By M8, M9, the differential amplifier that M10 and M11 form with M12 and M13 working frequency building-out capacitor, stablize the output of K multiplication reference current circuit with the PSRR that changes to be apt to the type reference current.The M14 mirror image is stablized the electric current of K multiplication reference current source, and the pressure reduction circuit of constituting for M15 and M16 provides biasing, and resistance R 1 constitutes the pressure reduction modifying factor with the ratio of R2, can adjust the temperature coefficient and the magnitude of voltage of output reference voltage through adjustment ratio.

Reference voltage source circuit for enhancement type MOS tube utilizes the mobility and the threshold voltage of enhancement mode NMOS pipe and enhancement mode PMOS pipe to have different temperature coefficient; Produce two voltages; Mobility and threshold voltage with enhancement mode NMOS pipe and enhancement mode PMOS pipe is relevant respectively, carries out forming stable voltage source output after the temperature compensation.Below we narrate the principle of work of this circuit structure.

General, the temperature characterisitic of metal-oxide-semiconductor threshold voltage can be expressed as:

$V_{\mathrm{thn}}\left(T\right)=V_{\mathrm{thn}}\left(T_0\right)+K_{\mathrm{TN}}(\frac{T}{T_0}-1)---\left(1\right)$

${-V}_{\mathrm{thp}}\left(T\right)={-V}_{\mathrm{thp}}\left(T_0\right)+K_{\mathrm{TP}}(\frac{T}{T_0}-1)---\left(2\right)$

T ₀Be reference temperature, K _TNBe NMOS pipe threshold voltage V _ThnTemperature coefficient, K _TPBe PMOS pipe threshold voltage V _ThpTemperature coefficient.

In addition, the metal-oxide-semiconductor mobility also is a parameter with temperature characterisitic, can be described as:

${\mathrm{\μ}}_n\left(T\right)={\mathrm{\μ}}_n\left(T_0\right){\left(\frac{T}{T_0}\right)}^{-{\mathrm{\β}}_{{\mathrm{\μ}}_n}}---\left(3\right)$

${\mathrm{\μ}}_p\left(T\right)={\mathrm{\μ}}_p\left(T_0\right){\left(\frac{T}{T_0}\right)}^{-{\mathrm{\β}}_{\mathrm{\μp}}}---\left(4\right)$

In the formula (2);

is NMOS pipe transfer rate humidity index,

be PMOS pipe transfer rate humidity index.Mobility has negative temperature coefficient.

M4, M5, M6, M7 produces the positive temperature coefficient (PTC) voltage relevant with enhancement mode NMOS threshold voltage with R3, and as shown in Figure 3, I0 can be expressed as:

$I_0=\frac{2}{{\mathrm{\μ}}_n\left(T\right)C_{\mathrm{ox}}{S}_5}\frac{1}{{R_3}^2}{(1--\frac{1}{\sqrt{K_1}})}^2---\left(5\right)$

K1 is the ratio of M4 and M5 size, S ₅It is the breadth length ratio of M5 pipe.

The electric current of M14 mirror image M7, when the size of M14 was K2 times of M7, I1 was to be expressed as:

I ₁＝K ₂I ₀ (6)

Therefore Vref can be expressed as:

$V_{\mathrm{ref}}=(1+\frac{R_1}{R_2})V_{\mathrm{GS}16}-\left|V_{\mathrm{GS}15}\right|---\left(7\right)$

M15 and M16 are operated in the saturation region, and the resistance value of R1 and R2 is bigger, and the electric current that flows through M15 and M16 all is approximately equal to I1, then has:

$V_{\mathrm{GS}16}=\sqrt{\frac{2I_1}{{\mathrm{\μ}}_n\left(T\right)C_{\mathrm{ox}}{S}_{16}}}+V_{\mathrm{thn}}---\left(8\right)$

$\left|V_{\mathrm{GS}15}\right|=\sqrt{\frac{2I_1}{{\mathrm{\μ}}_p\left(T\right)C_{\mathrm{ox}}{S}_{15}}}+\left|V_{\mathrm{thp}}\right|---\left(9\right)$

Can be expressed as in conjunction with (7), (8) and (9) formula Vref:

$V_{\mathrm{ref}}=(1+\frac{R1}{R2})(\sqrt{\frac{2I_1}{{\mathrm{\μ}}_n\left(T\right)C_{\mathrm{ox}}{S}_{16}}}+V_{\mathrm{thn}})-(\sqrt{\frac{2I_1}{{\mathrm{\μ}}_p\left(T\right)C_{\mathrm{ox}}{S}_{15}}}+|V_{\mathrm{thp}}\left|\right)---\left(10\right)$

$V_{\mathrm{ref}}=[(1+\frac{R1}{R2})\sqrt{\frac{2I_1}{{\mathrm{\μ}}_n\left(T\right)C_{\mathrm{ox}}{S}_{16}}}-\sqrt{\frac{2I_1}{{\mathrm{\μ}}_p\left(T\right)C_{\mathrm{ox}}{S}_{15}}}]+[(1+\frac{R1}{R2})V_{\mathrm{thn}}-|V_{\mathrm{thp}}\left|\right]---\left(11\right)$

Be that two in the first have positive temperature coefficient (PTC) but inequality in the formula (11), if adjustment M5, the parameter of M15 and M16, can make this part is zero at the desired temperatures coefficient; Two of following second portions all have negative temperature coefficient but are inequality, as long as the ratio of adjustment R1 and R2 resistance, can make this part is zero at the desired temperatures coefficient.And can realize Vref output different voltages with different value through the ratio of adjustment R1 and R2 resistance.

The reference voltage source circuit that reference voltage source circuit for enhancement type MOS tube of the present invention is more commonly used has following characteristics that advantage is arranged.

(1) circuit adopts the CMOS technology, and CMOS itself has characteristics such as switching speed is fast, low in energy consumption, and preparation technology is simple.

(2) only use strong type metal-oxide-semiconductor and resistance in the circuit, the depletion type MOS tube that does not need standard CMOS process not have does not need longitudinal P NP pipe yet; Circuit structure is simple; Be easy to the realization on technology and the circuit, under the situation that obtains identical performance, can significantly reduce cost.

(3) reference voltage source circuit for enhancement type MOS tube of the present invention, the change design through circuit parameter can obtain the different output voltage value, according to the needs of system, output voltage values that can design.

Claims (2)

1. reference voltage source circuit for enhancement type MOS tube is provided with:

Start-up circuit is connected in reference current source circuit, to start reference current source circuit;

Reference current source circuit is connected between start-up circuit and the reference voltage generating circuit, is activated circuit and starts, for reference voltage generating circuit provides bias current;

Reference voltage generating circuit is connected with reference current source circuit, for it bias current is provided through mirror image circuit by reference current source circuit, and this circuit produces output reference voltage; It is characterized in that:

Start-up circuit has two NMOS pipes (M0 and M2) and a PMOS pipe (M1) to form; The PMOS pipe (M1) of start-up circuit connects for diode; Source termination power voltage; The drain terminal of a NMOS pipe (M0) connects the drain terminal and the grid end of PMOS pipe (M1), source end ground connection, the drain terminal and the grid end of the grid termination PMOS pipe (M1) of another NMOS pipe (M2);

Reference current source circuit is a K multiplication reference current source circuit, and feedback is improved the sensitivity of reference current to supply voltage in order to improve the output resistance of metal-oxide-semiconductor;

Reference voltage generating circuit comprises mirror image PMOS pipe (M14), source termination power voltage, and grid termination start-up circuit and reference current source circuit are used for the reference current that the mirror image reference current source circuit produced, and think that reference voltage generating circuit provides bias current.

2. strong type metal-oxide-semiconductor reference voltage source circuit according to claim 1 is characterized in that reference voltage generating circuit also comprises:

First resistor (R2), an end ground connection, the grid end of another termination output NMOS (M16) pipe;

Second resistor (R1), the grid end of termination output NMOS (M16) pipe, the source end of another termination output PMOS (M15) pipe;

Output pmos (M15), the grid end links to each other with drain terminal, is connected to output reference voltage;

Output NMOS pipe (M16), drain terminal connects output reference voltage, source end ground connection.

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