CN107689358A - 金属垫结构 - Google Patents

金属垫结构 Download PDF

Info

Publication number
CN107689358A
CN107689358A CN201710284396.0A CN201710284396A CN107689358A CN 107689358 A CN107689358 A CN 107689358A CN 201710284396 A CN201710284396 A CN 201710284396A CN 107689358 A CN107689358 A CN 107689358A
Authority
CN
China
Prior art keywords
metal
top surface
hole
pad structure
gasket
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710284396.0A
Other languages
English (en)
Inventor
胡迪群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CN107689358A publication Critical patent/CN107689358A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03602—Mechanical treatment, e.g. polishing, grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16111—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Gasket Seals (AREA)

Abstract

本发明涉及一种金属垫结构，第一金属垫和第二金属垫配置在封装基材的顶表面上；所述第一金属垫的顶表面与所述第二金属垫的顶表面呈现非平面配置；第一平整金属配置在所述第一金属垫的顶表面上；第二平整金属设置在所述第二金属垫的顶表面上；所述第一平整金属的顶表面与所述第二平整金属的顶表面呈现共平面配置。本发明在所述第一金属垫的顶面上配置有第一平整金属，并且在所述第二金属垫的顶面上配置第二平整金属；第一平整金属和第二平整金属的顶表面，呈现共平面结构，能有效克服不同材料间的热膨胀系数不匹配或是制程误差而导致封装基材弯曲，进而引起焊接不良的问题。本发明还公开了该金属垫结构的制造方法。

Description

金属垫结构
技术领域
本发明涉及一种金属垫结构(pad structure)，特别涉及一种配置在电子组件或是基材上的多个金属垫的表面平整化技术。
背景技术
如图1A所示，电子组件或是封装基材18具有多个金属垫(metal pad)设置在顶侧，为简便起见，图中现有技术的封装基材18中，以P1、P2、P3三个金属垫作为范例说明之。原本希望是共平面的金属垫P1、P2、P3实际上呈现非共平面(non-coplanar)的状态，这个非共平面结构的产生，主要是因为制程误差、不同材料间的热膨胀系数(coefficient of thermalexpansions,CTE)不匹配等问题所引起的。
第一金属垫P1具有第一顶表面T1，第二金属垫P2具有第二顶表面T2，第三金属垫P3具有第三顶表面T3。在封装基材18的顶面T1、T2、T3原拟制成共平面(coplanar)结构，实际上却呈现”非共平面”(non-coplanar)的状态，参考第二水平线HR2；这里是假设封装基材18的底部呈现水平，如第一水平线HR1所示。
防焊层12配置在封装基材18的顶面上，具有第一孔141使得第一金属垫P1的第一顶表面T1裸露；具有第二孔142，使得第二金属垫P2的第二顶表面T2裸露；具有第三孔143，使得第三金属垫P3的第三顶表面T3裸露。
第一水平基准参考线HR1绘制在封装基材18的底侧，作为水平参考，表示封装基材18的底面系呈水平配置。
第二水平基准参考线HR2设置在金属垫P1、P2、P3的上侧，作为水平参考，以表示三个顶表面T1、T2、T3相互之间，并非呈现共平面构造。
如图1B所示，焊锡102设置于芯片10的金属柱101和金属垫P1、P2之间，在封装基材18顶面的非共平面的T1、T2、T3将导致部分焊点因为接触失败而故障。例如，图1B显示右边金属柱101下端焊料102无法接触到金属垫P3的顶表面T3。在焊料重新融合(reflow)之后，芯片10的右边金属柱102将不能电性连接到下方的金属垫P3。
对于高密度薄膜封装基材的电路而言，金属垫相互之间的不平整，甚至几微米的误差，都严重影响到焊接可靠度。特别是当一个高密度薄膜电路，它的金属垫之间的配置间距(pitch)范围分布于2μm-40μm时，金属垫之间这种微小偏差，都将造成电子组件严重的可靠度问题。
现有技术的缺点是，不同材料间的热膨胀系数(Coefficient of ThermalExpansion,CTE)的不匹配，在制程中的加热、冷却等温度变化，导致封装基材18的轻微弯曲，而引起的焊接可靠度问题。
发明内容
现有技术中，封装基材上制作有第一金属垫和第二金属垫，由于制程误差或是热膨胀系数(CTE)不匹配，第一金属垫和第二金属垫在微观下，呈现“非共平面”(non-coplanar)结构，在封装技术更进一步、电路设计准则更细小时，可能造成组件金属脚安装于基材上的金属垫时，产生焊接不良的问题。针对上述问题，根据本发明的实施例，希望提供一种能有效克服不同材料间的热膨胀系数(CTE)不匹配或是制程误差而导致封装基材弯曲，进而引起焊接不良的金属垫结构(pad structure)，并提出该金属垫结构(padstructure)的制造方法。
根据实施例，本发明提供的一种金属垫结构，包括第一金属垫、第二金属垫、第一平整金属和第二平整金属，其中：
第一金属垫和第二金属垫配置在封装基材的顶表面上；
所述第一金属垫的顶表面与所述第二金属垫的顶表面呈现非共平面配置；
第一平整金属配置在所述第一金属垫的顶表面上；
第二平整金属设置在所述第二金属垫的顶表面上；
所述第一平整金属的顶表面与所述第二平整金属的顶表面呈现共平面配置。
根据实施例，本发明提供的一种金属垫结构的制造方法，包括如下步骤：
准备封装基材，所述封装基材具有设置在顶表面上的第一金属垫和第二金属垫，且所述第一金属垫的顶表面与所述第二金属垫的顶表面非共平面配置；
在金属垫的顶表面上施加防焊层，形成在防焊层中的多个孔，每个孔暴露相应的金属垫的顶表面；
施加种子层，覆盖防焊层的顶表面和孔的底面与孔壁表面；
金属从种子层开始生长，使得金属填充在每个孔中，且覆盖于防焊层的顶表面；
去除覆盖在防焊层的顶表面上的金属，去除防焊层上方局部，以将防焊层的顶表面与每个孔中的金属的顶表面制成共平面；
蚀刻金属，以在多个孔内形成共平面的平整金属，每个共平面平整金属设置在相应的金属垫的顶表面上。
相对于现有技术，本发明在所述第一金属垫的顶面上配置有第一平整金属，并且在所述第二金属垫的顶面上配置第二平整金属；第一平整金属和第二平整金属的顶表面，呈现共平面(coplanar)结构，能有效克服不同材料间的热膨胀系数(CTE)不匹配或是制程误差而导致封装基材弯曲，进而引起焊接不良的问题。即使在封装技术更进一步、电路设计准则更细小时，组件金属脚安装于基材上的金属垫时，也不会产生焊接不良的问题。
附图说明
图1是现有技术中电子组件或是封装基材之金属垫(metal pad)的结构示意图。
图2A-2G是本发明金属垫结构的制程图。
图3A-3B是芯片安装在本发明金属垫结构上的结构示意图。
图4A-4B是本发明金属垫结构的孔内结构示意图。
图5A-5B是本发明金属垫结构的另一孔内结构示意图。
其中：10为芯片；101为金属针；18为封装基材；21为焊锡；212为回焊焊锡；22为防焊层；241、242、243为孔；26为种子层；262为金属；263为覆盖层；264为钛；HR1、HR2、HR3为水平参考；L1、L2、L3为平整金属；P1、P2、P3为金属垫；S1、S2、S3为表面处理层(镍-金)；S22、S23为表面处理层(镍-钯-金)；T1、T2、T3为顶面。
具体实施方式
下面结合附图和具体实施例，进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后，本领域技术人员可以对本发明作各种改动或修改，这些等效变化和修改同样落入本发明权利要求所限定的范围。
本技艺将封装基材原本非共平面的第一金属垫和第二金属垫，顶表面制作平整金属层使得平整金属层顶表面呈现共平面状态。封装基材具有第一金属垫和第二金属垫，第一金属垫与第二金属垫的顶表面呈现“非共平面”(non-coplanar)；第一平整金属配置在第一金属垫的顶侧，第二平整金属设置在第二金属垫的顶侧；第一平整金属和第二平整金属制成共平面(coplanar)状态。
图2A-2G显示本发明的金属垫制程。
图2A显示一片薄膜高密度封装基材18，封装基材18的顶表面，具有金属垫P1、P2、P3。第一金属垫P1具有第一顶表面T1、第二金属垫P2具有第二顶表面T2、第三金属垫P3具有第三顶表面T3。其中，第一顶表面T1、第二顶表面T2、与第三顶表面T3呈现非共平面(non-coplanar)状态。
我们在封装基材18的底侧配置第一水平基准参考线HR1作为水平参考基准，以表示封装基材18的底面呈现水平配置。
在金属垫P1、P2、P3的上侧，配置有第二水平基准参考线HR2作为参考基准，以表示三个顶面T1、T2、T3中，至少有两个顶面为非共平面(non-coplanar)构造。
图2B显示设置在封装基材18的顶表面上的防焊层22具有多个孔241、242、243。第一孔241配置在第一金属垫P1的顶侧、第二孔242配置在第二金属垫P2的顶侧、第三孔243配置在第三金属垫P3的顶侧。每个孔241、242、243暴露相应的金属垫P1、P2、P3的顶表面T1、T2、T3。每个孔241、242、243暴露一个面积小于对应金属垫P1、P2、P3的顶表面的面积。
孔241、242、243的孔壁表面制成垂直，使得后续的焊接材料可以被限制在每个孔中，以增强焊点的可靠性。
图2C显示种子层26施加在防焊层22的顶表面、以及孔241、242、243底面及孔壁表面上。种子层26可以是钛/铜(Ti/Cu)，其中，首先沉积钛(Ti)层，然后在钛层的顶表面上沉积一层铜(Cu)。
图2D显示从种子层26生长金属262，使得金属262完全填充在每个孔241、242、243中并覆盖防焊层22的顶表面。
图2E显示平坦化制程
磨除覆盖在防焊层22上方的过多金属263、磨除防焊层22顶部的种子层26、以及磨除部分防焊层22的顶部，使得防焊层22的顶表面和每个孔241、242、243中的金属262的顶表面呈现水平配置。第三水平基准HR3被配置在防焊层22的顶侧上作为水平参考，以显示防焊层22的顶表面和每个孔241、242、243中的金属262的顶表面是呈现共平面(coplanar)配置。
图2D显示蚀刻制程，将金属262向下等量蚀刻，以形成多个平整金属L1、L2、L3，即是平整金属L1、L2、L3系呈现共平面状态。即是，在第一金属垫P1的顶面上形成第一平整金属L1，在第二金属垫P2的顶表面上形成第二平整金属L2，并在第三金属垫P3的顶表面上形成第三平整金属L3。平整金属L1、L2、L3的顶表面呈现共平面(coplanar)状态。第二水平基准参考线HR2被配置在平整金属L1、L2、L3上方附近，作为水平参考，显示平整金属L1、L2、L3的顶表面呈现共平面(coplanar)状态。
在孔内的铜(Cu)金属蚀刻之后，由于钛(Ti)金属层位于铜层之下，种子层(Ti/Cu)中的钛(Ti)留在每个孔241、242、243的孔壁表面上。请参照图4A-4B、以及图5A-5B。
图2G显示在相应的平整金属L1、L2、L3的顶表面上，分别配置表面处理层S1、S2、S3。第一表面处理层S1设置在第一平整金属L1的顶面上、第二表面处理层S2设置在第二平整金属L2的顶面，并且将第三表面处理层S3设置在第三平整金属L3的顶面上。表面处理层S1、S2、S3可以是化学镀镍/金(ENIG或是Ni/Au)，参见图4A-4B；或是化学镀镍/钯/金(ENEPIG或是Ni/Pd/Au)，参见图5A-5B。
图3A-3B显示芯片安装在本发明的金属垫上的状态。
图3A显示芯片10准备安装在封装基材18上。多个金属引脚101配置在芯片10的底侧，金属引脚101用于将芯片10电性耦合到配置在封装基材18的顶面上的金属垫P1、P2、P3。焊料21分別配置在金属引脚101的底部，图3A显示焊料21回焊(reflow)之前的状态。
图3B显示金属引脚101的底部的焊料21回焊(reflow)之后的状态。回焊以后的焊料212，分别将各个金属引脚101连接到相应的金属垫P1、P2、P3上的表面处理层S1、S2、S3。每个孔241、242、243的孔壁，可以选择性的制成垂直面，可以将回焊以后的焊料212限制在孔内，用以增强焊接可靠性。
图4A-4B显示本发明的金属垫结构的孔内结构。
图4A显示表面处理层S2、S3的材料系ENIG(Ni/Au)，设置于金属垫上方。即是：在平整金属L2的上侧，配置有ENIG表面处理层S2、且在平整金属L3的上侧，配置有另一个ENIG表面处理层S3。
图4A显示在前面几个步骤中，使用的种子层26(Ti/Cu)，而在铜金属蚀刻之后，仍有一层钛264停留在孔242、243的孔壁表面上。
图4B显示孔壁表面的钛264，可以选择性地除去，使得防焊层22暴露在孔242、243的孔壁表面。
图5A-5B显示本发明的金属垫结构的孔内结构另一实施例。
图5A显示表面处理层S22、S32的材料系ENEPIG(Ni/Pd/Au)，设置于金属垫上方。即是：在平整金属L2的上侧配置有ENEPIG层S22,且在平整金属L3的上侧配置有另一个ENEPIG层S32。
图5A显示在前几个步骤中使用的种子层26(Ti/Cu)，在铜金属蚀刻之后，有一层钛264停留在孔242、243的孔壁表面上。
图5B显示在孔242、243的孔壁的钛264、243，可以选择性地被去除,使得防焊层22暴露在孔242、243的孔壁表面上。

Claims (20)

1.一种金属垫结构，其特征是，包括第一金属垫、第二金属垫、第一平整金属和第二平整金属，
第一金属垫和第二金属垫配置在封装基材的顶表面上；
所述第一金属垫的顶表面与所述第二金属垫的顶表面呈现非平面配置；
第一平整金属配置在所述第一金属垫的顶表面上；
第二平整金属设置在所述第二金属垫的顶表面上；以及
所述第一平整金属的顶表面与所述第二平整金属的顶表面呈现共平面配置。
2.如权利要求1所述的金属垫结构，其特征是，还包括表面处理层，所述表面处理层设置于平整金属的顶表面。
3.如权利要求2所述的金属垫结构，其特征是，还包括防焊层，所述防焊层配置在所述金属垫的顶面；且所述防焊层具有多个孔，每个孔配置在相应的金属垫的顶表面，包围着所述平整金属与所述表面处理层。
4.如权利要求3所述的金属垫结构，其特征是，每个孔暴露相应金属垫的顶表面。
5.根据权利要求3所述的金属垫结构，其特征是，每个孔暴露一个比相应金属垫的顶表面小的区域。
6.如权利要求3所述的金属垫结构，其特征是，每个表面处理层配置在相应的孔内。
7.根据权利要求3所述的金属垫结构，其特征是，每个平整金属配置在相应的孔内。
8.如权利要求3所述的金属垫结构，其特征是，每个孔都有一个垂直的孔壁墙面。
9.如权利要求2所述的金属垫结构，其特征是，所述表面处理层是化学镀镍金或化学镀镍钯金。
10.如权利要求5所述的金属垫结构，其特征是，还包括钛金属，所述钛金属设置在相应孔的孔壁表面上。
11.一种金属垫结构的制造方法，其特征是，包括如下步骤：
准备封装基材，所述封装基材具有设置在顶表面上的第一金属垫和第二金属垫，且所述第一金属垫的顶表面与所述第二金属垫的顶表面非共平面配置；
在金属垫的顶表面上施加防焊层，形成在防焊层中的多个孔，每个孔暴露相应的金属垫的顶表面；
施加种子层，覆盖防焊层的顶表面和孔的底面与孔壁表面；
金属从种子层开始生长，使得金属填充在每个孔中，且覆盖于防焊层的顶表面；
去除覆盖在防焊层的顶表面上的金属，去除防焊层上方局部，以将防焊层的顶表面与每个孔中的金属的顶表面制成共平面；
蚀刻金属，以在多个孔内形成共平面的平整金属，每个共平面平整金属设置在相应的金属垫的顶表面上。
12.根据权利要求11所述的金属垫结构的制造方法，其特征是，还包括：施加表面处理层在每个平整金属的顶表面上。
13.根据权利要求11所述的金属垫结构的制造方法，其特征是，所述种子层包含钛铜金属。
14.根据权利要求11所述的金属垫结构的制造方法，其特征是，每个孔都有一个垂直的孔壁墙面。
15.根据权利要求11所述的金属垫结构的制造方法，其特征是，每个平整金属配置在相应的孔内。
16.根据权利要求11所述的金属垫结构的制造方法，其特征是，每个孔暴露出一个面积小于相应金属垫的顶表面的面积。
17.根据权利要求12所述的金属垫结构的制造方法，其特征是，所述表面处理层为化学镀镍金或化学镀镍钯金。
18.根据权利要求12所述的金属垫结构的制造方法，其特征是，所述表面处理层配置在相应的孔内。
19.根据权利要求12所述的金属垫结构的制造方法，其特征是，所述表面处理层的顶表面积等于对应的平整金属的顶表面积。
20.根据权利要求14所述的衬金属垫结构的制造方法，其特征是，还包括钛金属，所述钛金属配置在每个孔的孔壁表面。
CN201710284396.0A 2016-08-04 2017-04-27 金属垫结构 Pending CN107689358A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662370835P 2016-08-04 2016-08-04
US62/370,835 2016-08-04

Publications (1)

Publication Number Publication Date
CN107689358A true CN107689358A (zh) 2018-02-13

Family

ID=61072011

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710284396.0A Pending CN107689358A (zh) 2016-08-04 2017-04-27 金属垫结构

Country Status (2)

Country Link
US (1) US10224300B2 (zh)
CN (1) CN107689358A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11488918B2 (en) * 2018-10-31 2022-11-01 Intel Corporation Surface finishes with low rBTV for fine and mixed bump pitch architectures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103635017A (zh) * 2012-08-24 2014-03-12 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
CN103857197A (zh) * 2012-12-04 2014-06-11 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
CN104617003A (zh) * 2013-11-05 2015-05-13 罗伯特·博世有限公司 用于制造倒装芯片电路装置的方法以及倒装芯片电路装置
US20160155702A1 (en) * 2014-12-02 2016-06-02 Subtron Technology Co., Ltd. Package structure and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9059106B2 (en) * 2012-10-31 2015-06-16 International Business Machines Corporation Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103635017A (zh) * 2012-08-24 2014-03-12 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
CN103857197A (zh) * 2012-12-04 2014-06-11 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
CN104617003A (zh) * 2013-11-05 2015-05-13 罗伯特·博世有限公司 用于制造倒装芯片电路装置的方法以及倒装芯片电路装置
US20160155702A1 (en) * 2014-12-02 2016-06-02 Subtron Technology Co., Ltd. Package structure and manufacturing method thereof

Also Published As

Publication number Publication date
US10224300B2 (en) 2019-03-05
US20180040577A1 (en) 2018-02-08

Similar Documents

Publication Publication Date Title
US10535626B2 (en) Structures and methods for low temperature bonding using nanoparticles
KR102492616B1 (ko) 확산 접합을 위한 기판을 제조하는 방법, 및 반도체 패키지와 그 제조 방법
US20170012021A1 (en) Structures and methods for low temperature bonding
US10820426B2 (en) Carrier substrate
KR20120091691A (ko) 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법
US20060231953A1 (en) Structure for mounting semiconductor part in which bump and land portion are hardly detached from each other and method of manufacturing mounting substrate used therein
KR101070098B1 (ko) 인쇄회로기판 및 그의 제조 방법
CN102165582A (zh) 引线框基板及其制造方法以及半导体装置
JP2014183057A (ja) 半導体装置の製造方法および半導体実装基板
CN109844934B (zh) 用于低温接合的结构和方法
JP2014195042A (ja) 基板の反り矯正装置及び基板の反り矯正方法
CN107689358A (zh) 金属垫结构
CN101400216B (zh) 具有焊料突起的布线基板的制造方法
JP5919641B2 (ja) 半導体装置およびその製造方法並びに電子装置
JP2017028156A (ja) 実装構造体及びその製造方法
US20190096845A1 (en) Chip module and stacked structure
JP2014150235A (ja) 半導体装置および半導体装置の製造方法
TWM481486U (zh) 倒裝封裝裝置
JP5479959B2 (ja) はんだバンプを有する配線基板の製造方法、はんだボール搭載用マスク
JP2007073951A (ja) 部材の接合手段及び／又ははんだ付け手段の形成方法
TWI420996B (zh) 印刷電路板及其製造方法
TWI608775B (zh) 焊墊及焊墊製作方法
JP2000232178A (ja) セラミックキャリアとその製造方法
JP2011091091A (ja) 電子部品の実装構造及び実装方法
TWI661759B (zh) 基板結構及其製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180213

WD01 Invention patent application deemed withdrawn after publication