CN107591359A - The method of adhesiveness between array base palte and preparation method thereof, raising film layer - Google Patents
The method of adhesiveness between array base palte and preparation method thereof, raising film layer Download PDFInfo
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- CN107591359A CN107591359A CN201710695063.7A CN201710695063A CN107591359A CN 107591359 A CN107591359 A CN 107591359A CN 201710695063 A CN201710695063 A CN 201710695063A CN 107591359 A CN107591359 A CN 107591359A
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- layer
- array base
- base palte
- drain electrode
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Abstract
The invention provides a kind of preparation method of array base palte, it includes step：One substrate is provided：Grid is formed on substrate；Gate insulator is formed on substrate and grid；Semiconductor material layer is formed on gate insulator；The surface of semiconductor material layer is roughened；Source-drain electrode metal level is formed on semiconductor material layer；Source-drain electrode metal level and semiconductor material layer are exposed, developed and etching processing, to form active layer on gate insulator and the source electrode being spaced and drain electrode are formed on active layer and gate insulator；Passivation layer is formed in active layer, gate insulator, source electrode and drain electrode；The via of exposure drain electrode is formed in the passivation layer；The pixel electrode by via and drain contact is formed over the passivation layer.The present invention can improve the adhesive force of source electrode, drain electrode and active layer by carrying out thick good fortune processing to the surface of active layer, from without the phenomenon that breaks, and then improve the yield of array base palte.
Description
Technical field
The invention belongs to film manufacturing techniques field, specifically, is related to a kind of array base palte and preparation method thereof, improves
The method of adhesiveness between film layer.
Background technology
The making of array base palte can use 4Mask techniques in liquid crystal panel at present, when making active layer and source-drain electrode,
It is to be initially formed gate insulator, semiconductor material layer and source-drain electrode metal level, is then formed simultaneously with by a Mask techniques
Active layer and source-drain electrode.
But in the manufacturing process of semiconductor material layer and source-drain electrode metal level, due to semiconductor material layer and source-drain electrode
The adhesion of metal level is not good enough, so the peeling of source-drain electrode metal level can be caused, so as to cause disconnection problem, and then influences array
The yield of substrate.
The content of the invention
In order to solve the above-mentioned problems of the prior art, it is an object of the invention to provide one kind can improve semiconductor
The method of adhesiveness between array base palte of adhesion of material layer and source-drain electrode metal level and preparation method thereof, raising film layer.
According to an aspect of the present invention, there is provided a kind of preparation method of array base palte, it includes step：One base is provided
Plate：Grid is formed on the substrate；Gate insulator is formed on the substrate and the grid；In the gate insulator
Upper formation semiconductor material layer；The surface of the semiconductor material layer is roughened；In the semiconductor material layer
Upper formation source-drain electrode metal level；The source-drain electrode metal level and the semiconductor material layer are exposed, developed and etched
Processing, to form active layer on the gate insulator and the source electrode being spaced and drain electrode are formed on the active layer；
Passivation layer is formed in the active layer, the gate insulator, the source electrode and the drain electrode；Formed in the passivation layer
The via of the exposure drain electrode；The pixel electrode by the via with the drain contact is formed on the passivation layer.
Further, the method for described " being roughened to the surface of the semiconductor material layer " includes：Utilize
Etching liquid containing hydrofluoric acid is roughened to the surface of the semiconductor material layer.
Further, the semiconductor material layer is made up of non-crystalline silicon.
Further, the method for described " forming grid on the substrate " includes：Grid gold is formed on the substrate
Belong to layer；The gate metal layer is exposed, developed and etching processing, to form the grid.
Further, the method for described " via that the exposure drain electrode is formed in the passivation layer " includes：To described
Passivation layer is exposed, develops and etching processing, to form the via.
Further, described " pixel electrode by the via with the drain contact is formed on the passivation layer "
Method include：Pixel electrode film layer is formed on the passivation layer；The pixel electrode film layer is gone exposure, development and
Etching processing, to form the pixel electrode.
According to another aspect of the present invention, the array that a kind of preparation method by above-mentioned array base palte makes is additionally provided
Substrate.
According to another aspect of the invention, a kind of method for improving the adhesiveness between film layer is provided again, and it includes：There is provided
One substrate；Make on the substrate and form semiconductor film；The surface of the semiconductor film is roughened；Coarse
Change and form metal film on the surface of the semiconductor film of processing.
Further, the method for described " being roughened to the surface of the semiconductor film " includes：Using containing
The etching liquid of hydrofluoric acid is roughened to the surface of the semiconductor film.
Further, the semiconductor film is made up of non-crystalline silicon.
Beneficial effects of the present invention：The present invention by carrying out thick good fortune processing to the surface of active layer, can improve source electrode,
Drain electrode and the adhesive force of active layer, from without the phenomenon that breaks, and then improve the yield of array base palte.
Brief description of the drawings
The following description carried out in conjunction with the accompanying drawings, above and other aspect, feature and the advantage of embodiments of the invention
It will become clearer, in accompanying drawing：
Fig. 1 is the processing procedure figure of the method for the adhesiveness between raising film layer according to an embodiment of the invention；
Fig. 2 is the processing procedure figure of the preparation method of array base palte according to an embodiment of the invention.
Embodiment
Hereinafter, with reference to the accompanying drawings to embodiments of the invention are described in detail.However, it is possible to come in many different forms real
Apply the present invention, and the specific embodiment of the invention that should not be construed as limited to illustrate here.Conversely, there is provided these implementations
Example is in order to explain the principle and its practical application of the present invention, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.
In the accompanying drawings, for the sake of clarity, layer and the thickness in region are exaggerated.Identical label is in entire disclosure and attached
Identical component is represented in figure.
Fig. 1 is the processing procedure figure of the method for the adhesiveness between raising film layer according to an embodiment of the invention.
The method of adhesiveness between raising film layer according to an embodiment of the invention includes：
Step 1：(a) figure in reference picture 1 a, there is provided substrate 110.In the present embodiment, the substrate 110 can be for example
Glass substrate, but the present invention is not restricted to this.
Step 2：(b) figure in reference picture 1, made on substrate 110 and form semiconductor film 120.Further, partly lead
Body film 120 can be made up of non-crystalline silicon (α-Si), but the present invention is not restricted to this.
Step 3：(c) figure in reference picture 1, is roughened to the surface of semiconductor film 120.
Specifically, the etching liquid containing hydrofluoric acid can be utilized to be roughened the surface of semiconductor film 120, but
The present invention is not restricted to this.
Step 4：(d) figure in reference picture 1, metal film is formed on the surface of the semiconductor film 120 after roughening is handled
130。
Specifically, under the vacuum condition of applying argon gas, argon gas is made to carry out glow discharge, at this moment ar atmo is ionized into argon ion
(Ar+), argon ion is in the presence of electric field, the cathode targets for the metal material making for accelerating bombardment to be coated with, the metal of target
Material can be sputtered out and deposit on the surface of the semiconductor film 120 after roughening processing, so as to form metal film 130.
Before deposited metal film 130, the surface of semiconductor film 120 is roughened, semiconductor can be improved
The adhesion of film 120 and metal film 130, such metal film 130 are just not easy to peel off.
The method of adhesiveness between raising film layer above can be used in the making of array base palte.Below will be to array
The preparation method of substrate is described in detail.It should be noted that illustrated by taking amorphous silicon film transistor as an example here,
But the present invention is not restricted to this.
Fig. 2 is the processing procedure figure of the preparation method of array base palte according to an embodiment of the invention.
The preparation method of array base palte according to an embodiment of the invention includes：
Step 1：(a) figure in reference picture 2 a, there is provided substrate 210.In the present embodiment, the substrate 210 can be for example
Glass substrate, but the present invention is not restricted to this.
Step 2：(b) figure in reference picture 2, grid 220 and the grid being connected with grid 220 are formed over the substrate 210
Line (not shown).
Realizing the method for step 2 includes：First, gate metal layer (not shown) is formed over the substrate 210；Secondly, to institute
State gate metal layer to be exposed, develop and etching processing, to form grid 220.
Step 3：(c) figure in reference picture 2, gate insulator is formed on substrate 210, grid 220 and the gate line
230.Gate insulator 230 can be for example silicon nitride layer and/or silicon oxide layer, but the present invention is not restricted to this.
Step 4：(d) figure in reference picture 2, semiconductor material layer 240a is formed on gate insulator 230.In this reality
Apply in example, semiconductor material layer 240a for example can be made up of non-crystalline silicon (α-Si), but the present invention is not restricted to this.
Step 5：(e) figure in reference picture 2, is roughened to semiconductor material layer 240a surface.
The specific method for realizing step 5 is：The etching liquid containing hydrofluoric acid can be utilized to semiconductor material layer 240a's
Surface is roughened, but the present invention is not restricted to this.
Step 6：(f) figure in reference picture 2, source-drain electrode metal level 250a is formed on semiconductor material layer 240a.
Specifically, under the vacuum condition of applying argon gas, argon gas is made to carry out glow discharge, at this moment ar atmo is ionized into argon ion
(Ar+), argon ion is in the presence of electric field, the cathode targets for the metal material making for accelerating bombardment to be coated with, the metal of target
Material can be sputtered out and deposit on the surface of the semiconductor material layer 240a after roughening processing, so as to form source-drain electrode
Metal level 250a.
Step 7：(g) figure in reference picture 2, source-drain electrode metal level 250a and semiconductor material layer 240a are exposed,
Development and etching processing, it is spaced with forming active layer 240 on gate insulator 230 and being formed on active layer 240
Source electrode 251 and drain electrode 252 and the source electrode line (not shown) that is connected with source electrode 251.
Step 8：(h) figure in reference picture 2, in active layer 240, gate insulator 230, source electrode 251, drain electrode 252 and institute
State formation passivation layer 260 on source electrode line.
Step 9：(i) figure in reference picture 2, the via 261 of exposure drain electrode 252 is formed in passivation layer 260.
Specifically, realizing the method for step 9 includes：Passivation layer 260 is exposed, developed and etching processing, to be formed
The via 261.
Step 10：(j) figure in reference picture 2, the picture contacted by via 261 with drain electrode 252 is formed on passivation layer 260
Plain electrode 270.
Specifically, realizing the method for step 10 includes：First, pixel electrode film layer is formed on passivation layer 260 (not show
Go out)；Secondly, the pixel electrode film layer is gone exposure, develop and etching processing, to form pixel electrode 270.
, can by carrying out thick good fortune processing to the surface of active layer in array base palte according to an embodiment of the invention
To improve source electrode, drain electrode and the adhesive force of active layer, from without break phenomenon, and then improve array base palte yield.
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where not departing from the spirit and scope of the present invention limited by claim and its equivalent, can carry out herein form and
Various change in details.
Claims (10)
1. a kind of preparation method of array base palte, it is characterised in that including step：
One substrate is provided：
Grid is formed on the substrate；
Gate insulator is formed on the substrate and the grid；
Semiconductor material layer is formed on the gate insulator；
The surface of the semiconductor material layer is roughened；
Source-drain electrode metal level is formed on the semiconductor material layer；
The source-drain electrode metal level and the semiconductor material layer are exposed, developed and etching processing, with the grid
Active layer is formed on the insulating barrier of pole and the source electrode being spaced and drain electrode are formed on the active layer；
Passivation layer is formed in the active layer, the gate insulator, the source electrode and the drain electrode；
The via of the exposure drain electrode is formed in the passivation layer；
The pixel electrode by the via with the drain contact is formed on the passivation layer.
2. the preparation method of array base palte according to claim 1, it is characterised in that described " to the semi-conducting material
Layer surface be roughened " method include：Using the etching liquid containing hydrofluoric acid to the semiconductor material layer
Surface is roughened.
3. the preparation method of array base palte according to claim 2, it is characterised in that the semiconductor material layer is by amorphous
Silicon is made.
4. the preparation method of array base palte according to claim 1, it is characterised in that described " to be formed on the substrate
The method of grid " includes：
Gate metal layer is formed on the substrate；
The gate metal layer is exposed, developed and etching processing, to form the grid.
5. the preparation method of array base palte according to claim 1, it is characterised in that " in the passivation layer shape
Into the via of the exposure drain electrode " method include：The passivation layer is exposed, developed and etching processing, to be formed
State via.
6. the preparation method of array base palte according to claim 1, it is characterised in that " on the passivation layer shape
Into the pixel electrode by the via and the drain contact " method include：
Pixel electrode film layer is formed on the passivation layer；
The pixel electrode film layer is gone exposure, development and etching processing, to form the pixel electrode.
7. the array base palte that a kind of preparation method of array base palte as described in any one of claim 1 to 6 makes.
A kind of 8. method for improving the adhesiveness between film layer, it is characterised in that including：
One substrate is provided；
Make on the substrate and form semiconductor film；
The surface of the semiconductor film is roughened；
Metal film is formed on the surface of the semiconductor film of roughening processing.
9. the method according to claim 8 for improving the adhesiveness between film layer, it is characterised in that described " partly to be led to described
The surface of body film is roughened " method include：Table using the etching liquid containing hydrofluoric acid to the semiconductor film
Face is roughened.
10. it is according to claim 9 improve film layer between adhesiveness method, it is characterised in that the semiconductor film by
Non-crystalline silicon is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710695063.7A CN107591359A (en) | 2017-08-15 | 2017-08-15 | The method of adhesiveness between array base palte and preparation method thereof, raising film layer |
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| CN201710695063.7A CN107591359A (en) | 2017-08-15 | 2017-08-15 | The method of adhesiveness between array base palte and preparation method thereof, raising film layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110335849A (en) * | 2019-06-25 | 2019-10-15 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and preparation method thereof |
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| CN1684273A (en) * | 2004-04-14 | 2005-10-19 | Nec液晶技术株式会社 | Thin film transistor and its producing method |
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| JP2014181373A (en) * | 2013-03-19 | 2014-09-29 | Jx Nippon Mining & Metals Corp | SILICON WAFER ON WHICH Ni AND Ni ALLOY FILM IS FORMED, FORMING METHOD OF Ni AND Ni ALLOY FILM ON Si WAFER, SURFACE ROUGHENING PROCESSING LIQUID TO SURFACE OF Si WAFER IN FORMING Ni AND Ni ALLOY FILM, AND SURFACE ROUGHENING PROCESSING METHOD OF THE SURFACE |
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| JPS5740943A (en) * | 1980-08-22 | 1982-03-06 | Mitsubishi Electric Corp | Semiconductror device |
| JPH09107101A (en) * | 1995-10-09 | 1997-04-22 | Fujitsu Ltd | Fabrication of semiconductor device |
| US20010015440A1 (en) * | 2000-02-18 | 2001-08-23 | Toshihide Tsubata | Thin film transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110335849A (en) * | 2019-06-25 | 2019-10-15 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and preparation method thereof |
| CN110335849B (en) * | 2019-06-25 | 2021-11-02 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and manufacturing method thereof |
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