CN107369614A - The preparation method of metal film plating method, thin film transistor (TFT) and array base palte - Google Patents
The preparation method of metal film plating method, thin film transistor (TFT) and array base palte Download PDFInfo
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- CN107369614A CN107369614A CN201710668127.4A CN201710668127A CN107369614A CN 107369614 A CN107369614 A CN 107369614A CN 201710668127 A CN201710668127 A CN 201710668127A CN 107369614 A CN107369614 A CN 107369614A
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- 239000002184 metal Substances 0.000 title claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 84
- 239000010408 film Substances 0.000 title claims abstract description 43
- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000007747 plating Methods 0.000 title claims abstract description 20
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 8
- 239000012212 insulator Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 3
- 230000002045 lasting effect Effects 0.000 abstract description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 18
- 229910052786 argon Inorganic materials 0.000 description 12
- -1 argon ion Chemical class 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02697—Forming conducting materials on a substrate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a kind of metal film plating method, it includes step：One substrate is provided；It is coated with to form the first metallic diaphragm on the substrate；After suspending the scheduled time, it is coated with to form the second metallic diaphragm on first metallic diaphragm；Wherein, the plating prepared material of first metallic diaphragm is identical with the plating prepared material of second metallic diaphragm.Present invention also offers a kind of thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof.The present invention is further continued for deposited metal film the pause scheduled time during metal film deposition, metal film can be prevented because of lasting film forming and temperature rise, surface detail occurs so as to avoid metallic film surface from being oxidized, and then improve the quality of metal film.
Description
Technical field
The invention belongs to film manufacturing techniques field, specifically, is related to a kind of metal film plating method, thin film transistor (TFT)
With the preparation method of array base palte.
Background technology
The manufacturing process of metal film is at present：Under the vacuum condition of argon filling (Ar) gas, argon gas is set to carry out glow discharge, this
When ar atmo be ionized into argon ion (Ar+), in the presence of electric field, acceleration bombardment is made argon ion with the metal material being coated with
Cathode targets, the metal material of target can be sputtered out and deposit on glass substrate, so as to form metal film.
For metal film in deposition process, the metal material that sputters is bombardment on glass substrate and then depositing, with
The increase of metal film thickness, metal film temperature also increases, so as to which the surface of the metal film of high temperature is easily oxidized and occurred
Surface detail, so as to influence the quality of metal film.
The content of the invention
In order to solve the above-mentioned problems of the prior art, it is an object of the invention to provide one kind can avoid metal film
There is the metal film plating method of surface detail, thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof in surface.
According to an aspect of the present invention, there is provided a kind of metal film plating method, it includes step：One substrate is provided；
It is coated with to form the first metallic diaphragm on the substrate；After suspending the scheduled time, it is coated with to be formed on first metallic diaphragm
Second metallic diaphragm；Wherein, the plating prepared material of first metallic diaphragm is identical with the plating prepared material of second metallic diaphragm.
According to another aspect of the present invention, a kind of preparation method of thin film transistor (TFT) is additionally provided, it includes step：There is provided
One substrate：First grid metal level is formed on the substrate；After suspending the scheduled time, on the first grid metal level
Making forms second grid metal level；The second grid metal level and the first grid metal level are exposed, developed
And etching processing, to form grid；Gate insulator is formed on the substrate and the grid；On the gate insulator
Form the active layer relative with the grid；Formed on the active layer and the gate insulator source electrode that is spaced and
Drain electrode.
According to another aspect of the invention, a kind of the thin of preparation method making by above-mentioned thin film transistor (TFT) is provided again
Film transistor.
According to another aspect of the invention, a kind of preparation method of array base palte is provided again, and it includes step：There is provided one
Substrate：First grid metal level is formed on the substrate；After suspending the scheduled time, made on the first grid metal level
Form second grid metal level；The second grid metal level and the first grid metal level are exposed, develop and
Etching processing, to form grid；Gate insulator is formed on the substrate and the grid；The shape on the gate insulator
Into the active layer relative with the grid；The source electrode being spaced and leakage are formed on the active layer and the gate insulator
Pole；Passivation layer is formed in the active layer, the gate insulator, the source electrode and the drain electrode；In the passivation layer
Form the via of the exposure drain electrode；Formed on the passivation layer by the pixel of the via and drain contact electricity
Pole.
According to another aspect of the invention, the array that a kind of preparation method by above-mentioned array base palte makes is provided again
Substrate.
Further, described " forming the source electrode being spaced and drain electrode on the active layer and the gate insulator "
Method include step：The first source-drain electrode metal level is formed on the active layer and the gate insulator；The pre- timing of pause
Between after, the second source-drain electrode metal level is formed on the first source-drain electrode metal level；To the first source-drain electrode metal level and
The second source-drain electrode metal level is exposed, develops and etching processing, to form the source electrode and the drain electrode.
Further, the scheduled time is 10 seconds to 20 seconds.
Beneficial effects of the present invention：The present invention is further continued for deposited metal the pause scheduled time during metal film deposition
Film, can prevent metal film because of lasting film forming and temperature raises, and surface occur so as to avoid metallic film surface from being oxidized
Decorative pattern, and then improve the quality of metal film.
Brief description of the drawings
The following description carried out in conjunction with the accompanying drawings, above and other aspect, feature and the advantage of embodiments of the invention
It will become clearer, in accompanying drawing：
Fig. 1 is the processing procedure figure of metal film plating method according to an embodiment of the invention；
Fig. 2 is the processing procedure figure of the preparation method of thin film transistor (TFT) according to an embodiment of the invention；
Fig. 3 is the processing procedure figure of the preparation method of array base palte according to an embodiment of the invention；
Fig. 4 is the processing procedure figure of the preparation method of source electrode according to an embodiment of the invention and drain electrode.
Embodiment
Hereinafter, with reference to the accompanying drawings to embodiments of the invention are described in detail.However, it is possible to come in many different forms real
Apply the present invention, and the specific embodiment of the invention that should not be construed as limited to illustrate here.Conversely, there is provided these implementations
Example is in order to explain the principle and its practical application of the present invention, so that others skilled in the art are it will be appreciated that the present invention
Various embodiments and be suitable for the various modifications of specific intended application.
In the accompanying drawings, for the sake of clarity, layer and the thickness in region are exaggerated.Identical label is in entire disclosure and attached
Identical component is represented in figure.
Fig. 1 is the processing procedure figure of metal film plating method according to an embodiment of the invention.
Metal film plating method according to an embodiment of the invention includes：
Step 1：(a) figure in reference picture 1 a, there is provided substrate 110.In the present embodiment, the substrate 110 can be for example
Glass substrate, but the present invention is not restricted to this.
Step 2：(b) figure in reference picture 1, made on substrate 110 and form the first metallic diaphragm 120.
Specifically, under the vacuum condition of applying argon gas, argon gas is made to carry out glow discharge, at this moment ar atmo is ionized into argon ion
(Ar+), argon ion is in the presence of electric field, the cathode targets for the metal material making for accelerating bombardment to be coated with, the metal of target
Material can be sputtered out and deposit on substrate 110, so as to form the first metallic diaphragm 120.
Step 3：(c) figure in reference picture 1, after suspending the scheduled time, it is coated with to be formed on the first metallic diaphragm 120
Second metallic diaphragm 130；Wherein, the plating prepared material phase of the plating prepared material and the second metallic diaphragm 130 of the first metallic diaphragm 120
Together.
Specifically, after the scheduled time of the first metallic diaphragm 120 has been made, the vacuum condition in applying argon gas is continued
Under, argon gas is carried out glow discharge, at this moment ar atmo is ionized into argon ion (Ar+), argon ion accelerates to bang in the presence of electric field
The cathode targets that the metal material for hitting to be coated with makes, the metal material of target can be sputtered out and deposit to the first metal film
On layer 120, so as to form the second metallic diaphragm 130.
In this embodiment, it is preferred that the scheduled time is 10 seconds to 20 seconds.If because pause time it is oversize,
The Wen Duxiajiang of the metallic diaphragm 120 of substrate 110 and first will be caused too many, so as to when forming the second metallic diaphragm 130 by
Decline too many in temperature and cause the absorption affinity between the second metallic diaphragm 130 and the first metallic diaphragm 120 to decline, in turn result in
Second metallic diaphragm, 130 caducous phenomenon.However, if the time of pause is too short, temperature decline degree is inadequate, the second metal
The surface of film layer 130 is still easily oxidized and surface detail occurs, so as to influence the quality of the second metallic diaphragm 130.
More than the plating method of metal film can be used in being coated with for metallic diaphragm in the thin film transistor (TFT) of array base palte.
The preparation method of array substrate and thin film transistor (TFT) is described in detail below.It should be noted that it is with amorphous here
Illustrated exemplified by silicon thin film transistor, but the present invention is not restricted to this, such as metal oxide thin-film transistor or low
Warm polycrystalline SiTFT etc. is applicable.
Fig. 2 is the processing procedure figure of the preparation method of thin film transistor (TFT) according to an embodiment of the invention.
The preparation method of thin film transistor (TFT) according to an embodiment of the invention includes：
Step 1：(a) figure in reference picture 2 a, there is provided substrate 210.In the present embodiment, the substrate 210 can be for example
Glass substrate, but the present invention is not restricted to this.
Step 2：(b) figure in reference picture 2, first grid metal level 220a is formed over the substrate 210.
Step 3：(c) figure in reference picture 2, after suspending the scheduled time, shape is made on first grid metal level 220a
Into second grid metal level 220b.Further, the scheduled time can be 10 seconds to 20 seconds.
Step 4：(d) figure in reference picture 2, second grid metal level 220b and first grid metal level 220a is carried out
Exposure, development and etching processing, to form grid 220.
Step 5：(e) figure in reference picture 2, gate insulator 230 is formed on substrate 210 and grid 220.Grid is exhausted
Edge layer 230 can be for example silicon nitride layer and/or silicon oxide layer, but the present invention is not restricted to this.
Step 6：(f) figure in reference picture 2, the active layer relative with grid 220 is formed on gate insulator 230
240.In the present embodiment, active layer 240 can be for example non-crystalline silicon (α-Si) layer, but the present invention is not restricted to this.
Step 7：(g) figure in reference picture 2, the source being spaced is formed on active layer 240 and gate insulator 230
Pole 251 and drain electrode 252.
Fig. 3 is the processing procedure figure of the preparation method of array base palte according to an embodiment of the invention.
The preparation method of array base palte according to an embodiment of the invention includes：
Step 1：(a) figure in reference picture 3 a, there is provided substrate 210.In the present embodiment, the substrate 210 can be for example
Glass substrate, but the present invention is not restricted to this.
Step 2：(b) figure in reference picture 3, first grid metal level 220a is formed over the substrate 210.
Step 3：(c) figure in reference picture 3, after suspending the scheduled time, shape is made on first grid metal level 220a
Into second grid metal level 220b.Further, the scheduled time can be 10 seconds to 20 seconds.
Step 4：(d) figure in reference picture 3, second grid metal level 220b and first grid metal level 220a is carried out
Exposure, development and etching processing, with the gate line (not shown) for forming grid 220 and being connected with grid 220.
Step 5：(e) figure in reference picture 3, gate insulator is formed on substrate 210, grid 220 and the gate line
230.Gate insulator 230 can be for example silicon nitride layer and/or silicon oxide layer, but the present invention is not restricted to this.
Step 6：(f) figure in reference picture 3, the active layer relative with grid 220 is formed on gate insulator 230
240.In the present embodiment, active layer 240 can be for example non-crystalline silicon (α-Si) layer, but the present invention is not restricted to this.
Step 7：(g) figure in reference picture 3, the source being spaced is formed on active layer 240 and gate insulator 230
Pole 251 and drain electrode 252 and the source electrode line (not shown) being connected with source electrode 251.
Step 8：(h) figure in reference picture 3, in active layer 240, gate insulator 230, source electrode 251, drain electrode 252 and institute
State formation passivation layer 260 on source electrode line.
Step 9：(i) figure in reference picture 3, the via 261 of exposure drain electrode 252 is formed in passivation layer 260.
Step 10：(j) figure in reference picture 3, the picture contacted by via 261 with drain electrode 252 is formed on passivation layer 260
Plain electrode 270.
In addition, further, the preparation method of step seven and/or array base palte in the preparation method of thin film transistor (TFT)
The preparation method of source electrode 251 and drain electrode 252 in step 7 can also use and the identical preparation method of grid 220.
Fig. 4 is the processing procedure figure of the preparation method of source electrode according to an embodiment of the invention and drain electrode.
Source electrode according to an embodiment of the invention and the preparation method of drain electrode include：
Step 1：(a) figure in reference picture 4, the first source-drain electrode gold is formed on active layer 240 and gate insulator 230
Belong to layer 250a.
Step 2：(b) figure in reference picture 4, after suspending the scheduled time, formed on the first source-drain electrode metal level 250a
Second source-drain electrode metal level 250b.Further, the scheduled time can be 10 seconds to 20 seconds.
Step 3：(c) figure in reference picture 4, to the first source-drain electrode metal level 250a and the second source-drain electrode metal level 250b
It is exposed, develops and etching processing, forms source electrode 251 and drain electrode 252.It should be noted that in the making of array base palte
In method, in this step, also source electrode line is formed simultaneously.
In summary, according to an embodiment of the invention, the pause scheduled time is further continued for sinking during metal film deposition
Product metal film, can prevent metal film because of lasting film forming and temperature raises, and so as to avoid metallic film surface from being oxidized
Existing surface detail, and then improve the quality of metal film.
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where not departing from the spirit and scope of the present invention limited by claim and its equivalent, can carry out herein form and
Various change in details.
Claims (10)
1. a kind of metal film plating method, it is characterised in that including step：
One substrate is provided；
It is coated with to form the first metallic diaphragm on the substrate；
After suspending the scheduled time, it is coated with to form the second metallic diaphragm on first metallic diaphragm；Wherein, first gold medal
The plating prepared material for belonging to film layer is identical with the plating prepared material of second metallic diaphragm.
2. metal film plating method according to claim 1, it is characterised in that the scheduled time is 10 seconds to 20 seconds.
3. a kind of preparation method of thin film transistor (TFT), it is characterised in that including step：
One substrate is provided：
First grid metal level is formed on the substrate；
After suspending the scheduled time, made on the first grid metal level and form second grid metal level；
The second grid metal level and the first grid metal level are exposed, developed and etching processing, to form grid
Pole；
Gate insulator is formed on the substrate and the grid；
The active layer relative with the grid is formed on the gate insulator；
The source electrode being spaced and drain electrode are formed on the active layer and the gate insulator.
4. the preparation method of thin film transistor (TFT) according to claim 3, it is characterised in that it is described " in the active layer and
The source electrode being spaced and drain electrode are formed on the gate insulator " method include step：
The first source-drain electrode metal level is formed on the active layer and the gate insulator；
After suspending the scheduled time, the second source-drain electrode metal level is formed on the first source-drain electrode metal level；
The first source-drain electrode metal level and the second source-drain electrode metal level are exposed, developed and etching processing, with shape
Into the source electrode and the drain electrode.
5. the preparation method of the thin film transistor (TFT) according to claim 3 or 4, it is characterised in that the scheduled time is 10
Second was to 20 seconds.
6. the thin film transistor (TFT) that a kind of preparation method of thin film transistor (TFT) as described in any one of claim 3 to 5 makes.
7. a kind of preparation method of array base palte, it is characterised in that including step：
One substrate is provided：
First grid metal level is formed on the substrate；
After suspending the scheduled time, made on the first grid metal level and form second grid metal level；
The second grid metal level and the first grid metal level are exposed, developed and etching processing, to form grid
Pole；
Gate insulator is formed on the substrate and the grid；
The active layer relative with the grid is formed on the gate insulator；
The source electrode being spaced and drain electrode are formed on the active layer and the gate insulator；
Passivation layer is formed in the active layer, the gate insulator, the source electrode and the drain electrode；
The via of the exposure drain electrode is formed in the passivation layer；
The pixel electrode by the via with the drain contact is formed on the passivation layer.
8. the preparation method of array base palte according to claim 7, it is characterised in that described " in the active layer and institute
State and the source electrode being spaced and drain electrode formed on gate insulator " method include step：
The first source-drain electrode metal level is formed on the active layer and the gate insulator；
After suspending the scheduled time, the second source-drain electrode metal level is formed on the first source-drain electrode metal level；
The first source-drain electrode metal level and the second source-drain electrode metal level are exposed, developed and etching processing, with shape
Into the source electrode and the drain electrode.
9. the preparation method of the array base palte according to claim 7 or 8, it is characterised in that the scheduled time is 10 seconds
To 20 seconds.
10. the array base palte that a kind of preparation method of array base palte as described in any one of claim 7 to 9 makes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710668127.4A CN107369614A (en) | 2017-08-07 | 2017-08-07 | The preparation method of metal film plating method, thin film transistor (TFT) and array base palte |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710668127.4A CN107369614A (en) | 2017-08-07 | 2017-08-07 | The preparation method of metal film plating method, thin film transistor (TFT) and array base palte |
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| CN107369614A true CN107369614A (en) | 2017-11-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0782040A2 (en) * | 1995-12-28 | 1997-07-02 | Samsung Electronics Co., Ltd. | Method for manufacturing liquid crystal display |
| CN101410952A (en) * | 2006-01-31 | 2009-04-15 | 东京毅力科创株式会社 | Method for seed film formation, plasma film forming apparatus, and memory medium |
| CN103489882A (en) * | 2013-10-17 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, preparation method for same and display device |
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2017
- 2017-08-07 CN CN201710668127.4A patent/CN107369614A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0782040A2 (en) * | 1995-12-28 | 1997-07-02 | Samsung Electronics Co., Ltd. | Method for manufacturing liquid crystal display |
| CN101410952A (en) * | 2006-01-31 | 2009-04-15 | 东京毅力科创株式会社 | Method for seed film formation, plasma film forming apparatus, and memory medium |
| CN103489882A (en) * | 2013-10-17 | 2014-01-01 | 京东方科技集团股份有限公司 | Array substrate, preparation method for same and display device |
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