CN103700670A - Array substrate and manufacturing method thereof and display device - Google Patents
Array substrate and manufacturing method thereof and display device Download PDFInfo
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- CN103700670A CN103700670A CN201310713498.1A CN201310713498A CN103700670A CN 103700670 A CN103700670 A CN 103700670A CN 201310713498 A CN201310713498 A CN 201310713498A CN 103700670 A CN103700670 A CN 103700670A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 95
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 187
- 230000004888 barrier function Effects 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 35
- 239000000203 mixture Substances 0.000 claims description 25
- 239000010410 layer Substances 0.000 description 153
- 238000002161 passivation Methods 0.000 description 40
- 229910052751 metal Inorganic materials 0.000 description 29
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- 229910044991 metal oxide Inorganic materials 0.000 description 17
- 150000004706 metal oxides Chemical class 0.000 description 17
- 230000000694 effects Effects 0.000 description 14
- 239000010408 film Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 238000010276 construction Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000002207 thermal evaporation Methods 0.000 description 5
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- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
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- 229910052779 Neodymium Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
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- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
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- 239000011787 zinc oxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention provides an array substrate and a manufacturing method thereof, and a display device, and belongs to the technical field of display. The manufacturing method of the array substrate comprises the following steps: before making a conductive pattern, compositing an insulating layer below the conductive pattern by using a mask plate for making the conductive pattern; depositing a conducting layer, and compositing the conducting layer by using the mask plate for making the conductive pattern to form the conductive pattern. By adopting the technical scheme of the invention, residues on the periphery of the etched conductive pattern can be eliminated, and the influences of etching residues on the performance of the display device are reduced.
Description
Technical field
The present invention relates to Display Technique field, refer to especially a kind of array base palte and preparation method thereof, display unit.
Background technology
At LCD(Liquid Crystal Display, liquid crystal display) array base palte and OLED(Organic Light-Emitting Diode, Organic Light Emitting Diode) in the manufacturing process of array base palte, the inhomogeneous display performance that will pair array substrate of conductive pattern etching impacts, for example array base palte is usually used tin indium oxide (ITO) to make pixel electrode, but when deposition ITO, the temperature easily causing because of long-term sputter raises and forms ITO crystallization, thickness with ito thin film increases, this phenomenon is further obvious, because the etching of crystalline state ITO is more difficult, therefore when the figure of the pixel electrode of etching ito thin film formation subsequently, easily there is ITO residual.
Be illustrated in figure 1 more common array base-plate structure, on underlay substrate 4, make the making of carrying out passivation layer 2 and ITO layer 1 after each rete 3 of array base palte comprise gate electrode, gate insulation layer, active layer, source-drain electrode layer etc.ITO is after composition technique, and desirable situation as shown in Figure 2, is also adjacent ITO graphics field at the region of adjacent reservation ito thin film 7() between the ITO rete in region 5 of removal ito thin film should be completely removed, expose passivation layer below.But, when etching ITO layer forms pixel electrode figure, because the etching of crystalline state ITO is more difficult, as shown in Figure 3, often occur the incomplete situation of etching, in region, 7 will retain ito thin film formation electrode, passivation layer below removal ito thin film being exposed in region 5, but because the etching difficulty of crystalline state ITO is greater than the etching difficulty of normality ITO, in region, 7 neighboring area 6, still can leave over ITO crystal grain.If the ITO crystal grain that the neighboring area 6 in region 7 is left over too much can make to be electrically connected between the pixel electrode of neighbor, have a strong impact on the electric property of array base palte, increase the uncontrollability of array base palte overall performance, finally will affect the display effect of display unit.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, display unit, can guarantee the periphery noresidue of conductive pattern after etching, has reduced the impact of etching residue on the performance of display unit.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme as follows:
On the one hand, provide a kind of manufacture method of array base palte, comprising:
Before making conductive pattern, utilize the mask plate of making conductive pattern to carry out composition to the insulating barrier under described conductive pattern;
Depositing conducting layer, the mask plate of utilization making conductive pattern carries out composition to described conductive layer and forms described conductive pattern.
Further, the mask plate that conductive pattern is made in described utilization carries out composition to the insulating barrier under described conductive pattern and comprises:
Form the first figure of insulating barrier;
On the substrate of the first figure that is formed with described insulating barrier, apply photoresist, utilize the mask plate of making conductive pattern to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to described conductive pattern region, photoresist not reserve area corresponding to the region beyond described conductive pattern, carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not partial insulative layer of reserve area of photoresist, peel off remaining photoresist, form the second graph corresponding with described conductive pattern of described insulating barrier, the edge of described second graph has slope.
Further, the thickness of insulating layer under described conductive pattern is greater than the thickness of insulating layer of other location.
Further, the mask plate that conductive pattern is made in described utilization carries out composition to described conductive layer and forms described conductive pattern and comprise:
Depositing conducting layer on described insulating barrier;
On described conductive layer, apply photoresist, utilize the mask plate of making conductive pattern to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to described conductive pattern region, and photoresist not reserve area, corresponding to the region beyond described conductive pattern, carries out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not conductive layer of reserve area of photoresist completely, peel off remaining photoresist, form described conductive pattern.
Further, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
The array base palte that the embodiment of the present invention also provides a kind of utilization to make with said method, the insulating barrier under at least one conductive pattern includes the insulating barrier figure corresponding with described conductive pattern, the justified margin of described conductive pattern and described insulating barrier figure.
Further, the thickness of insulating layer under described conductive pattern is greater than the thickness of insulating layer of other location
Further, the marginal existence of the insulating barrier figure corresponding with described conductive pattern has slope.
Further, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
The embodiment of the present invention also provides a kind of display unit, comprises array base palte as above.
Embodiments of the invention have following beneficial effect:
In such scheme, before making conductive pattern, utilize the mask plate of making conductive pattern to carry out composition to the insulating barrier under conductive pattern, make the insulating barrier under conductive pattern there is the insulating barrier figure corresponding with conductive pattern.Afterwards on insulating barrier during depositing electrically conductive rete, due to the marginal existence slope at insulating barrier figure, the conductive film layer at place, slope is very thin, the process of etching conductive figure is become than being easier to, even if the conductive film layer of below, slope has residual, also will be stopped by the slope of noresidue, play good isolated effect, at the periphery of conductive pattern, form the isolation strip of noresidue, the part of having separated conductive pattern and etching residue, the effect of etching is embodied, reduced the impact of etching residue on the performance of display unit.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of existing array base palte;
Schematic top plan view when Fig. 2 is the noresidue of ITO etching;
Fig. 3 is that ITO is etched with schematic top plan view when residual;
Fig. 4 is the schematic flow sheet of the manufacture method of embodiment of the present invention array base palte;
Fig. 5 is the schematic cross-section after embodiment of the present invention array base palte deposit transparent conductive layer;
Fig. 6 is the schematic top plan view of embodiment of the present invention ITO marginal portion.
Reference numeral
1 transparency conducting layer 2 passivation layers
3 comprise each retes such as gate electrode, gate insulation layer, active layer, source-drain electrode layer
The region that 4 underlay substrates 5 are removed ito thin film
The neighboring area 7 in 6 regions 7 retains the region of ito thin film
8 isolation strip 9 etching residue part 10 pixel electrodes
Embodiment
For technical problem, technical scheme and advantage that embodiments of the invention will be solved are clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The problem that embodiments of the invention can impact the performance of display unit for the etching residue of conductive pattern periphery in prior art, a kind of array base palte and preparation method thereof, display unit are provided, can guarantee the periphery noresidue of conductive pattern after etching, reduce the impact of etching residue on the performance of display unit.
The embodiment of the present invention provides a kind of manufacture method of array base palte, and as shown in Figure 4, the present embodiment comprises:
Step 101: before making conductive pattern, utilize the mask plate of making conductive pattern to carry out composition to the insulating barrier under described conductive pattern;
Step 102: depositing conducting layer, the mask plate of utilization making conductive pattern carries out composition to described conductive layer and forms described conductive pattern.
The manufacture method of array base palte of the present invention, before making conductive pattern, utilizes the mask plate of making conductive pattern to carry out composition to the insulating barrier under conductive pattern, makes the insulating barrier under conductive pattern have the insulating barrier figure corresponding with conductive pattern.Afterwards on insulating barrier during depositing electrically conductive rete, due to the marginal existence slope at insulating barrier figure, the conductive film layer at place, slope is very thin, the process of etching conductive figure is become than being easier to, even if the conductive film layer of below, slope has residual, also will be stopped by the slope of noresidue, play good isolated effect, at the periphery of conductive pattern, form the isolation strip of noresidue, the part of having separated conductive pattern and etching residue, the effect of etching is embodied, reduced the impact of etching residue on the performance of display unit.
Further, the mask plate that conductive pattern is made in described utilization carries out composition to the insulating barrier under described conductive pattern and comprises:
Form the first figure of insulating barrier;
On the substrate of the first figure that is formed with described insulating barrier, apply photoresist, utilize the mask plate of making conductive pattern to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to described conductive pattern region, photoresist not reserve area corresponding to the region beyond described conductive pattern, carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not partial insulative layer of reserve area of photoresist, peel off remaining photoresist, form the second graph corresponding with described conductive pattern of described insulating barrier, the edge of described second graph has slope.
Further, the thickness of insulating layer under described conductive pattern is greater than the thickness of insulating layer of other location.
Further, the mask plate that conductive pattern is made in described utilization carries out composition to described conductive layer and forms described conductive pattern and comprise:
Depositing conducting layer on described insulating barrier;
On described conductive layer, apply photoresist, utilize the mask plate of making conductive pattern to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to described conductive pattern region, and photoresist not reserve area, corresponding to the region beyond described conductive pattern, carries out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not conductive layer of reserve area of photoresist completely, peel off remaining photoresist, form described conductive pattern.
Further, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
Particularly, described conductive pattern can be source electrode, drain electrode, data wire, described array base palte includes the insulating barrier being positioned under source electrode, drain electrode and data wire, described insulating barrier can be etching barrier layer, described before making conductive pattern, the mask plate of utilization making conductive pattern carries out composition to the insulating barrier under described conductive pattern and comprises:
Before the figure of the source of making electrode, drain electrode and data wire, utilize the mask plate of making source electrode, drain electrode and data wire to carry out composition to the etching barrier layer under described source electrode, drain electrode and data wire, etch away partial etching barrier layer, make etching barrier layer include the figure of corresponding source electrode, drain electrode and data wire;
The mask plate that conductive pattern is made in described utilization carries out composition to described conductive layer and forms described conductive pattern and comprise:
Sedimentary origin electrode, drain electrode, data wire metal layer on etching barrier layer;
At described source electrode, drain electrode, on data wire metal layer, apply photoresist, utilize making source electrode, the mask plate of drain electrode and data wire exposes to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to source electrode, drain electrode and data wire region, photoresist not reserve area corresponding to source electrode, region beyond drain electrode data wire, carry out development treatment, the photoresist not photoresist of reserve area is completely removed, the photoresist thickness of photoresist reserve area remains unchanged,
By etching technics, etch away photoresist not source electrode, drain electrode, the data wire metal layer of reserve area completely, peel off remaining photoresist, form the figure of source electrode, drain electrode and data wire.
Further, described array base palte includes the insulating barrier being positioned under gate electrode and grid line, described conductive pattern can be the figure of gate electrode and grid line, insulating barrier under described conductive pattern can be the resilient coating under gate electrode and grid line, described before making conductive pattern, the mask plate of utilization making conductive pattern carries out composition to the insulating barrier under described conductive pattern and comprises:
Before making the figure of gate electrode and grid line, utilize the mask plate of making gate electrode and grid line to carry out composition to the resilient coating under described gate electrode and grid line, etch away partial buffer layer, make resilient coating include the figure of corresponding gate electrode and grid line;
The mask plate that conductive pattern is made in described utilization carries out composition to described conductive layer and forms described conductive pattern and comprise:
On resilient coating, deposit grid metal level;
On described grid metal level, apply photoresist, utilize the mask plate of making gate electrode and grid line to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to gate electrode and grid line region, and photoresist not reserve area, corresponding to the region beyond gate electrode and grid line, carries out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not grid metal level of reserve area of photoresist completely, peel off remaining photoresist, form the figure of gate electrode and grid line.
Further, described array base palte includes the passivation layer being positioned under pixel electrode, described conductive pattern can be the figure of pixel electrode, insulating barrier under described conductive pattern can be the passivation layer under pixel electrode, described before making conductive pattern, the mask plate of utilization making conductive pattern carries out composition to the insulating barrier under described conductive pattern and comprises:
Before making the figure of pixel electrode, utilize the mask plate of making pixel electrode to carry out composition to the passivation layer under described pixel electrode, etch away part passivation layer, make passivation layer include the figure of respective pixel electrode;
The mask plate that conductive pattern is made in described utilization carries out composition to described conductive layer and forms described conductive pattern and comprise:
Pixel deposition electrode layer on passivation layer;
On described pixel electrode layer, apply photoresist, utilize the mask plate of making pixel electrode to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to pixel electrode region, and photoresist not reserve area, corresponding to the region beyond pixel electrode, carries out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not pixel electrode layer of reserve area of photoresist completely, peel off remaining photoresist, form the figure of pixel electrode.
In such scheme, before making conductive pattern, utilize the mask plate of making conductive pattern to carry out composition to the insulating barrier under conductive pattern, make the insulating barrier under conductive pattern there is the insulating barrier figure corresponding with conductive pattern.Afterwards on insulating barrier during depositing electrically conductive rete, due to the marginal existence slope at insulating barrier figure, the conductive film layer at place, slope is very thin, the process of etching conductive figure is become than being easier to, even if the conductive film layer of below, slope has residual, also will be stopped by the slope of noresidue, play good isolated effect, at the periphery of conductive pattern, form the isolation strip of noresidue, the part of having separated conductive pattern and etching residue, the effect of etching is embodied, reduced the impact of etching residue on the performance of display unit.
The insulating barrier of conductive pattern under pixel electrode, conductive pattern take below as passivation layer is example, array base palte of the present invention and preparation method thereof described in detail:
In the manufacture method of existing array base palte, conventional pixel electrode often adopts tin indium oxide (ITO) material, when utilizing ITO to form pixel electrode, first by Sputter(sputter) film-forming process forms ITO rete on substrate, in this process, the temperature easily causing because of long-term sputter raises and forms ITO crystallization, for thicker ITO rete, this residual more general, because the etching difficulty of crystalline state ITO is greater than the etching difficulty of normality ITO, as shown in Figure 3, after etching forms the figure of pixel electrode, in the neighboring area 6 that retains the region 7 of ITO rete, still can leave over ITO crystal grain, cause having conductive particle between adjacent region 7, will have a strong impact on the overall performance of display unit.
In order to address the above problem, technical scheme of the present invention is before deposition ITO rete, first utilize the mask plate that forms pixel electrode to carry out once more shallow etching to the passivation layer under ITO rete, edge at the pixel electrode that should form forms the gradient, while depositing ITO rete like this on passivation layer, due to the marginal existence slope at passivation layer figure, the ITO rete at place, slope is thin compared with the rete at other smooth places, the process of etching ITO rete is become than being easier to, even if the ITO rete of below, slope has residual, also will be stopped by the slope of noresidue, play good isolated effect, at the periphery of pixel electrode, form the isolation strip of noresidue, the part of having separated pixel electrode and etching residue, the effect of etching is embodied, reduced the impact of etching residue on the performance of display unit.
Particularly, the manufacture method of the array base palte of the present embodiment can comprise the following steps:
Step a a: underlay substrate 4 is provided, and this underlay substrate is transparency carrier particularly, can be glass substrate or quartz base plate;
Step b: form gate electrode and grid line on underlay substrate 4;
Particularly, can adopt the method for sputter or thermal evaporation on underlay substrate 4, to deposit a layer thickness to be
grid metal level, grid metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, grid metal level can be single layer structure or sandwich construction, sandwich construction is such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.On grid metal level, apply one deck photoresist, adopt mask plate to expose to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to the figure region of grid line and gate electrode, photoresist not reserve area corresponding to the region beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; By etching technics, etch away the not grid metallic film of reserve area of photoresist completely, peel off remaining photoresist, form the figure of grid line and gate electrode.
Step c: form gate insulation layer on the underlay substrate through step b;
Particularly, can strengthen chemical gaseous phase depositing process by using plasma, on the underlay substrate through step b, deposit thickness is about
gate insulation layer, wherein, gate insulation layer material can be selected oxide, nitride or nitrogen oxide, gate insulation layer can be individual layer, bilayer or sandwich construction.Particularly, gate insulation layer can be SiNx, SiOx or Si (ON) x.
Steps d: form active layer on gate insulation layer;
Particularly, can on the underlay substrate through step c, adopt magnetron sputtering, thermal evaporation or other film build method deposition a layer thickness to be about
transparent metal oxide semiconductor layer, transparent metal oxide semiconductor layer can be selected amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO2, SnO, CdSnO or other metal oxide semiconductor materials.On transparent metal oxide semiconductor layer, apply photoresist, expose, develop, etching transparent metal oxide semiconductor layer, and stripping photoresist, the figure of the active layer that formation is comprised of transparent metal oxide semiconductor layer.
Step e: forming etching barrier layer through on the underlay substrate of steps d;
Particularly, can, strengthening chemical gaseous phase depositing process deposition-etch barrier layer through using plasma on the substrate of steps d, on etching barrier layer, apply photoresist, expose, develop, etching etching barrier layer, and stripping photoresist, the figure of formation etching barrier layer.Wherein, etching barrier layer can adopt same mask board to explosure, development, etching with active layer.Etching barrier layer material can be selected oxide, nitride or nitrogen oxide, and etching barrier layer can be individual layer, bilayer or sandwich construction.Particularly, etching barrier layer can be SiNx, SiOx or Si (ON) x.
Step f: form source electrode, drain electrode, data wire and data wire on etching barrier layer;
Particularly, can on the underlay substrate through step e, adopt magnetron sputtering, thermal evaporation or other film build method deposition a layer thickness to be about
source leak metal level, it can be Cu that metal level is leaked in source, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals.It can be single layer structure or sandwich construction that metal level is leaked in source, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.In source, leak on metal level and apply one deck photoresist, adopt mask plate to expose to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to the figure region of source electrode, drain electrode, data wire and data wire, photoresist not reserve area corresponding to the region beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; By etching technics, etch away photoresist completely and do not leak metallic film in the source of reserve area, peel off remaining photoresist, form the figure of data wire, source electrode and drain electrode.
Step g: form passivation layer 2 on the underlay substrate through step f;
Particularly, on the underlay substrate through step f, adopt magnetron sputtering, thermal evaporation, PECVD or other film build method deposit thickness to be
passivation material, wherein, passivation material can be selected oxide, nitride or nitrogen oxide, particularly, passivation layer can be SiNx, SiOx or Si (ON) x.Passivation layer can be single layer structure, can be also the double-layer structure that adopts silicon nitride and silica to form.
In passivation material, apply one deck photoresist; Adopt mask plate to expose to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, reserve area is not corresponding to the via hole region of passivation layer for photoresist, and photoresist reserve area is corresponding to the region beyond via hole; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; By etching technics, etch away the not passivation material of reserve area of photoresist completely, peel off remaining photoresist, form the figure of the passivation layer 2 that comprises via hole, wherein the etch period of this etching technics is the first Preset Time.
Step h: utilize the mask plate of making pixel electrode to carry out etching for the second time to passivation layer;
Through on the passivation layer of step g, applying one deck photoresist; Adopt the mask plate of making pixel electrode to expose to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to the figure region of pixel electrode, photoresist not reserve area corresponding to the region beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; By etching technics, etch away the not part passivation material of reserve area of photoresist, peel off remaining photoresist, form the passivation layer figure of respective pixel electrode pattern, wherein the etch period of this etching technics is the second Preset Time, the second Preset Time is less than the first Preset Time, therefore passivation layer can't be carved completely.Passivation layer includes the passivation layer figure of respective pixel electrode, and the passivation layer thickness under pixel electrode is greater than the passivation layer thickness in other regions, and the marginal existence of the passivation layer figure corresponding with pixel electrode has slope.
Step I: form pixel electrode 10 on the underlay substrate 4 through step h.
Particularly, on the underlay substrate 4 through step h, adopt magnetron sputtering, thermal evaporation or other film build method deposit thickness to be
iTO rete, can form structure as shown in Figure 5.On ITO rete, apply one deck photoresist; Adopt pixel electrode mask plate to expose to photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to the figure region of pixel electrode, photoresist not reserve area corresponding to the region beyond above-mentioned figure; Carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged; By etching technics, etch away the not transparency conducting layer of reserve area of photoresist completely, peel off remaining photoresist, form the figure of pixel electrode, pixel electrode is electrically connected by via hole and the drain electrode of passivation layer.
As shown in Figure 5, when deposition ITO layer, the ITO layer segment thickness that forward is faced target is a, and at place, passivation layer slope, lateral face is b to the ITO layer segment thickness of target, and b has significantly and reduces compared with a.After development treatment, photoresist is covered with the region that part above slope needs to retain ITO layer, in etching, form in the process of pixel electrode, use the etching liquid for a thickness ITO layer to carry out etching, different from dry quarter, in etching liquid, etching degree in all directions is consistent, so place, slope etching effect is obviously better than forward in the face of the etching effect of the ITO layer segment of target, the ITO layer at place, slope can be got rid of completely, no longer residual ITO or ITO crystallization, finally as shown in Figure 6, at the periphery of pixel electrode 10, form the isolation strip 8 of noresidue, pixel electrode 8 and etching residue part 9 have been separated, the effect of etching is embodied, reduced the impact of etching residue on the performance of display unit.Certainly pixel electrode is not limited to ITO material, and the manufacture method that the materials such as indium zinc oxide (IZO) also can be applied above-mentioned array base palte forms pixel electrode.
Above-described embodiment be take the manufacture method of etching ITO layer as example explanation array base palte of the present invention, in fact, ITO layer not only, various metal level or the metal oxide layers that are difficult to etching, all can use the method to process: before depositing metal layers or metal oxide layer, utilize the mask plate of making metal level or metal oxide layer to carry out pre-etching to the insulating barrier under metal level or metal oxide layer, insulating barrier is had and metal layer image or the corresponding figure of metal oxide layer pattern, marginal existence slope at the metal layer image that should form or metal oxide layer pattern, while making subsequent deposition metal level or metal oxide layer, can form thinner metal level or metal oxide layer at place, slope, final etching forms after metal layer image or metal oxide layer pattern, isolation strip in metal layer image or metal oxide layer pattern periphery formation noresidue, separate metal layer image or metal oxide layer pattern and etching residue part, reduced the impact of etching residue on the performance of display unit.
The embodiment of the present invention also provides more than one to state the array base palte of manufacture method, insulating barrier under at least one conductive pattern of described array base palte includes the insulating barrier figure corresponding with described conductive pattern, the justified margin of described conductive pattern and described insulating barrier figure.
Further, the thickness of insulating layer under described conductive pattern is greater than the thickness of insulating layer of other location.
Further, the marginal existence of the insulating barrier figure corresponding with described conductive pattern has slope.Described conductive pattern can be source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
Array base palte of the present invention, the insulating barrier under conductive pattern has the insulating barrier figure corresponding with conductive pattern.When on the insulating barrier of this kind of array base palte, depositing electrically conductive rete is made conductive pattern like this, due to the marginal existence slope at insulating barrier figure, the conductive film layer at place, slope is very thin, the process of etching conductive figure is become than being easier to, even if the conductive film layer of below, slope has residual, also will be stopped by the slope of noresidue, play good isolated effect, at the periphery of conductive pattern, form the isolation strip of noresidue, the part of having separated conductive pattern and etching residue, the effect of etching is embodied, reduced the impact of etching residue on the performance of display unit.
Further, described array base palte includes the insulating barrier being positioned under source electrode, drain electrode and data wire, described insulating barrier can be etching barrier layer layer, resilient coating or passivation layer, when the insulating barrier under described conductive pattern is etching barrier layer, etching barrier layer under source electrode, drain electrode and the data wire of described array base palte has the etching barrier layer figure corresponding with described source electrode, drain electrode, data wire and data wire, the justified margin of source electrode, drain electrode, data wire and etching barrier layer.
Further, described array base palte includes the insulating barrier being positioned under gate electrode and grid line, described conductive pattern can be the figure of gate electrode and grid line, insulating barrier under described conductive pattern can be the resilient coating under gate electrode and grid line, the gate electrode of described array base palte and the resilient coating under grid line have the resilient coating figure corresponding with described gate electrode and grid line, the justified margin of gate electrode and grid line and resilient coating figure.
Further, described array base palte includes the insulating barrier being positioned under pixel electrode, described conductive pattern can be the figure of pixel electrode, insulating barrier under described conductive pattern can be the passivation layer under pixel electrode, passivation layer under the pixel electrode of described array base palte has the passivation layer figure corresponding with described pixel electrode, the justified margin of pixel electrode and passivation layer.
The embodiment of the present invention also provides a kind of display unit, comprises array base palte as above.Wherein, the same above-described embodiment of the structure of array base palte and operation principle, does not repeat them here.In addition, the structure of other parts of display unit can, with reference to prior art, be not described in detail this herein.This display unit can be: liquid crystal panel, Electronic Paper, OLED(Organic Light Emitting Diode, Organic Light Emitting Diode) panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any Presentation Function.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a manufacture method for array base palte, is characterized in that, comprising:
Before making conductive pattern, utilize the mask plate of making conductive pattern to carry out composition to the insulating barrier under described conductive pattern;
Depositing conducting layer, the mask plate of utilization making conductive pattern carries out composition to described conductive layer and forms described conductive pattern.
2. the manufacture method of array base palte according to claim 1, is characterized in that, the mask plate of described utilization making conductive pattern carries out composition to the insulating barrier under described conductive pattern and comprises:
Form the first figure of insulating barrier;
On the substrate of the first figure that is formed with described insulating barrier, apply photoresist, utilize the mask plate of making conductive pattern to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to described conductive pattern region, photoresist not reserve area corresponding to the region beyond described conductive pattern, carry out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not partial insulative layer of reserve area of photoresist, peel off remaining photoresist, form the second graph corresponding with described conductive pattern of described insulating barrier, the edge of described second graph has slope.
3. the manufacture method of array base palte according to claim 2, is characterized in that, the thickness of insulating layer under described conductive pattern is greater than the thickness of insulating layer of other location.
4. according to the manufacture method of the array base palte described in any one in claim 1-3, it is characterized in that, the mask plate that conductive pattern is made in described utilization carries out composition to described conductive layer and forms described conductive pattern and comprise:
Depositing conducting layer on described insulating barrier;
On described conductive layer, apply photoresist, utilize the mask plate of making conductive pattern to expose to described photoresist, make photoresist form photoresist not reserve area and photoresist reserve area, wherein, photoresist reserve area is corresponding to described conductive pattern region, and photoresist not reserve area, corresponding to the region beyond described conductive pattern, carries out development treatment, the photoresist not photoresist of reserve area is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
By etching technics, etch away the not conductive layer of reserve area of photoresist completely, peel off remaining photoresist, form described conductive pattern.
5. the manufacture method of array base palte according to claim 4, is characterized in that, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
6. an array base palte made from method described in any one in claim 1-5, it is characterized in that, insulating barrier under at least one conductive pattern includes the insulating barrier figure corresponding with described conductive pattern, the justified margin of described conductive pattern and described insulating barrier figure.
7. array base palte according to claim 6, is characterized in that, the thickness of insulating layer under described conductive pattern is greater than the thickness of insulating layer of other location.
8. array base palte according to claim 6, is characterized in that, the marginal existence of the insulating barrier figure corresponding with described conductive pattern has slope.
9. array base palte according to claim 6, is characterized in that, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
10. a display unit, is characterized in that, comprises the array base palte as described in any one in claim 6-9.
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| CN201310713498.1A CN103700670B (en) | 2013-12-20 | 2013-12-20 | Array base palte and preparation method thereof, display device |
| PCT/CN2014/078923 WO2015090008A1 (en) | 2013-12-20 | 2014-05-30 | Array substrate and manufacturing method therefor, and display device |
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| CN201310713498.1A CN103700670B (en) | 2013-12-20 | 2013-12-20 | Array base palte and preparation method thereof, display device |
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Cited By (4)
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| WO2015090008A1 (en) * | 2013-12-20 | 2015-06-25 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN106086797A (en) * | 2016-07-12 | 2016-11-09 | 京东方科技集团股份有限公司 | Indium tin oxide films and preparation method thereof, containing its array base palte, display device |
| WO2018218987A1 (en) * | 2017-06-02 | 2018-12-06 | Boe Technology Group Co., Ltd. | Display substrate, display apparatus, and method of fabricating display substrate |
| CN114924437A (en) * | 2022-05-20 | 2022-08-19 | 北京京东方技术开发有限公司 | Array substrate, preparation method thereof and display device |
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| CN114141936B (en) * | 2020-09-03 | 2024-08-20 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
| CN113053766B (en) * | 2021-03-08 | 2024-08-02 | 京东方科技集团股份有限公司 | Photoresist residue detection method, panel, manufacturing method and display device |
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| CN100456089C (en) * | 2006-03-09 | 2009-01-28 | 北京京东方光电科技有限公司 | Pixel structure of LCD array substrate and method for making same |
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| CN202948924U (en) * | 2012-09-13 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN103700670B (en) * | 2013-12-20 | 2016-08-17 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
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| US20060145232A1 (en) * | 2004-12-30 | 2006-07-06 | Kim Hyung S | Method for manufacturing semiconductor device including MIM capacitor |
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| WO2015090008A1 (en) | 2015-06-25 |
| CN103700670B (en) | 2016-08-17 |
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