CN103700670B - Array base palte and preparation method thereof, display device - Google Patents
Array base palte and preparation method thereof, display device Download PDFInfo
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- CN103700670B CN103700670B CN201310713498.1A CN201310713498A CN103700670B CN 103700670 B CN103700670 B CN 103700670B CN 201310713498 A CN201310713498 A CN 201310713498A CN 103700670 B CN103700670 B CN 103700670B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
Abstract
The invention provides a kind of array base palte and preparation method thereof, display device, belong to Display Technique field.The manufacture method of this array base palte includes: before making conductive pattern, utilizes the mask plate making conductive pattern to be patterned the insulating barrier under described conductive pattern；Deposition conductive layer, utilizes the mask plate making conductive pattern to be patterned forming described conductive pattern to described conductive layer.Pass through technical scheme, it is possible to ensure the periphery noresidue of conductive pattern after etching, reduce the etching residue impact on the performance of display device.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and preparation method thereof, display device.
Background technology
At LCD(Liquid Crystal Display, liquid crystal display) array base palte and OLED(Organic Light-
Emitting Diode, Organic Light Emitting Diode) array base palte manufacturing process in, conductive pattern etching is uneven will be poised for battle
The display performance of row substrate impacts, and such as array base palte is frequently used tin indium oxide (ITO) and makes pixel electrode, but
When depositing ITO, easily form ITO crystallization because sputtering the temperature rising caused for a long time, increase with the thickness of ito thin film, this
Plant phenomenon further obvious, owing to the etching of crystalline state ITO is relatively difficult, therefore etch ito thin film formation pixel electrode subsequently
During figure, it is susceptible to ITO residual.
Be illustrated in figure 1 array base-plate structure more typically, on underlay substrate 4 make include gate electrode, gate insulation layer,
Active layer, source-drain electrode layer etc. are passivated layer 2 and the making of ITO layer 1 after interior array base palte each film layer 3.ITO passes through
After patterning processes, preferable situation is as in figure 2 it is shown, be also adjacent ITO pattern district at the region 7(of adjacent reservation ito thin film
Territory) between the ito film layer in region 5 removing ito thin film should be completely removed, expose following passivation layer.But, carving
The when that erosion ITO layer forming pixel electrode figure, owing to the etching ratio of crystalline state ITO is more difficult, as it is shown on figure 3, etching often occurs
Incomplete situation, will retain ito thin film and form electrode, expose following passivation in region 5 by removing ito thin film in region 7
Layer, but owing to the etching difficulty of crystalline state ITO is more than the etching difficulty of normality ITO, in the neighboring area 6 in region 7, still can lose
Leave ITO crystal grain.If the ITO crystal grain that the neighboring area 6 in region 7 is left over too much can make electricity between the pixel electrode of neighbor
Connect, have a strong impact on the electric property of array base palte, add the uncontrollability of array base palte overall performance, will eventually affect
The display effect of display device.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte and preparation method thereof, display device, it is possible to protect
Demonstrate,prove the periphery noresidue of conductive pattern after etching, reduce the etching residue impact on the performance of display device.
For solving above-mentioned technical problem, embodiments of the invention provide technical scheme as follows:
On the one hand, it is provided that the manufacture method of a kind of array base palte, including:
Before making conductive pattern, utilize the mask plate making conductive pattern to the insulating barrier under described conductive pattern
It is patterned；
Deposition conductive layer, utilizes the mask plate making conductive pattern to be patterned forming described conductive pattern to described conductive layer
Shape.
Further, the described mask plate utilizing making conductive pattern carries out structure to the insulating barrier under described conductive pattern
Figure includes:
Form the first figure of insulating barrier；
The substrate of the first figure being formed with described insulating barrier coats photoresist, utilizes the mask making conductive pattern
Described photoresist is exposed by plate, makes photoresist form photoresist and does not retains region and photoresist reservation region, wherein, photoetching
Glue retains region and corresponds to described conductive pattern region, and photoresist does not retains region corresponding to beyond described conductive pattern
Region, carries out development treatment, and photoresist does not retains the photoresist in region and is completely removed, and the photoresist that photoresist retains region is thick
Degree keeps constant；
Etch away photoresist by etching technics and do not retain the partial insulative layer in region, peel off remaining photoresist, formed
The second graph corresponding with described conductive pattern of described insulating barrier, the edge of described second graph there are slope.
Further, the thickness of insulating layer under described conductive pattern is more than the thickness of insulating layer at other regions.
Further, described conductive layer is patterned forming described conduction by the described mask plate utilizing making conductive pattern
Figure includes:
Described insulating barrier deposits conductive layer；
Described conductive layer coats photoresist, utilizes the mask plate making conductive pattern that described photoresist is exposed
Light, makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region corresponding to described
Conductive pattern region, photoresist does not retains region and corresponds to the region beyond described conductive pattern, carries out development treatment, light
Photoresist does not retains the photoresist in region and is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；
Etched away photoresist by etching technics completely and do not retain the conductive layer in region, peel off remaining photoresist, formed
Described conductive pattern.
Further, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
The embodiment of the present invention additionally provides a kind of array base palte utilizing method described above to make, at least one conductive pattern it
Under insulating barrier include the layer pattern corresponding with described conductive pattern, described conductive pattern and described layer pattern
Justified margin.
Further, the thickness of insulating layer under described conductive pattern is more than the thickness of insulating layer at other regions
Further, the marginal existence of corresponding with described conductive pattern layer pattern has slope.
Further, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
The embodiment of the present invention additionally provides a kind of display device, including array base palte as above.
Embodiments of the invention have the advantages that
In such scheme, making before conductive pattern, utilize the mask plate making conductive pattern to conductive pattern under
Insulating barrier be patterned so that the insulating barrier under conductive pattern has the layer pattern corresponding with conductive pattern.Afterwards
On the insulating layer during deposition conductive film layer, due to the marginal existence slope at layer pattern, the conductive film layer at slope is the thinnest,
The process making etching conductive figure becomes easier to, even if the conductive film layer below slope has residual, and also will be by noresidue
Slope stopped, play good isolation effect, conductive pattern periphery formed noresidue isolation strip, separated conduction
The part of figure and etching residue so that the effect of etching is embodied, reduces etching residue to the performance of display device
Impact.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of existing array base palte；
Fig. 2 is schematic top plan view during ITO etching noresidue；
Fig. 3 is ITO schematic top plan view when being etched with residual；
Fig. 4 is the schematic flow sheet of the manufacture method of embodiment of the present invention array base palte；
Fig. 5 is the schematic cross-section after embodiment of the present invention array base palte deposition transparency conducting layer；
Fig. 6 is the schematic top plan view of embodiment of the present invention ITO marginal portion.
Reference
1 transparency conducting layer 2 passivation layer
3 including gate electrode, gate insulation layer, active layer, source-drain electrode layer etc. including each film layer
4 underlay substrates 5 remove the region of ito thin film
The neighboring area 7 in 6 regions 7 retains the region of ito thin film
8 isolation strip 9 etching residue part 10 pixel electrodes
Detailed description of the invention
For making embodiments of the invention solve the technical problem that, technical scheme and advantage clearer, below in conjunction with
Drawings and the specific embodiments are described in detail.
Embodiments of the invention can be to the performance of display device for the etching residue of conductive pattern periphery in prior art
The problem impacted, it is provided that a kind of array base palte and preparation method thereof, display device, it is possible to ensure conductive pattern after etching
Periphery noresidue, reduce the etching residue impact on the performance of display device.
Embodiments providing the manufacture method of a kind of array base palte, as shown in Figure 4, the present embodiment includes:
Step 101: making before conductive pattern, utilize the mask plate making conductive pattern to described conductive pattern under
Insulating barrier be patterned；
Step 102: deposition conductive layer, utilizes the mask plate making conductive pattern to be patterned described conductive layer forming institute
State conductive pattern.
The manufacture method of the array base palte of the present invention, before making conductive pattern, utilizes the mask making conductive pattern
Insulating barrier under conductive pattern is patterned by plate so that the insulating barrier under conductive pattern has corresponding with conductive pattern
Layer pattern.The most on the insulating layer during deposition conductive film layer, due to the marginal existence slope at layer pattern, at slope
Conductive film layer the thinnest so that the process of etching conductive figure becomes easier to, even if the conductive film layer below slope has residual
Stay, also will be stopped by the slope of noresidue, play good isolation effect, conductive pattern periphery formed noresidue every
From band, separate the part of conductive pattern and etching residue so that the effect of etching is embodied, reduce etching residue to aobvious
The impact of the performance of showing device.
Further, the described mask plate utilizing making conductive pattern carries out structure to the insulating barrier under described conductive pattern
Figure includes:
Form the first figure of insulating barrier；
The substrate of the first figure being formed with described insulating barrier coats photoresist, utilizes the mask making conductive pattern
Described photoresist is exposed by plate, makes photoresist form photoresist and does not retains region and photoresist reservation region, wherein, photoetching
Glue retains region and corresponds to described conductive pattern region, and photoresist does not retains region corresponding to beyond described conductive pattern
Region, carries out development treatment, and photoresist does not retains the photoresist in region and is completely removed, and the photoresist that photoresist retains region is thick
Degree keeps constant；
Etch away photoresist by etching technics and do not retain the partial insulative layer in region, peel off remaining photoresist, formed
The second graph corresponding with described conductive pattern of described insulating barrier, the edge of described second graph there are slope.
Further, the thickness of insulating layer under described conductive pattern is more than the thickness of insulating layer at other regions.
Further, described conductive layer is patterned forming described conduction by the described mask plate utilizing making conductive pattern
Figure includes:
Described insulating barrier deposits conductive layer；
Described conductive layer coats photoresist, utilizes the mask plate making conductive pattern that described photoresist is exposed
Light, makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region corresponding to described
Conductive pattern region, photoresist does not retains region and corresponds to the region beyond described conductive pattern, carries out development treatment, light
Photoresist does not retains the photoresist in region and is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；
Etched away photoresist by etching technics completely and do not retain the conductive layer in region, peel off remaining photoresist, formed
Described conductive pattern.
Further, described conductive pattern is source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
Specifically, described conductive pattern can be source electrode, drain electrode, data wire, and described array base palte includes and is positioned at
Insulating barrier under source electrode, drain electrode and data wire, described insulating barrier can be etching barrier layer, described at making conductive pattern
Before shape, the mask plate making conductive pattern is utilized to be patterned including to the insulating barrier under described conductive pattern:
Before making the figure of source electrode, drain electrode and data wire, utilize and make source electrode, drain electrode and data wire
Etching barrier layer under described source electrode, drain electrode and data wire is patterned by mask plate, etch away sections etch stopper
Layer so that etching barrier layer includes corresponding source electrode, drain electrode and the figure of data wire；
The described mask plate utilizing making conductive pattern is patterned forming described conductive pattern and includes described conductive layer:
Sedimentary origin electrode, drain electrode, data wire metal layer on etching barrier layer；
On described source electrode, drain electrode, data wire metal layer coat photoresist, utilize make source electrode, drain electrode and
Described photoresist is exposed by the mask plate of data wire, makes photoresist form photoresist and does not retains region and photoresist reserved area
Territory, wherein, photoresist retains region and corresponds to source electrode, drain electrode and data wire region, and photoresist does not retains region pair
Should region beyond source electrode, drain electrode data wire, carry out development treatment, photoresist does not retains the photoresist in region by completely
Removing, photoresist retains the photoresist thickness in region and keeps constant；
Etched away photoresist by etching technics completely and do not retain the source electrode in region, drain electrode, data wire metal layer, stripping
From remaining photoresist, form source electrode, drain electrode and the figure of data wire.
Further, described array base palte includes the insulating barrier being positioned under gate electrode and grid line, described conductive pattern
Can be the figure of gate electrode and grid line, the insulating barrier under described conductive pattern can be the buffering under gate electrode and grid line
Layer, described before making conductive pattern, utilize the mask plate making conductive pattern to the insulating barrier under described conductive pattern
It is patterned including:
Before making the figure of gate electrode and grid line, utilize the mask plate making gate electrode and grid line to described gate electrode
It is patterned with the cushion under grid line, etch away sections cushion so that cushion includes corresponding gate electrode and grid line
Figure；
The described mask plate utilizing making conductive pattern is patterned forming described conductive pattern and includes described conductive layer:
Deposition grid metal level on the buffer layer；
Described grid metal level coats photoresist, utilizes the mask plate making gate electrode and grid line that described photoresist is entered
Row exposure, makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region and corresponds to
Gate electrode and grid line region, photoresist does not retains region and corresponds to the region beyond gate electrode and grid line, carries out at development
Reason, photoresist does not retains the photoresist in region and is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；
Etched away photoresist by etching technics completely and do not retain the grid metal level in region, peel off remaining photoresist, shape
Become gate electrode and the figure of grid line.
Further, described array base palte includes the passivation layer being positioned under pixel electrode, and described conductive pattern is permissible
For the figure of pixel electrode, the insulating barrier under described conductive pattern can be the passivation layer under pixel electrode, described in system
Before making conductive pattern, utilize the mask plate making conductive pattern that the insulating barrier under described conductive pattern is patterned bag
Include:
Make pixel electrode figure before, utilize make pixel electrode mask plate to described pixel electrode under
Passivation layer is patterned, etch away sections passivation layer so that passivation layer includes the figure of respective pixel electrode；
The described mask plate utilizing making conductive pattern is patterned forming described conductive pattern and includes described conductive layer:
Pixel deposition electrode layer over the passivation layer；
Described pixel electrode layer coats photoresist, utilizes the mask plate making pixel electrode that described photoresist is carried out
Exposure, makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region corresponding to picture
Element electrode region, photoresist does not retains region and corresponds to the region beyond pixel electrode, carries out development treatment, and photoresist is not
The photoresist retaining region is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；
Etched away photoresist by etching technics completely and do not retain the pixel electrode layer in region, peel off remaining photoresist,
Form the figure of pixel electrode.
In such scheme, making before conductive pattern, utilize the mask plate making conductive pattern to conductive pattern under
Insulating barrier be patterned so that the insulating barrier under conductive pattern has the layer pattern corresponding with conductive pattern.Afterwards
On the insulating layer during deposition conductive film layer, due to the marginal existence slope at layer pattern, the conductive film layer at slope is the thinnest,
The process making etching conductive figure becomes easier to, even if the conductive film layer below slope has residual, and also will be by noresidue
Slope stopped, play good isolation effect, conductive pattern periphery formed noresidue isolation strip, separated conduction
The part of figure and etching residue so that the effect of etching is embodied, reduces etching residue to the performance of display device
Impact.
As a example by with conductive pattern, insulating barrier as pixel electrode, under conductive pattern is as passivation layer below, to the present invention's
Array base palte and preparation method thereof describes in detail:
In the manufacture method of existing array base palte, conventional pixel electrode is frequently with tin indium oxide (ITO) material, in profit
When forming pixel electrode with ITO, first passing through Sputter(sputtering) film-forming process forms ito film layer, in this mistake on substrate
Cheng Zhong, easily forms ITO crystallization because sputtering the temperature rising caused for a long time, and for thicker ito film layer, this residual is more
Generally, owing to the etching difficulty of crystalline state ITO is more than the etching difficulty of normality ITO, as it is shown on figure 3, form pixel electrode in etching
Figure after, in the neighboring area 6 in region 7 retaining ito film layer, still can leave over ITO crystal grain, cause adjacent region
Conductive particle is there is, it will have a strong impact on the overall performance of display device between 7.
In order to solve the problems referred to above, technical scheme is before deposition of ITO films, first with forming pixel electricity
The mask plate of pole carries out the most shallower etching to the passivation layer under ito film layer, in the edge of the pixel electrode that should be formed
Form the gradient, the most over the passivation layer during deposition of ITO films, due to the marginal existence slope at passivation layer figure, at slope
Ito film layer is thin compared with the film layer of other flat places so that the process of etching ito film layer becomes easier to, even if below slope
Ito film layer has residual, also will be stopped by the slope of noresidue, plays good isolation effect, in the periphery shape of pixel electrode
Become the isolation strip of noresidue, separate the part of pixel electrode and etching residue so that the effect of etching is embodied, and reduces
The etching residue impact on the performance of display device.
Specifically, the manufacture method of the array base palte of the present embodiment may comprise steps of:
Step a: provide a underlay substrate 4, this underlay substrate is transparency carrier, specifically, can be glass substrate or stone
English substrate；
Step b: form gate electrode and grid line on underlay substrate 4；
Specifically, sputtering or the method for thermal evaporation can be used to deposit a layer thickness on underlay substrate 4 to beGrid metal level, grid metal level can be Cu, the metal such as Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W with
And the alloy of these metals, grid metal level can be single layer structure or multiple structure, multiple structure such as Cu Mo, Ti Cu
Ti, Mo Al Mo etc..Grid metal level coats a layer photoetching glue, uses mask plate that photoresist is exposed, make photoresist
Forming photoresist not retain region and photoresist and retain region, wherein, photoresist retains region corresponding to grid line and gate electrode
Figure region, photoresist does not retains region corresponding to the region beyond above-mentioned figure；Carrying out development treatment, photoresist is not protected
The photoresist staying region is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；Complete by etching technics
Etch away photoresist and do not retain the grid metallic film in region, peel off remaining photoresist, form grid line and the figure of gate electrode.
Step c: forming gate insulation layer on the underlay substrate of step b；
Specifically, chemical gaseous phase depositing process can be strengthened with using plasma, heavy on the underlay substrate of step b
Long-pending thickness is aboutGate insulation layer, wherein, gate insulator layer material can select oxide, nitride or nitrogen
Oxide, gate insulation layer can be monolayer, bilayer or multiple structure.Specifically, gate insulation layer can be SiNx, SiOx or Si
(ON)x。
Step d: be formed with active layer on gate insulation layer；
Specifically, can sink using magnetron sputtering, thermal evaporation or other film build method on the underlay substrate of step c
Long-pending a layer thickness is aboutTransparent metal oxide semiconductor layer, transparent metal oxide semiconductor layer can select
With amorphous IGZO, HIZO, IZO, InZnO, ZnO, TiO2, SnO, CdSnO or other metal oxide semiconductor materials.Transparent
Coat photoresist on metal oxide semiconductor layer, be exposed, develop, etch transparent metal oxide semiconductor layer, and shell
From photoresist, form the figure of the active layer being made up of transparent metal oxide semiconductor layer.
Step e: forming etching barrier layer on the underlay substrate of step d；
Specifically, chemical vapor deposition can be strengthened at using plasma on the substrate of step d to carve
Erosion barrier layer, coats photoresist on etching barrier layer, is exposed, develops, and etches etching barrier layer, and stripping photoresist,
Form the figure of etching barrier layer.Wherein, the mask plate as etching barrier layer can use with active layer is exposed, shows
Shadow, etching.Etching barrier layer materials can select oxide, nitride or nitrogen oxides, etching barrier layer can be monolayer,
Bilayer or multiple structure.Specifically, etching barrier layer can be SiNx, SiOx or Si (ON) x.
Step f: form source electrode, drain electrode, data wire and data wire on etching barrier layer；
Specifically, can sink using magnetron sputtering, thermal evaporation or other film build method on the underlay substrate of step e
Long-pending a layer thickness is aboutSource and drain metal level, source and drain metal level can be Cu, Al, Ag, Mo, Cr, Nd, Ni,
The metals such as Mn, Ti, Ta, W and the alloy of these metals.Source and drain metal level can be single layer structure or multiple structure, multilamellar
Structure such as Cu Mo, Ti Cu Ti, Mo Al Mo etc..Source and drain metal level coats a layer photoetching glue, uses mask plate to light
Photoresist is exposed, and makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region
Corresponding to the figure region of source electrode, drain electrode, data wire and data wire, photoresist does not retains region corresponding to above-mentioned figure
Region beyond shape；Carrying out development treatment, photoresist does not retains the photoresist in region and is completely removed, and photoresist retains region
Photoresist thickness keeps constant；Etched away photoresist by etching technics completely and do not retain the source and drain metallic film in region, peel off
Remaining photoresist, forms data wire, source electrode and the figure of drain electrode.
Step g: forming passivation layer 2 on the underlay substrate of step f；
Specifically, on the underlay substrate of step f, magnetron sputtering, thermal evaporation, PECVD or other film build method are being used
Deposit thickness isPassivation material, wherein, passivation material can select oxide, nitride or nitrogen oxygen
Compound, specifically, passivation layer can be SiNx, SiOx or Si (ON) x.Passivation layer can be single layer structure, it is also possible to be to use
The double-layer structure that silicon nitride and silicon oxide are constituted.
Passivation material applies a layer photoetching glue；Use mask plate that photoresist is exposed, make photoresist be formed
Photoresist does not retains region and photoresist retains region, and wherein, photoresist does not retains the via place corresponding to passivation layer, the region
Region, photoresist retains region corresponding to the region beyond via；Carrying out development treatment, photoresist does not retains the photoresist in region
Being completely removed, photoresist retains the photoresist thickness in region and keeps constant；Photoresist is etched away completely not by etching technics
Retain the passivation material in region, peel off remaining photoresist, form the figure of the passivation layer 2 including via, wherein this quarter
The etch period of etching technique is the first Preset Time.
Step h: utilize the mask plate making pixel electrode that passivation layer carries out second time and etch；
A layer photoetching glue is being applied on the passivation layer of step g；Use the mask plate making pixel electrode to photoresist
Being exposed, make photoresist form photoresist and do not retain region and photoresist reservation region, wherein, it is corresponding that photoresist retains region
In the figure region of pixel electrode, photoresist does not retains region corresponding to the region beyond above-mentioned figure；Carry out at development
Reason, photoresist does not retains the photoresist in region and is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；Pass through
Etching technics etches away photoresist and does not retains the partial deactivation layer material in region, peels off remaining photoresist, forms respective pixel
The passivation layer figure of electrode pattern, wherein the etch period of this etching technics is the second Preset Time, and the second Preset Time is little
In the first Preset Time, therefore passivation layer can't be carved completely.Passivation layer includes the passivation layer figure of respective pixel electrode
Shape, the passivation layer thickness under pixel electrode is more than the passivation layer thickness in other regions, the passivation layer figure corresponding with pixel electrode
Marginal existence have slope.
Step i: forming pixel electrode 10 on the underlay substrate 4 of step h.
Specifically, on the underlay substrate 4 of step h, magnetron sputtering, thermal evaporation or other film build method deposition are being used
Thickness isIto film layer, structure as shown in Figure 5 can be formed.Ito film layer applies a layer photoetching glue；
Use pixel electrode mask plate that photoresist is exposed, make photoresist form photoresist and do not retain region and photoresist reserved area
Territory, wherein, photoresist retains the figure region corresponding to pixel electrode, the region, and photoresist does not retains region corresponding to above-mentioned
Region beyond figure；Carrying out development treatment, photoresist does not retains the photoresist in region and is completely removed, and photoresist retains region
Photoresist thickness keep constant；Etched away photoresist by etching technics completely and do not retain the transparency conducting layer in region, peel off
Remaining photoresist, forms the figure of pixel electrode, and pixel electrode is electrically connected with drain electrode by the via of passivation layer.
As it is shown in figure 5, when depositing ITO layer, forward is a in the face of the ITO layer segment thickness of target, on passivation layer slope
Place, lateral face is that b, b relatively a has significantly reduction to the ITO layer segment thickness of target.After development treatment, photoresist is covered with
Slope part above i.e. needs to retain the region of ITO layer, during etching forms pixel electrode, uses for a thickness
The etching liquid of ITO layer performs etching, different from dry etching, and in etching liquid, the etching degree in all directions is consistent, so
At slope, etching effect is substantially better than forward in the face of the etching effect of the ITO layer part of target, it is possible to by complete for the ITO layer at slope
Entirely get rid of, no longer residual ITO or ITO crystallization, the most as shown in Figure 6, pixel electrode 10 periphery formed noresidue every
From band 8, pixel electrode 8 and etching residue part 9 are separated so that the effect of etching is embodied, and reduces etching residue pair
The impact of the performance of display device.The materials such as pixel electrode is not limited to ITO material certainly, indium zinc oxide (IZO) can also be applied
The manufacture method of above-mentioned array base palte forms pixel electrode.
Above-described embodiment illustrates the manufacture method of array base palte of the present invention as a example by etching ITO layer, it practice, not only ITO
Layer, the various metal levels being difficult to etch or metal oxide layer, the method all can be used to process: at deposition metal level or gold
Belong to before oxide skin(coating), utilize the mask plate making metal level or metal oxide layer to metal level or metal oxide layer under
Insulating barrier carry out pre-etching, make insulating barrier have and metal layer image or the corresponding figure of metal-oxide layer pattern, should
The metal layer image formed or the marginal existence slope of metal-oxide layer pattern so that subsequent deposition metal level or burning
During nitride layer, it is possible to form relatively thin metal level or metal oxide layer at slope, final etching forms metal layer image or gold
After belonging to oxide skin(coating) figure, form the isolation strip of noresidue, separately gold in metal layer image or metal-oxide layer pattern periphery
Belong to layer pattern or metal-oxide layer pattern and etching residue part, reduce the etching residue shadow to the performance of display device
Ring.
The embodiment of the present invention additionally provides more than one array base paltes stating manufacture method, at least the one of described array base palte
Insulating barrier under conductive pattern includes the layer pattern corresponding with described conductive pattern, described conductive pattern with described absolutely
The justified margin of edge layer figure.
Further, the thickness of insulating layer under described conductive pattern is more than the thickness of insulating layer at other regions.
Further, the marginal existence of corresponding with described conductive pattern layer pattern has slope.Described conductive pattern
Can be source electrode, drain electrode, data wire, gate electrode, grid line or pixel electrode.
The array base palte of the present invention, the insulating barrier under conductive pattern has the layer pattern corresponding with conductive pattern.
When so depositing conductive film layer making conductive pattern on the insulating barrier of this kind of array base palte, due to the edge at layer pattern
There is slope, the conductive film layer at slope is the thinnest so that the process of etching conductive figure becomes easier to, even if below slope
Conductive film layer have residual, also will be stopped by the slope of noresidue, play good isolation effect, at the periphery of conductive pattern
Form the isolation strip of noresidue, separated the part of conductive pattern and etching residue so that the effect of etching is embodied, reduce
The etching residue impact on the performance of display device.
Further, described array base palte includes the insulating barrier being positioned under source electrode, drain electrode and data wire, described
Insulating barrier can be etching barrier layer layer, cushion or passivation layer, and the insulating barrier under described conductive pattern is etch stopper
During layer, the etching barrier layer under the source electrode of described array base palte, drain electrode and data wire has and described source electrode, electric leakage
The edge of pole, the etch stopper layer pattern that data wire is corresponding with data wire, source electrode, drain electrode, data wire and etching barrier layer
Alignment.
Further, described array base palte includes the insulating barrier being positioned under gate electrode and grid line, described conductive pattern
Can be the figure of gate electrode and grid line, the insulating barrier under described conductive pattern can be the buffering under gate electrode and grid line
Layer, the gate electrode of described array base palte has the cushion figure corresponding with described gate electrode and grid line with the cushion under grid line
Shape, gate electrode and grid line and the justified margin of cushion figure.
Further, described array base palte includes the insulating barrier being positioned under pixel electrode, and described conductive pattern is permissible
For the figure of pixel electrode, the insulating barrier under described conductive pattern can be the passivation layer under pixel electrode, described array
Passivation layer under the pixel electrode of substrate has the passivation layer figure corresponding with described pixel electrode, pixel electrode and passivation layer
Justified margin.
The embodiment of the present invention additionally provides a kind of display device, including array base palte as above.Wherein, array base palte
Structure and the same above-described embodiment of operation principle, do not repeat them here.It addition, the structure of other parts of display device can be joined
Examine prior art, this is not described in detail herein.This display device can be: liquid crystal panel, Electronic Paper, OLED(Organic
Light Emitting Diode, Organic Light Emitting Diode) panel, LCD TV, liquid crystal display, DPF, mobile phone, flat
Plate computer etc. has product or the parts of any display function.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, it is also possible to make some improvements and modifications, these improvements and modifications are also
Should be regarded as protection scope of the present invention.
Claims (10)
1. the manufacture method of an array base palte, it is characterised in that including:
Before making conductive pattern, utilize the mask plate making conductive pattern that the insulating barrier under described conductive pattern is carried out
Composition；
Deposition conductive layer, utilizes the mask plate making conductive pattern to be patterned forming described conductive pattern to described conductive layer.
The manufacture method of array base palte the most according to claim 1, it is characterised in that described utilization makes conductive pattern
Insulating barrier under described conductive pattern is patterned including by mask plate:
Form the first figure of insulating barrier；
The substrate of the first figure being formed with described insulating barrier coats photoresist, utilizes the mask plate pair making conductive pattern
Described photoresist is exposed, and makes photoresist form photoresist and does not retains region and photoresist reservation region, and wherein, photoresist is protected
Staying region to correspond to described conductive pattern region, photoresist does not retains region corresponding to the district beyond described conductive pattern
Territory, carries out development treatment, and photoresist does not retains the photoresist in region and is completely removed, and photoresist retains the photoresist thickness in region
Keep constant；
Etch away photoresist by etching technics and do not retain the partial insulative layer in region, peel off remaining photoresist, formed described
The second graph corresponding with described conductive pattern of insulating barrier, the edge of described second graph there are slope.
The manufacture method of array base palte the most according to claim 2, it is characterised in that the insulating barrier under described conductive pattern
Thickness is more than the thickness of insulating layer at other regions.
4. according to the manufacture method of the array base palte according to any one of claim 1-3, it is characterised in that described utilization makes
The mask plate of conductive pattern is patterned forming described conductive pattern and includes described conductive layer:
Described insulating barrier deposits conductive layer；
Described conductive layer coats photoresist, utilizes the mask plate making conductive pattern that described photoresist is exposed, make
Photoresist forms photoresist and does not retains region and photoresist reservation region, and wherein, photoresist retains region corresponding to described conduction
Figure region, photoresist does not retains region and corresponds to the region beyond described conductive pattern, carries out development treatment, photoresist
The photoresist not retaining region is completely removed, and photoresist retains the photoresist thickness in region and keeps constant；
Etched away photoresist by etching technics completely and do not retain the conductive layer in region, peel off remaining photoresist, formed described
Conductive pattern.
The manufacture method of array base palte the most according to claim 4, it is characterised in that described conductive pattern be source electrode,
Drain electrode, data wire, gate electrode, grid line or pixel electrode.
6. the array base palte made with method according to any one of claim 1-5, it is characterised in that at least one conductive pattern
Insulating barrier under shape includes the layer pattern corresponding with described conductive pattern, described conductive pattern and described insulating barrier figure
The justified margin of shape.
Array base palte the most according to claim 6, it is characterised in that the thickness of insulating layer under described conductive pattern is more than it
Thickness of insulating layer at his region.
Array base palte the most according to claim 6, it is characterised in that the layer pattern corresponding with described conductive pattern
Marginal existence has slope.
Array base palte the most according to claim 6, it is characterised in that described conductive pattern is source electrode, drain electrode, data
Line, gate electrode, grid line or pixel electrode.
10. a display device, it is characterised in that include the array base palte as according to any one of claim 6-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310713498.1A CN103700670B (en) | 2013-12-20 | 2013-12-20 | Array base palte and preparation method thereof, display device |
| PCT/CN2014/078923 WO2015090008A1 (en) | 2013-12-20 | 2014-05-30 | Array substrate and manufacturing method therefor, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310713498.1A CN103700670B (en) | 2013-12-20 | 2013-12-20 | Array base palte and preparation method thereof, display device |
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| Publication Number | Publication Date |
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| CN103700670A CN103700670A (en) | 2014-04-02 |
| CN103700670B true CN103700670B (en) | 2016-08-17 |
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| WO (1) | WO2015090008A1 (en) |
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| CN103700670B (en) * | 2013-12-20 | 2016-08-17 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN106086797B (en) * | 2016-07-12 | 2018-12-11 | 京东方科技集团股份有限公司 | Indium tin oxide films and preparation method thereof, the array substrate containing it, display device |
| CN108987411A (en) * | 2017-06-02 | 2018-12-11 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display device |
| CN114924437B (en) * | 2022-05-20 | 2024-01-12 | 北京京东方技术开发有限公司 | Array substrate, preparation method thereof and display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983568A (en) * | 2005-12-14 | 2007-06-20 | 韩国科学技术院 | Integrated thin-film solar cell and method of manufacturing the same |
| CN101833204A (en) * | 2009-03-13 | 2010-09-15 | 北京京东方光电科技有限公司 | Array substrate as well as manufacturing method and liquid crystal display panel thereof |
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| KR100617056B1 (en) * | 2004-12-30 | 2006-08-30 | 동부일렉트로닉스 주식회사 | The method for preventing attack during via etching |
| CN100456089C (en) * | 2006-03-09 | 2009-01-28 | 北京京东方光电科技有限公司 | Pixel structure of LCD array substrate and method for making same |
| KR101968115B1 (en) * | 2012-04-23 | 2019-08-13 | 엘지디스플레이 주식회사 | Array substrate and method of fabricating the same |
| CN202948924U (en) * | 2012-09-13 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and display device |
| CN103700670B (en) * | 2013-12-20 | 2016-08-17 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
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2013
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1983568A (en) * | 2005-12-14 | 2007-06-20 | 韩国科学技术院 | Integrated thin-film solar cell and method of manufacturing the same |
| CN101833204A (en) * | 2009-03-13 | 2010-09-15 | 北京京东方光电科技有限公司 | Array substrate as well as manufacturing method and liquid crystal display panel thereof |
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|---|---|
| WO2015090008A1 (en) | 2015-06-25 |
| CN103700670A (en) | 2014-04-02 |
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