CN101833204A - Array substrate as well as manufacturing method and liquid crystal display panel thereof - Google Patents
Array substrate as well as manufacturing method and liquid crystal display panel thereof Download PDFInfo
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- CN101833204A CN101833204A CN200910079952A CN200910079952A CN101833204A CN 101833204 A CN101833204 A CN 101833204A CN 200910079952 A CN200910079952 A CN 200910079952A CN 200910079952 A CN200910079952 A CN 200910079952A CN 101833204 A CN101833204 A CN 101833204A
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Abstract
The invention relates to an array substrate as well as a manufacturing method and a liquid crystal display panel thereof. A groove is formed on a passivation layer of the array substrate and correspondingly formed between two adjacent pixel electrodes; and the depth of the groove is less than that of the passivation layer. The method comprises the following steps of: forming patterns with a plurality of film layers on the substrate; forming the passivation layer on the substrate with the plurality of film layers forming; forming a passivation layer through hole and the groove on the passivation layer; depositing a transparent conducting film layer on the passivation layer with the groove forming; and forming a plurality of pixel electrodes in a matrix mode by adopting a mapping process. The liquid crystal display panel comprises the array substrate. In the invention, the groove is formed on the passivation layer beyond the pixel electrode area, therefore, a pixel electrode material layer can form a faultage at the edge of the groove, and the connected short-circuit between the adjacent pixel electrodes is reduced or avoided, thereby improving the finished product ratio.
Description
Technical field
The present invention relates to lcd technology, relate in particular to a kind of array base palte and manufacture method thereof and liquid crystal panel.
Background technology
LCD occupies critical role in flat-panel monitor, wherein, and Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display; Hereinafter to be referred as: TFT-LCD) be widely used a kind of LCD.
The liquid crystal panel of TFT-LCD is formed box by array base palte and color membrane substrates, and Fig. 1 is the fragmentary top TV structure synoptic diagram of a kind of thin-film transistor LCD device array substrate in the prior art, and Fig. 2 is that A-A among Fig. 1 is to cut-open view.As depicted in figs. 1 and 2, typical TFT-LCD array base-plate structure mainly comprises: underlay substrate 1; On underlay substrate 1, form the pattern of gate electrode 4 and controlling grid scan line 2, and form the pattern of public electrode 5; On gate electrode 4 and controlling grid scan line 2, form gate insulator 6; Form the pattern of semiconductor layer 7, doping semiconductor layer 8, source electrode 9, drain electrode 10 and data scanning line 3 on the gate insulator 6; On above-mentioned pattern, form passivation layer 11 again; On passivation layer 11, form the pattern of pixel electrode 13, and pixel electrode 13 is communicated with drain electrode 10 by passivation layer via hole 12.
By as can be seen shown in Figure 1, the pattern of pixel electrode is matrix form and arranges, respectively corresponding each pixel region, but existing TFT-LCD exists following defective: in manufacture process, pixel electrode normally at first deposits the layer of transparent conductive film layer on passivation layer, then adopt the exposure etching technics to etch the pattern of each piece pixel electrode.In etching process, because indium tin oxide (Indium Tin Oxides; Hereinafter to be referred as: there are influences such as interfacial diffusion between transparent conductive film layer ITO) and the lower floor's passivation layer film, may be behind the etching technics at the residual ITO of lower floor's passivation layer surface.Residual ITO may cause adjacent pixel electrodes to be communicated with short circuit, is presented to and promptly shows as the defective that bright spot or dim spot occur on the LCD, if there is the residual ITO of large tracts of land, " group's brightness " phenomenon that a plurality of bright spots join together then may occur, and makes product rejection.Generally can reduce the residual occurrence probability of ITO in the prior art by the technological parameter in the adjusting process process, but can't solve the residual harmful effect that brings of ITO effectively, it is more remarkable that especially the less interval between the pixel electrode is subjected to the residual influence of ITO.
Summary of the invention
The purpose of this invention is to provide a kind of array base palte and manufacture method thereof and liquid crystal panel, the influence of product is improved yield rate with residue after the reduction pixel electrode material etching.
For achieving the above object, the invention provides a kind of array base palte, comprise underlay substrate and on many thin layers, described many thin layers comprise controlling grid scan line, data scanning line and thin film transistor (TFT), on described many thin layers, be coated with passivation layer, a plurality of pixel electrodes that matrix form is arranged on the described passivation layer, wherein: be formed with groove on the described passivation layer, and described groove correspondence is formed between two adjacent pixel electrodes; The degree of depth of described groove is less than the thickness of described passivation layer.
For achieving the above object, the present invention also provides a kind of manufacture method of array base palte, comprising:
Form the pattern of many thin layers on underlay substrate, described many thin layers comprise controlling grid scan line, data scanning line and thin film transistor (TFT);
On the underlay substrate that forms described many thin layers, form passivation layer;
Form passivation layer via hole and groove on described passivation layer, the degree of depth of described groove is less than the thickness of described passivation layer;
Deposition of transparent conductive film layer on the passivation layer that forms described groove;
Adopt composition technology etching transparent conductive film layer to form a plurality of pixel electrodes of matrix form, described groove correspondence is formed between two adjacent pixel electrodes.
For achieving the above object, the present invention provides a kind of liquid crystal panel that comprises array base palte of the present invention again, also comprises color membrane substrates, and described array base palte and color membrane substrates are filled with liquid crystal layer therebetween to the box setting.
By above technical scheme as can be known, the present invention adopts the technological means that forms groove on the passivation layer in zone between two pixel electrodes, make when the deposition of transparent conductive film layer, can form tomography or increase distance between two pixel electrode pattern in the edge of groove, then after the etching pixel electrode pattern, even the transparent conductive material residue is arranged, but because the existence of tomography or the increase of distance, also can reduce or avoid the connection short circuit of adjacent pixel electrodes, therefore can reduce after the pixel electrode material etching residue to the influence of product, improve yield rate, improve the picture display quality.
Description of drawings
Fig. 1 is the fragmentary top TV structure synoptic diagram of a kind of thin-film transistor LCD device array substrate in the prior art;
Fig. 2 is that A-A among Fig. 1 is to cut-open view;
Fig. 3 is the fragmentary top TV structure synoptic diagram of array base palte first embodiment of the present invention;
Fig. 4 is that B-B among Fig. 3 is to cut-open view;
Fig. 5 is that C-C among Fig. 3 is to cut-open view;
Fig. 6 is the longitudinal cross-section synoptic diagram one of groove among array base palte first embodiment of the present invention;
Fig. 7 is the longitudinal cross-section synoptic diagram two of groove among array base palte first embodiment of the present invention;
Fig. 8 is the longitudinal cross-section synoptic diagram three of groove among array base palte first embodiment of the present invention;
Fig. 9 is the fragmentary top TV structure synoptic diagram of array base palte second embodiment of the present invention;
Figure 10 is that D-D among Fig. 9 is to cut-open view;
Figure 11 is the process flow diagram of manufacture method first embodiment of array base palte of the present invention;
Figure 12 is the process flow diagram of manufacture method second embodiment of array base palte of the present invention;
Figure 13 is the local longitudinal sectional view one of array base palte among manufacture method second embodiment of array base palte of the present invention;
Figure 14 is the local longitudinal sectional view two of array base palte among manufacture method second embodiment of array base palte of the present invention;
Figure 15 is the local longitudinal sectional view three of array base palte among manufacture method second embodiment of array base palte of the present invention;
Figure 16 is the local longitudinal sectional view four of array base palte among manufacture method second embodiment of array base palte of the present invention;
Figure 17 is the local longitudinal sectional view five of array base palte among manufacture method second embodiment of array base palte of the present invention;
Figure 18 is the local longitudinal sectional view six of array base palte among manufacture method second embodiment of array base palte of the present invention.
Among the figure:
1-underlay substrate 2-controlling grid scan line 3-data scanning line
4-gate electrode 5-public electrode 6-gate insulator
7-semiconductor layer 8-doping semiconductor layer 9-source electrode
10-drain electrode 11-passivation layer 12-passivation layer via hole
13-pixel electrode 14-groove 15-pixel electrode material residue
16-photoresist 17-mask plate 18-removes the zone fully
The complete reserve area of 19-half reserve area 20-
Embodiment
Also in conjunction with the accompanying drawings the present invention is described in further detail below by specific embodiment.
Array base palte first embodiment
Fig. 3 is the fragmentary top TV structure synoptic diagram of array base palte first embodiment of the present invention, Fig. 4 be B-B among Fig. 3 to cut-open view, Fig. 5 is that C-C among Fig. 3 is to cut-open view.The array base palte of present embodiment is specially the array base palte among the TFT-LCD, its primary structure comprises: underlay substrate 1 and on many thin layers, be coated with passivation layer 11 on many thin layers, corresponding each pixel region is formed with a plurality of pixel electrodes 13 of matrix form on the passivation layer 11.Underlay substrate 1 generally is a glass substrate.Many thin layers are to be used to control the voltage on each pixel electrode 13 so that present the structure of respective image, in TFT-LCD, many thin layers are specially thin film transistor (TFT) and drive array, and its structure generally comprises controlling grid scan line 2, data scanning line 3, gate electrode 4, semiconductor layer 7, doping semiconductor layer 8, source electrode 9 and drain electrode 10.Be illustrated in figure 3 as a kind of form in the thin film transistor (TFT) driving array structure.Wherein several data scanning lines 3 are vertical setting, and several controlling grid scan lines 2 are horizontally set, and data scanning line 3 and controlling grid scan line 2 intersections surround each pixel region.In each pixel region, be formed with the gate electrode 4 that links to each other with controlling grid scan line 2 respectively, in the present embodiment with the part in the controlling grid scan line 2 as gate electrode 4; The source electrode 9 that links to each other with data scanning line 3; And the drain electrode 10 that links to each other with pixel electrode 13 by passivation layer via hole 12.Source electrode 9 and drain electrode 10 are formed on the top of gate electrode 4, be provided with semiconductor layer 7 therebetween, and between source electrode 9 and drain electrode 10 and semiconductor layer 7, be provided with doping semiconductor layer 8, promptly form the TFT raceway groove between source electrode 9 and the drain electrode 10, data scanning line 3 utilizes same mask plate etching to form with the pattern of semiconductor layer 7 and doping semiconductor layer 8, therefore at the data scanning line semiconductor layer 7 and doping semiconductor layer 8 are also arranged for 3 times, this does not influence the function of data scanning line 3.On array base palte, generally also be provided with public electrode, public electrode can adopt the electrically conducting transparent material to make, provide common electric voltage as storage capacitor electrode, form electric field with the voltage of pixel electrode 13, the concrete pattern of public electrode is various, can design as the case may be, also public electrode can be set.
The longitudinal cross-section shape of groove 14 is specifically as follows the sidewall of groove 14 perpendicular to underlay substrate 1, and for example the longitudinal cross-section of groove 14 is shaped as rectangle, and as shown in Figure 4, the groove 14 of vertical sidewall can form by dry etching passivation layer 11.
The array base palte of present embodiment, owing on the passivation layer between the pixel electrode 13 11, be formed with the groove 14 of vertical sidewall, so even the residue of transparent conductive film layer is arranged on the passivation layer 11, it is pixel electrode material residue 15, because groove 14 sidewalls are vertical, can form the tomography of transparent conductive film layer at groove 14 sidewall edge places, as shown in Figure 4, the degree of depth of groove 14 should satisfy the requirement that forms pixel electrode 13 material tomographies at least, and the thickness of passivation layer 11 (PVX) can be 3000 dusts usually
So pixel electrode material residue 15 can't be communicated with short circuit with adjacent pixel electrodes 13, therefore can reduce even eliminate the influence of 15 pairs of lcd products of pixel electrode material residue, thereby improves yield rate.
In the present embodiment, it is vertical that the shape of groove is not limited to sidewall, can also be that the uncovered center position to groove of groove draws in.Be illustrated in figure 6 as the longitudinal cross-section synoptic diagram one of groove among array base palte first embodiment of the present invention, the longitudinal cross-section shape of groove can be trapezoidal for what just putting, be illustrated in figure 7 as the longitudinal cross-section synoptic diagram two of groove among array base palte first embodiment of the present invention, the longitudinal cross-section shape of groove can also be crown for satisfying the circle that uncovered center position to groove draws in.When adopting different technological means to form the groove of above-mentioned shape, can make the transparent conductive film layer on the passivation layer form tomography at the slot wedge place, avoid pixel electrode material residue to make each piece pixel electrode be communicated with short circuit.
Perhaps, the shape of groove also can be illustrated in figure 8 as the longitudinal cross-section synoptic diagram three of groove among array base palte first embodiment of the present invention for inverted trapezoidal.Because the setting of groove has been equivalent to increase the distance between the pixel electrode pattern of groove both sides, therefore when the etching pixel electrode pattern, help avoiding the connection short circuit between two pixel electrode pattern.
Array base palte second embodiment
Fig. 9 is the fragmentary top TV structure synoptic diagram of array base palte second embodiment of the present invention, and Figure 10 is that D-D among Fig. 9 is to cut-open view.In the array base palte of present embodiment, the structure of many thin layers still comprises controlling grid scan line 2, data scanning line 3, gate electrode 4, public electrode 5, semiconductor layer 7, doping semiconductor layer 8, source electrode 9 and drain electrode 10.Be with the difference of above-mentioned first embodiment: gate electrode 4 is outstanding to pixel electrode 13 directions from controlling grid scan line 2, on the jag of gate electrode 4, be formed with semiconductor layer 7 and doping semiconductor layer 8, source electrode 9 and drain electrode 10 lay respectively on the doping semiconductor layer 8, form the TFT raceway groove between source electrode 9 and the drain electrode 10.
Adopt different manufacture craft flow processs just can form different many film layer structure, each functional part can get final product in performance effect itself on many thin layers, and its relative position relation is not only.The concrete structure of many thin layers is not limited to patternings such as the controlling grid scan line, data scanning line described in the embodiment of the invention, can drive the pixel electrode conducting and get final product.
In the present embodiment, this array base palte is specially and adopts fringe field switching (Fringe Field Switching; Hereinafter to be referred as: the FFS) array base palte in a kind of wide viewing angle LCD of technology.To be each piece pixel electrode 13 have many parallel strip slits as Fig. 9 with shown in Figure 10 to the characteristics of this array base palte, and pixel electrode 13 links to each other with drain electrode 10 by passivation layer via hole 12.Groove 14 on the passivation layer 11 also is formed on the zone in corresponding each slit in pixel electrode 13 patterns, in order to avoid pixel electrode 13 should be communicated with because of existing of pixel electrode material residue 15 with the pixel electrode bar that the slit separates.On the array base palte of FFS structure, should be provided with public electrode 5, the design of public electrode 5 is various informative, public electrode 5 in the present embodiment specifically can adopt transparent conductive material to be formed on the underlay substrate 1, be shaped as the bulk in respective pixel district, and keep apart mutually with the pattern of controlling grid scan line 2.
Adopt the technical scheme of present embodiment, can prevent that not only the residue of pixel electrode material from forming the connection short circuit between the pixel electrode of each piece pixel region, the part that can also avoid any pixel electrode to separate is connected.Thereby guarantee the yield rate of LCD, avoid taking place the demonstration bad phenomenon of products such as " bright spots ".
Pixel electrode pattern on the array base palte of the present invention is not limited to above-mentioned two kinds, can design the pattern of pixel electrode as required.In a plurality of pixel electrodes that matrix form is arranged, the pixel electrode pattern on the matrix dot has the slit, and then groove is formed in the slit, is communicated with the pixel electrode of avoiding separating.
Many thin layers on the array base palte of the present invention also are not limited to above-mentioned thin film transistor (TFT) and drive array, can also adopt the many thin layers according to other drive principle designs, and this is to not influence of the trench design on the passivation layer of the present invention.
Manufacture method first embodiment of array base palte
Figure 11 comprises the steps: for the process flow diagram of manufacture method first embodiment of array base palte of the present invention
Step 400, forming deposition of transparent conductive film layer on the fluted passivation layer;
The technical scheme of present embodiment, be formed with groove in the zone between the corresponding two adjacent pixel electrodes on the passivation layer, and the sidewall of groove is vertical, or the uncovered center position to groove of groove draws in, then during the deposition of transparent conductive film layer, transparent conductive film layer forms tomography in the edge of groove, can be referring to Fig. 4, even then there is pixel electrode material residue, but because the appearance of tomography, the pixel electrode material can not make pixel electrode be communicated with short circuit, perhaps, the existence of groove has increased the distance between the pixel electrode pattern, helps etching and disconnects the adjacent pixel electrodes pattern, also can effectively avoid the connection short circuit between the pixel electrode pattern.Therefore can improve the yield rate of LCD, avoid occurring the demonstration bad phenomenon of products such as " bright spots ".
Manufacture method second embodiment of array base palte
Figure 12 is the process flow diagram of manufacture method second embodiment of array base palte of the present invention, and present embodiment is specifically based on above-mentioned first embodiment, and is specially the array base palte among the manufacturing TFT-LCD, and then above-mentioned steps 100 specifically comprises:
Then execution in step 200, and the material of deposit passivation layer 11 on the underlay substrate 1 of completing steps 120 forms passivation layer 11, as shown in figure 13.
Step 300 can be for adopting gray tone mask (Gray Tone Mask; Hereinafter to be referred as: GTM) or intermediate tone mask (Half Tone Mask; Hereinafter to be referred as: HTM) technology etching on passivation layer 11 forms groove 14, and step 300 specifically can comprise the steps:
Then execution in step 400:
Step 400, on the passivation layer 11 that is formed with groove 14 the deposition of transparent conductive film layer, for example deposit the ITO layer;
Composition technologies such as step 500, employing mask and etching form a plurality of pixel electrodes 13 of matrix form in pixel electrode area, as shown in figure 18, because the sidewall of groove 14 is vertical,, pixel electrode 13 can be communicated with short circuit so pixel electrode material residue forms tomography at the sidewall edge place.
When making the array base palte of FFS structure, by adopting the mask plate of suitable pattern, can on passivation layer, form the pixel electrode of corresponding pattern, each pixel electrode pattern has a plurality of strips slit, the groove correspondence is formed between two adjacent pixel electrodes, and groove also is formed on the zone in corresponding slit in the pixel electrode pattern.
The technical scheme of present embodiment can utilize HTM or GTM technology etching on passivation layer to form groove, need not to increase the mask number of times, so operation is simple, is easy to improve in prior art processes.The groove of dry etching has vertical sidewall, can make residual pixel electrode material form tomography, therefore can avoid pixel electrode to be communicated with short circuit, thereby improve the yield rate of LCD, avoids occurring the demonstration bad phenomenon of products such as " bright spots ".
The technical scheme that each embodiment of the manufacture method of array base palte of the present invention can be used to make the arbitrary embodiment of array base palte of the present invention, can effectively reduce the harmful effect that pixel electrode material residue connected pixel electrode causes, improve yield rate, and implementation method is simple, is easy to promote.
Liquid crystal panel embodiment
Liquid crystal panel embodiment of the present invention comprises array base palte of the present invention, and also comprises color membrane substrates, and array base palte and color membrane substrates are filled with liquid crystal layer therebetween to the box setting.Liquid crystal panel cooperates other necessary control modules and module backlight can constitute LCD.
Adopt the liquid crystal panel of array base palte of the present invention, be not prone to the defective that pixel electrode is communicated with short circuit, then bad problem such as " bright spot " demonstration can not appear in LCD, and picture quality significantly improves.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. array base palte, comprise underlay substrate and on many thin layers, described many thin layers comprise controlling grid scan line, data scanning line and thin film transistor (TFT), on described many thin layers, be coated with passivation layer, a plurality of pixel electrodes that matrix form is arranged on the described passivation layer, it is characterized in that: be formed with groove on the described passivation layer, and described groove correspondence is formed between two adjacent pixel electrodes; The degree of depth of described groove is less than the thickness of described passivation layer.
2. array base palte according to claim 1 is characterized in that: described groove is the strip distribution along controlling grid scan line and/or data scanning line direction.
3. array base palte according to claim 1, in a plurality of pixel electrodes of described matrix form, each pixel electrode pattern has a plurality of strips slit, it is characterized in that: groove also is formed on the zone in corresponding described slit in the pixel electrode pattern.
4. array base palte according to claim 1 is characterized in that: the sidewall of described groove draws in perpendicular to the uncovered center position to described groove of described underlay substrate or described groove.
5. the manufacture method of an array base palte is characterized in that, comprising:
Form the pattern of many thin layers on underlay substrate, described many thin layers comprise controlling grid scan line, data scanning line and thin film transistor (TFT);
On the underlay substrate that forms described many thin layers, form passivation layer;
Form passivation layer via hole and groove on described passivation layer, the degree of depth of described groove is less than the thickness of described passivation layer;
Deposition of transparent conductive film layer on the passivation layer that forms described groove;
Adopt composition technology etching transparent conductive film layer to form a plurality of pixel electrodes of matrix form, described groove correspondence is formed between two adjacent pixel electrodes.
6. the manufacture method of array base palte according to claim 5 is characterized in that, adopts composition technology etching transparent conductive film layer to form a plurality of pixel electrodes of matrix form, and described groove correspondence is formed between two adjacent pixel electrodes and is specially:
Adopt composition technology etching transparent conductive film layer with in a plurality of pixel electrodes that form matrix form, each pixel electrode pattern has a plurality of strips slit, and described groove also is formed on the zone in corresponding described slit in the pixel electrode pattern.
7. the manufacture method of array base palte according to claim 5 is characterized in that, the pattern that forms many thin layers on underlay substrate specifically comprises:
On described underlay substrate, deposit the grid metal level, on described underlay substrate, form the pattern of controlling grid scan line and gate electrode by composition technology;
On the underlay substrate that forms described controlling grid scan line and gate electrode, deposit gate insulator, semiconductor film, doped semiconductor rete and source and leak metallic diaphragm, adopt composition technology on described gate insulator, to form the pattern of data scanning line, semiconductor layer, doping semiconductor layer, source electrode and drain electrode, with described controlling grid scan line and gate electrode jointly as described many thin layers, form thin film transistor channel between described source electrode and the drain electrode.
8. according to the manufacture method of the arbitrary described array base palte of claim 5～7, it is characterized in that formation passivation layer via hole and groove specifically comprise on described passivation layer:
On described passivation layer, apply photoresist;
With gray mask plate or half-tone mask plate described photoresist is carried out the exposure imaging operation, form and remove zone, half reserve area and complete reserve area fully, the zone of corresponding described groove is half reserve area, the zone of corresponding passivation layer via hole is for removing the zone fully, the removal of all developing of the photoresist of removing the zone fully, the photoresist of half reserve area keeps sets thickness, and the photoresist of reserve area all keeps fully;
Adopt the dry etching passivation layer, remove the passivation layer in zone fully by partial etching;
The residue photoresist is carried out ashing treatment, remove the photoresist of setting thickness, the photoresist of described half reserve area is removed fully, and the photoresist of described complete reserve area keeps sets thickness;
Adopt the dry etching passivation layer, the passivation layer of reserve area is etched and sets thickness to form described groove fully, and the passivation layer of removing the zone is simultaneously fully etched away fully to form passivation layer via hole;
Peel off the residue photoresist.
9. liquid crystal panel that comprises the arbitrary described array base palte of claim 1～4, it is characterized in that: also comprise color membrane substrates, described array base palte and color membrane substrates are filled with liquid crystal layer therebetween to the box setting.
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| CN113097272A (en) * | 2021-03-29 | 2021-07-09 | 鄂尔多斯市源盛光电有限责任公司 | Display back plate, manufacturing method thereof and display device |
| CN113097272B (en) * | 2021-03-29 | 2023-09-22 | 鄂尔多斯市源盛光电有限责任公司 | Display backboard, manufacturing method thereof and display device |
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Application publication date: 20100915 |