CN103295953A - Formation method of semiconductor device - Google Patents
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- CN103295953A CN103295953A CN2013102049906A CN201310204990A CN103295953A CN 103295953 A CN103295953 A CN 103295953A CN 2013102049906 A CN2013102049906 A CN 2013102049906A CN 201310204990 A CN201310204990 A CN 201310204990A CN 103295953 A CN103295953 A CN 103295953A
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Abstract
A formation method of a semiconductor device includes: providing a substrate; forming shallow trenches in the substrate; forming transistors on the surface of the substrate in an area enclosed by the shallow trenches; forming an interlayer dielectric layer which cover the transistors and fill the shallow trenches. The shallow trenches are filled after the transistors are formed, so that after the shallow trenches are filled by silicon oxide and the shallow trench isolation structure is formed, the semiconductor material of sidewalls of the shallow trenches is prevented from being continuously oxidized, formation of larger oxide is prevented and pressure stress is introduced to the trench areas of the transistors. The formed NMOS (N-channel metal oxide semiconductor) transistors have better performance. In addition, the formation process is simple, and the process steps are few.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of semiconductor device.
Background technology
Semiconductor device continues to develop towards integrated, the high service speed of height and low-power consumption direction, silicon-on-insulator substrate has the medium of realizing components and parts in the integrated circuit and isolates, thoroughly eliminates that parasitic latch-up, parasitic capacitance in the body silicon CMOS circuit is little, integration density is high, speed is fast, technology is simple, short-channel effect is little and be applicable to advantage such as low-power consumption low voltage circuit, therefore, utilizing silicon-on-insulator substrate to form semiconductor device more and more is much accounted of.
The formation method of the semiconductor device of prior art comprises:
Please refer to Fig. 1, silicon-on-insulator (SOI) substrate 100 is provided, and described silicon-on-insulator (SOI) substrate 100 comprises at the bottom of the backing 101, cover the buried oxide layer 103 on 101 surfaces at the bottom of the described backing and the top layer silicon 105 that covers described buried oxide layer 103 surfaces;
Please refer to Fig. 2, form the fleet plough groove isolation structure 107 that is positioned at described top layer silicon 105, the formation technology of described fleet plough groove isolation structure 107 is high density plasma deposition (HDP) technology, and its material is silica;
Please refer to Fig. 3, form the transistor 109 that is positioned at described top layer silicon 105 surfaces, the zone of described transistor 109 between adjacent fleet plough groove isolation structure 107;
Please refer to Fig. 4, form the interlayer dielectric layer 111 that covers described transistor 109, fleet plough groove isolation structure 107.After above-mentioned steps is finished, the completing of the semiconductor device of prior art.Yet in the semiconductor device that prior art forms, the raceway groove of nmos pass transistor is subjected to compression descends carrier mobility, causes device performance to descend.
More formation methods about semiconductor device please refer to publication number and are the United States Patent (USP) of " US7871878B2 ".
Summary of the invention
The problem that the present invention solves provides a kind of formation method of semiconductor device, and the performance of the semiconductor device of formation is better.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising: substrate is provided; Formation is positioned at described intrabasement shallow trench; Formation is positioned at the transistor of described substrate surface, and described transistor is positioned at by the shallow trench area surrounded; Form and cover described transistorized interlayer dielectric layer, described interlayer dielectric layer is filled full described shallow trench.
Alternatively, described substrate is semiconductor-on-insulator substrate, at the bottom of comprising backing, cover the buried oxide layer of described backing basal surface and the top-layer semiconductor that covers described buried oxide laminar surface, described shallow trench is formed in the top-layer semiconductor, and exposes the buried oxide laminar surface.
Alternatively, also comprise: before forming described transistor, adopt thermal oxidation technology that the sidewall of described shallow trench is repaired.
Alternatively, the reaction temperature during described thermal oxidation technology is 600 degrees centigrade-1150 degrees centigrade.
Alternatively, after the sidewall of described shallow trench repaired, oxidated layer thickness 20 dusts-500 dust of formation.
Alternatively, also comprise: before forming described transistor, form side wall at described shallow trench sidewall, and the angle of the sidewall of described side wall and described substrate surface is less than 90 degree.
Alternatively, the formation technology of described side wall is chemical vapor deposition method.
Alternatively, the angle of the sidewall of described side wall and described substrate surface is 30 degree-85 degree.
Alternatively, also comprise: before forming shallow trench, form the protective layer that covers described substrate surface.
Alternatively, described transistor is nmos pass transistor.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form shallow trench in substrate after, formation earlier is positioned at the transistor that is surrounded by shallow trench, and then forms interlayer dielectric layer, and described interlayer dielectric layer not only covers substrate surface and transistor surface, also fills full described shallow trench.Because shallow trench is filled after forming transistor, avoided after common shallow trench isolation is filled the formation fleet plough groove isolation structure from oxidized silicon, the semi-conducting material of shallow trench sidewall is continued oxidation, forms the bigger oxide of volume, introduces compression in the transistorized channel region and make.The performance of the semiconductor device that forms is good, and the performance of nmos pass transistor is better.And above-mentioned formation technology is simple, and processing step is few.
Further, form described transistor before, form side wall at described shallow trench sidewall, and the angle of the sidewall of described side wall and described substrate surface is spent less than 90.Make that the step of follow-up filling shallow trench formation fleet plough groove isolation structure is smooth, and have the space in the fleet plough groove isolation structure of avoiding forming, strengthened the isolation effect of fleet plough groove isolation structure, further improved the performance of semiconductor device.And, if polysilicon gate forms behind shallow trench, because the shallow trench sidewall is formed with side wall, easier to be clean unwanted polysilicon etching when making the etching polysilicon gate, it is residual to avoid forming polysilicon film at the shallow trench sidewall, cause short circuit between the adjacent polysilicon gate, further improved the performance of semiconductor device.
Further, before the formation shallow trench, form the protective layer (PAD Oxide) that covers described substrate surface, effectively avoided photoresist layer directly to contact with substrate, when subsequent etching, substrate is polluted, further improved the performance of semiconductor device.
Description of drawings
Fig. 1-Fig. 4 is the cross-sectional view of forming process of the semiconductor device of prior art;
Fig. 5-Figure 10 is the cross-sectional view of the forming process of semiconductor device of the present invention.
Embodiment
Just as stated in the Background Art, the performance of the performance of the semiconductor device of prior art, especially nmos pass transistor descends.
Through research, the inventor finds, prior art forms shallow trench usually in top layer silicon after, full dielectric material will be filled earlier in the described shallow trench, after forming fleet plough groove isolation structure, silicon face forms transistor on the SI semi-insulation body that is surrounded by fleet plough groove isolation structure again, forms at last to cover described fleet plough groove isolation structure and transistorized interlayer dielectric layer.Because transistor forms after forming fleet plough groove isolation structure, when form constituting described transistorized grid oxide layer, oxygen is diffused into the sidewall of fleet plough groove isolation structure by the silica of having filled in the fleet plough groove isolation structure, inevitably can react with the silicon of shallow trench sidewall, form silica, than silicon, the volume of silica increases, and since this moment shallow trench be filled, the silica of the larger volume of formation can produce compression (among Fig. 4 shown in the arrow) at transistorized channel region.
And prior art usually can form sacrificial oxide layer on the top layer silicon surface after forming fleet plough groove isolation structure, in order to protecting group basal surface when injecting ion in basad.When forming described sacrificial oxide layer, also have the sidewall that oxygen diffuses to fleet plough groove isolation structure, react with the silicon of shallow trench sidewall, form silica, thereby further produce compression at transistorized channel region.
Though for the PMOS transistor, wish usually to introduce bigger compression at its channel region, to improve the carrier mobility of its channel region, yet, for nmos pass transistor, then wish to introduce bigger tension stress at its channel region, to improve the carrier mobility of nmos pass transistor channel region.Obviously, the formation method of the semiconductor device of prior art can have influence on the carrier mobility of the channel region of nmos pass transistor.Need in the high application of NMOS performance height, drive current at some, the stress that above-mentioned stress causes the NMOS performance to descend need be considered and improve.
After further research, the inventor has found a kind of formation method of semiconductor device, after forming shallow trench, does not fill earlier described shallow trench, but after forming transistor, described shallow trench is filled full when forming interlayer dielectric layer.This kind formation method, when the semi-conducting material of oxygen and shallow trench sidewall reacts the formation oxide, empty shallow trench provides the space that discharges for stress, therefore the oxide that forms can not produce compression at transistorized channel region, the transistorized carrier mobility that forms is not subjected to the influence of described oxide, and the performance of nmos pass transistor is better.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Please refer to Fig. 5, substrate 200 is provided.
Described substrate 200 is used to subsequent technique that platform is provided.Described substrate 200 is body silicon substrate or semiconductor-on-insulator substrate.When described substrate 200 is semiconductor-on-insulator substrate, comprising: at the bottom of the backing 201, cover the buried oxide layer 203 on 201 surfaces at the bottom of the described backing and the top-layer semiconductor 205 that covers described buried oxide layer 203 surfaces.Wherein, 201 material is semi-conducting material at the bottom of the described backing, for example monocrystalline silicon, monocrystalline germanium or SiGe etc.; The material of described buried oxide layer 203 is silica or germanium oxide etc.; The material of described top-layer semiconductor 205 is monocrystalline silicon, monocrystalline germanium or SiGe etc.In the embodiments of the invention, described substrate 200 is silicon-on-insulator (SOI) substrate, and 201 material is monocrystalline silicon at the bottom of the backing, and the material of buried oxide layer 203 is silica, and the material of described top-layer semiconductor 205 is monocrystalline silicon.
Need to prove; the formation shallow trench because the top-layer semiconductor 205 back extended meetings of described substrate 200 are etched; photoetching glue stain top-layer semiconductor 205 when avoiding etching technics; in the embodiments of the invention; also comprise: before forming shallow trench, form the protective layer (PAD Oxide) 206 that covers described substrate 200 surfaces.The material of described protective layer 206 is silica, and it forms technology is can be chemical vapor deposition method or thermal oxidation technology.
Need to prove, in an embodiment of the present invention, all right: as to form sacrificial oxide layers (not shown) on described protective layer 206 surfaces, 200 surfaces at the bottom of the protecting group when injecting ion in follow-up basad 200.Consider when forming described sacrificial oxide layer, because the intervention of oxygen is arranged, also oxidized portion shallow trench 207 sidewalls very easily, for transistorized channel region is introduced compression, for avoiding above-mentioned phenomenon, in the embodiments of the invention, described sacrificial oxide layer forms before forming fleet plough groove isolation structure.
Please refer to Fig. 6, form the shallow trench 207 that is positioned at described substrate 200.
Described shallow trench 207 is used for follow-up isolation adjacent transistors.The formation step of described shallow trench 207 comprises: form the photoresist layer (not shown) that covers described substrate 200 surfaces, described photoresist layer defines position and the size of described shallow trench 207; Be mask with described photoresist layer, the described substrate 200 of etching forms the shallow trench 207 that is positioned at described substrate 200.In the embodiments of the invention, because described substrate 200 is silicon-on-insulator (SOI), described shallow trench 207 forms after by the top layer silicon in the etching silicon-on-insulator, and described shallow trench 207 runs through described top layer silicon (being top-layer semiconductor 205), and exposes buried oxide layer 203 surfaces.
Need to prove, in the embodiments of the invention, when forming shallow trench 207, also comprise: be mask with described photoresist layer, the step of the described protective layer 206 of etching and sacrificial oxide layer does not repeat them here.The protection of protective layer 206 has been arranged just, just made described top layer silicon not contaminated.
Need to prove, be well known to those skilled in the art because etching forms the technology of described shallow trench 207, do not repeat them here.
Please refer to Fig. 7, behind the formation shallow trench 207, adopt thermal oxidation technology that the sidewall of described shallow trench 207 is repaired.
The inventor finds that in the process of aforementioned etching technics, the top-layer semiconductor of described shallow trench 207 sidewalls can be damaged, and for example makes that described sidewall is coarse, and the performance to subsequent technique and semiconductor device impacts easily.Therefore, also can repair the sidewall of described shallow trench 207.In the embodiments of the invention, select for use thermal oxidation technology that the sidewall of described shallow trench 207 is repaired.In thermal oxidation technology, the atom in the top-layer semiconductor moves, reconfigures, and reacts with oxygen, form to cover the oxide layer 209 of described shallow trench 207 sidewalls, efficiently solves problems such as sidewall is coarse.
In the embodiments of the invention, the reaction temperature during described thermal oxidation technology is 600 degrees centigrade-1150 degrees centigrade, and after the sidewall of described shallow trench 207 was repaired, oxide layer 209 thickness 20 dusts-500 dusts of formation had effectively improved shallow trench 207 sidewall surfaces.
Need to prove, because this moment, shallow trench 207 was not filled, can't produce stress when forming oxide layer.
Please refer to Fig. 8, form side wall 211 at described shallow trench 207 sidewalls, and the angle α on the sidewall of described side wall 211 and described substrate 200 surfaces is less than 90 degree.
In the semiconductor-on-insulator layer in the thickness smaller applications of top-layer semiconductor 205, the sidewall of the shallow trench that the described top-layer semiconductor 205 of etching forms is almost perpendicular to substrate 200, be unfavorable for follow-up filling shallow trench 207, form the good fleet plough groove isolation structure of isolation effect.And, if polysilicon gate is (follow-up as transistorized grid or pseudo-grid, not shown) form in shallow trench 207 backs, above-mentioned sidewall is unfavorable for also that perpendicular to the shallow trench 207 of substrate 200 the polysilicon removal that it is inner is clean, cause residual polycrystalline silicon in its inside, cause (being between the transistor) short circuit between the adjacent polysilicon gate.
After further research, the inventor finds, can form side wall 211 at described shallow trench 207 sidewalls, the sidewall of described side wall 211 and the angle α on described substrate 200 surfaces are spent less than 90, form the side wall 211 described shallow trenchs 207 in back cross section top dimension as shown in Figure 8 greater than bottom size, be trapezoidal, easier shallow trench 207 bottoms that enter of follow-up packing material, fill full described shallow trench 207, and can not produce the space, can effectively address the above problem, form the good fleet plough groove isolation structure of isolation effect.And, because shallow trench 207 sidewalls are formed with side wall 211, and are easier to be clean unwanted polysilicon etching when making the etching polysilicon gate, it is residual to avoid forming polysilicon film at shallow trench 207 sidewalls, cause short circuit between the adjacent polysilicon gate, further improved the performance of semiconductor device.
In the embodiments of the invention, angle when the sidewall of described side wall 211 and described substrate 200 surfaces is 30 degree-85 degree, the isolation effect of the fleet plough groove isolation structure that follow-up filling forms is best, and effectively avoided the residual polycrystalline silicon of shallow trench 207 sidewalls, the performance of the semiconductor device of formation is better.
The formation step of described side wall 211 comprises: adopt chemical vapor deposition method to form sidewall and the bottom that covers described shallow trench 207, and cover the side wall film on described substrate 200 surfaces; Dry etching is removed the side wall film of the bottom that is positioned at described substrate 200 surfaces and shallow trench 207 then, forms side wall 211.
The material of described side wall 211 is silica, silicon nitride or silicon oxynitride.In the embodiments of the invention, the material of described side wall 211 is silica.
Need to prove that in an embodiment of the present invention, described side wall 211 carries out after repairing the sidewall of shallow trench 207, the oxide layer 209 that forms during described reparation shallow trench 207 can not removed, and described side wall 211 directly is formed at oxide layer 209 sidewalls.Certainly, also can remove described oxide layer 209 after, form described side wall 211 again, do not repeat them here.
Please refer to Fig. 9, form described side wall 211 after, remove described protective layer 206(as shown in Figure 8), form the transistor 213 be positioned at described substrate 200 surfaces then, described transistor 213 is positioned at by shallow trench 207 area surrounded.
The technology of removing described protective layer 206 is etching technics, and wet-etching technology for example contacts so that have preferably between the transistor of follow-up formation 213 and the substrate 200, improves the performance of the transistor 213 that forms.
Described transistor 213 is as the important component part of semiconductor device.Classify from its structure, described transistor 213 can be planar transistor or non-planar transistor, divides from its doping type, and described transistor 213 can be CMOS transistor or nmos pass transistor.In the embodiments of the invention, described transistor is nmos pass transistor, follow-uply can be used to form radio-frequency (RF) switch.
The formation technology of described transistor 213 is well known to those skilled in the art, and does not repeat them here.
Need to prove that in the embodiments of the invention, described sacrificial oxide layer can be removed before forming transistor.
Please refer to Figure 10, form the interlayer dielectric layer 215 that covers described transistor 213, described interlayer dielectric layer 215 is filled full described shallow trench 207.
The formation technology of described interlayer dielectric layer 215 is chemical vapor deposition method.The interlayer dielectric layer 215 that forms not only covers the surface of substrate 200 surfaces and transistor 213, but also fills full described shallow trench 207, forms fleet plough groove isolation structure (not indicating).In the embodiments of the invention, owing to formed side wall 211 in the aforementioned technology, the technology of filling described shallow trench 207 is smooth, and does not have the space in the fleet plough groove isolation structure that forms, and its isolation effect is good.
Owing to fill the step of described shallow trench 207 forming transistor 213 back execution, effectively alleviated the generation of the compression of mentioning in the preamble, improved transistor, especially the performance of nmos pass transistor.And, in same processing step, both formed fleet plough groove isolation structure, covered transistor 213 and substrate 200 surfaces again, effectively saved processing step.
After above-mentioned steps is finished, the completing of the semiconductor device of the embodiment of the invention, the performance of the semiconductor device of formation is better.
To sum up, behind the formation shallow trench, formation earlier is positioned at the transistor that is surrounded by shallow trench, and then forms interlayer dielectric layer in substrate, and described interlayer dielectric layer not only covers substrate surface and transistor surface, also fills and expires described shallow trench.Because shallow trench is filled after forming transistor, avoided after common shallow trench isolation is filled the formation fleet plough groove isolation structure from oxidized silicon, the semi-conducting material of shallow trench sidewall is continued oxidation, forms the bigger oxide of volume, introduces compression in the transistorized channel region and make.The performance of the semiconductor device that forms is good, and the performance of nmos pass transistor is better.And above-mentioned formation technology is simple, and processing step is few.
Further, form described transistor before, form side wall at described shallow trench sidewall, and the angle of the sidewall of described side wall and described substrate surface is spent less than 90.Make that the step of follow-up filling shallow trench formation fleet plough groove isolation structure is smooth, and have the space in the fleet plough groove isolation structure of avoiding forming, strengthened the isolation effect of fleet plough groove isolation structure, further improved the performance of semiconductor device.And, if polysilicon gate forms behind shallow trench, because the shallow trench sidewall is formed with side wall, easier to be clean unwanted polysilicon etching when making the etching polysilicon gate, it is residual to avoid forming polysilicon film at the shallow trench sidewall, cause short circuit between the adjacent polysilicon gate, further improved the performance of semiconductor device.
Further, before the formation shallow trench, form the protective layer that covers described substrate surface, effectively avoided photoresist layer directly to contact with substrate, when subsequent etching, substrate is polluted, further improved the performance of semiconductor device.
Above-mentioned explanation by embodiment should be able to make this area professional and technical personnel understand the present invention better, and can reproduce and use the present invention.Those skilled in the art can do various changes to above-described embodiment under the situation that does not break away from the spirit and scope of the invention according to described principle herein and modification is apparent.Therefore, the present invention should not be understood that to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (10)
1. the formation method of a semiconductor device is characterized in that, comprising:
Substrate is provided;
Formation is positioned at described intrabasement shallow trench;
Formation is positioned at the transistor of described substrate surface, and described transistor is positioned at by the shallow trench area surrounded;
Form and cover described transistorized interlayer dielectric layer, described interlayer dielectric layer is filled full described shallow trench.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described substrate is semiconductor-on-insulator substrate, at the bottom of comprising backing, cover the buried oxide layer of described backing basal surface and the top-layer semiconductor that covers described buried oxide laminar surface, described shallow trench is formed in the top-layer semiconductor, and exposes the buried oxide laminar surface.
3. the formation method of semiconductor device as claimed in claim 1 is characterized in that, also comprises: before forming described transistor, adopt thermal oxidation technology that the sidewall of described shallow trench is repaired.
4. the formation method of semiconductor device as claimed in claim 3 is characterized in that, the reaction temperature during described thermal oxidation technology is 600 degrees centigrade-1150 degrees centigrade.
5. the formation method of semiconductor device as claimed in claim 3 is characterized in that, after the sidewall of described shallow trench is repaired, and oxidated layer thickness 20 dusts-500 dust of formation.
6. the formation method of semiconductor device as claimed in claim 1 is characterized in that, also comprises: before forming described transistor, form side wall at described shallow trench sidewall, and the angle of the sidewall of described side wall and described substrate surface is less than 90 degree.
7. the formation method of semiconductor device as claimed in claim 6 is characterized in that, the formation technology of described side wall is chemical vapor deposition method.
8. the formation method of semiconductor device as claimed in claim 6 is characterized in that, the sidewall of described side wall and the angle of described substrate surface are 30 degree-85 degree.
9. the formation method of semiconductor device as claimed in claim 1 is characterized in that, also comprises: before forming shallow trench, form the protective layer that covers described substrate surface.
10. the formation method of semiconductor device as claimed in claim 1 is characterized in that, described transistor is nmos pass transistor.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392955A (en) * | 2014-11-19 | 2015-03-04 | 上海华力微电子有限公司 | Method for improving SiC stress property of shallow trench isolation edge |
| CN104538347A (en) * | 2014-12-31 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Contact hole technological method |
| CN105632891A (en) * | 2014-11-28 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of PIP capacitor |
| CN111146090A (en) * | 2020-02-14 | 2020-05-12 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing SOI device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194283B1 (en) * | 1997-10-29 | 2001-02-27 | Advanced Micro Devices, Inc. | High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers |
| US20070069307A1 (en) * | 2005-09-27 | 2007-03-29 | Kentaro Eda | Semiconductor device and method of manufacturing the same |
| US20070148906A1 (en) * | 2005-12-28 | 2007-06-28 | Bong Jun Kim | Method of fabricating a semiconductor device |
| CN1992195A (en) * | 2005-12-28 | 2007-07-04 | 恩益禧电子股份有限公司 | Semiconductor device and fabrication method thereof |
| CN100407399C (en) * | 2004-12-03 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of adjusting transistor structural-stress in shallow trench isolation |
| CN101833204A (en) * | 2009-03-13 | 2010-09-15 | 北京京东方光电科技有限公司 | Array substrate as well as manufacturing method and liquid crystal display panel thereof |
-
2013
- 2013-05-28 CN CN2013102049906A patent/CN103295953A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194283B1 (en) * | 1997-10-29 | 2001-02-27 | Advanced Micro Devices, Inc. | High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers |
| CN100407399C (en) * | 2004-12-03 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method of adjusting transistor structural-stress in shallow trench isolation |
| US20070069307A1 (en) * | 2005-09-27 | 2007-03-29 | Kentaro Eda | Semiconductor device and method of manufacturing the same |
| US20070148906A1 (en) * | 2005-12-28 | 2007-06-28 | Bong Jun Kim | Method of fabricating a semiconductor device |
| CN1992195A (en) * | 2005-12-28 | 2007-07-04 | 恩益禧电子股份有限公司 | Semiconductor device and fabrication method thereof |
| CN101833204A (en) * | 2009-03-13 | 2010-09-15 | 北京京东方光电科技有限公司 | Array substrate as well as manufacturing method and liquid crystal display panel thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392955A (en) * | 2014-11-19 | 2015-03-04 | 上海华力微电子有限公司 | Method for improving SiC stress property of shallow trench isolation edge |
| CN105632891A (en) * | 2014-11-28 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of PIP capacitor |
| CN104538347A (en) * | 2014-12-31 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Contact hole technological method |
| CN111146090A (en) * | 2020-02-14 | 2020-05-12 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing SOI device |
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