CN104392955A - Method for improving SiC stress property of shallow trench isolation edge - Google Patents
Method for improving SiC stress property of shallow trench isolation edge Download PDFInfo
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- CN104392955A CN104392955A CN201410664627.7A CN201410664627A CN104392955A CN 104392955 A CN104392955 A CN 104392955A CN 201410664627 A CN201410664627 A CN 201410664627A CN 104392955 A CN104392955 A CN 104392955A
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- silicon
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- 238000002955 isolation Methods 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 71
- 239000010703 silicon Substances 0.000 claims abstract description 71
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 57
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 28
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 208000032750 Device leakage Diseases 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000002210 silicon-based material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000000227 grinding Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
Abstract
The invention provides a method for improving SiC stress property of a shallow trench isolation edge. The step of forming shallow trench isolation in a silicon substrate comprises the following steps of: depositing a silicon dioxide cushion layer and a silicon nitride cushion layer on the silicon substrate in sequence; actively photoetching and etching the silicon dioxide cushion layer, the silicon nitride cushion layer and the silicon substrate so as to form a groove in the silicon substrate, wherein an included angle between the lateral wall of the groove and the vertical line of the surface of a silicon wafer ranges from 15 degrees to 60 degrees; filling silicon dioxide in the groove and flattening the filled silicon dioxide through chemical and mechanical grinding to form a shallow trench isolation body; peeling off the silicon nitride cushion layer and the silicon dioxide cushion layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of method improving shallow groove isolation edge SiC stress performance.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element, in continuous reduction, generally includes the reduction of MOSFET element channel length, and the thinning grade of gate oxide thickness is to obtain device speed faster.But along with very large scale integration technology be developed to sub-micro level time, particularly when 90 nanometers and following technology node, reduce channel length and can bring series of problems, in order to control short-channel effect, the impurity with higher concentration can be mixed in channels, this can reduce the mobility of charge carrier, thus causes device performance to decline, and simple device size reduces to be difficult to the development meeting large scale integrated circuit technology.Therefore, the extensive research of stress engineering is used for improving the mobility of charge carrier, thus reaches device speed faster, and meets the rule of Moore's Law.
The eighties in last century, academia just started to realize heterostructure research based on silicon-based substrate, until just realize business application the beginning of this century to the nineties.Wherein have two kinds of representational stress application, one is biaxial stress technology (Biaxial Technique), another kind is simple stress technology (UniaxialTechnique), i.e. stress memory technique (Stress Memorization Technology), nCESL and selectivity (or embedding) epitaxial growth silicon-carbon SiC drain-source are (see document " K.W.Ang et a l., IEDMTech.Dig., pp.1069, 2004 " and document " Y.C.Liu et al., VLSI, pp.44-45, 2007 ") mobility that tensile stress improves electronics is applied to the raceway groove of NMOSFET, selectivity (or embedding) epitaxial growth Ge-Si SiGe, pCESL applies to PMOSFET raceway groove the mobility that compression improves hole, thus improve the performance of device, see Fig. 2.
At present, the research for SiC epitaxial growth technology mainly concentrates on the concentration how improving carbon in SiC, and the concentration of carbon is higher, and lattice mismatch is larger, and the stress of generation is larger, more remarkable to the raising of carrier mobility; In addition, the shape of SiC, SiC drain-source is close to the edge of polysilicon, and namely near device channel, stress more directly acts on the charge carrier of device channel, obvious to the lifting of device performance.
Research and development all are above all based on silicon substrate, that is, the seed that silicon substrate provides SiC to grow, SiC carries out epitaxial growth along the lattice of silicon, but, in semiconductor technology, electric isolation is realized by shallow ditch groove separation process (STI) between device, silicon dioxide is used to fill in STI, therefore at STI and active-surface, SiC epitaxy technique can be subject to the impact of STI, and STI can not provide enough silicon " seed ", just there will be STI edge, left and right sides SiC in SiC selective epitaxial process and grows and lowly even to lack.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of method can improving shallow groove isolation edge SiC stress performance.
In order to realize above-mentioned technical purpose, according to the present invention, providing a kind of method improving shallow groove isolation edge SiC stress performance, comprising: in a silicon substrate formed shallow trench isolation from, and manufacture with shallow trench isolation from the nmos device separated and/or PMOS device.
Preferably, in a silicon substrate formed carry out shallow trench isolation from step comprise the following step performed successively: at surface of silicon successively deposit bed course silicon dioxide layer and bed course silicon nitride layer; Active area photoetching and etching are carried out to form groove in a silicon substrate to bed course silicon dioxide layer, bed course silicon nitride layer and silicon substrate; Wherein, described groove sidewall relative to the line angulation vertical with silicon chip surface between 15 degree to 60 between; Fill silicon dioxide in a groove and by cmp, planarization carried out to obtain shallow trench isolating main bodies to the silicon dioxide of filling; Peel off bed course silicon nitride layer, and peel off bed course silicon dioxide layer.
Preferably, the sidewall of described groove relative to the line angulation vertical with silicon chip surface between 20 degree to 50 degree.
Preferably, the sidewall of described groove relative to the line angulation vertical with silicon chip surface between 30 degree to 45 degree.
Preferably, the sidewall of described groove is 35 degree or 40 degree relative to the line angulation vertical with silicon chip surface.
Preferably, manufacture and comprise the steps: to carry out trap with shallow trench isolation from the nmos device separated and/or PMOS device and inject and form N-type trap and/or P type trap; Make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid; By the silicon dioxide layer of protection that atomic deposition generates, the silicon face of protection device, reduces the loss of surface silicon; Make first grid side wall; Carry out PMOS light dope and inject formation PMOS device leakage light-dope structure; Carry out germanium and silicon epitaxial growth technique; Carry out NMOS light dope and inject formation nmos device leakage light-dope structure.Make second grid side wall, second grid side wall comprises SiO
2layer and SiN layer; Form NMOS source and drain SiC epitaxial region.
Preferably, the step of described formation NMOS source and drain SiC epitaxial region comprises: formed with shallow trench isolation from adjacent U-type silicon groove; Epitaxial growth SiC in U-type silicon groove.
Preferably, manufacture and comprise the steps: to carry out trap with shallow trench isolation from the nmos device separated and/or PMOS device and inject and form N-type trap and/or P type trap; Make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid; By the silicon dioxide layer of protection that atomic deposition generates, the silicon face of protection device, reduces the loss of surface silicon; Make first grid side wall; Carry out PMOS light dope and inject formation PMOS device leakage light-dope structure; Carry out germanium and silicon epitaxial growth technique; Carry out NMOS light dope and inject formation nmos device leakage light-dope structure.Make second grid side wall, second grid side wall comprises SiO
2layer and SiN layer; Form NMOS source and drain SiC epitaxial region.
Preferably, the step of described formation NMOS source and drain SiC epitaxial region comprises: formed with shallow trench isolation from adjacent U-type silicon groove; Epitaxial growth SiC in U-type silicon groove.
Reasonably optimizing shallow groove isolation etching technique of the present invention; make shallow trench isolation digression degree larger; at this moment shallow trench isolation can be protected the silicon below STI edge from silicon dioxide; decrease the loss of shallow trench isolated side wall silicon; the silicon that shallow trench isolated side wall stays can be many; provide " seed " needed for more SiC selective growth, strengthen SiC selective epitaxial growth ability, improve follow-up SiC semiconductor manufacturing process ability.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the difference in height of STI silicon oxide layer and active area silicon face.
Fig. 2 schematically shows the flow chart of the method improving shallow groove isolation edge SiC stress performance according to the preferred embodiment of the invention.
Fig. 3 to Fig. 6 schematically shows each step improving the method for shallow groove isolation edge SiC stress performance according to the present invention according to the preferred embodiment of the invention.
Fig. 7 to Figure 10 schematically shows different shallow trench isolations from the impact of Sidewall angles on the silicon below shallow trench isolated side wall.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 2 schematically shows the flow chart of the method improving shallow groove isolation edge SiC stress performance according to the preferred embodiment of the invention.
Particularly, as shown in Figure 2, the method improving shallow groove isolation edge SiC stress performance according to the preferred embodiment of the invention comprises:
First carry out step S10, formed in silicon substrate 10 shallow trench isolation from.
In silicon substrate 10 formed carry out shallow trench isolation from step S10 specifically can comprise the steps:
First at silicon substrate 10 surface successively deposit bed course silicon dioxide layer 1 and bed course silicon nitride layer 2 (as shown in Figure 3);
Then active area photoetching and etching are carried out to form groove 3 (as shown in Figure 4) in silicon substrate 10 to bed course silicon dioxide layer 1, bed course silicon nitride layer 2 and silicon substrate 10; Wherein, the sidewall of described groove 3 relative to the line angulation vertical with silicon chip surface between 15 degree to 60 between, preferably between 20 degree to 50 degree; Further preferably between 30 degree to 45 degree, such as, can choose 35 degree, 40 degree isogonism angle value.
In groove 3, fill silicon dioxide subsequently and by cmp, planarization carried out to obtain shallow trench isolation from 20 (as shown in Figure 5) to the silicon dioxide of filling; Thus, shallow trench isolated side wall is also in above-mentioned angular range relative to the line angulation (being called for short " shallow trench isolation is from Sidewall angles ") vertical with silicon chip surface.
Then bed course silicon nitride layer 2 (as shown in Figure 6) is peeled off.
Fig. 7 to Figure 10 schematically shows different shallow trench isolations from the impact of Sidewall angles on the silicon below shallow trench isolated side wall.Fig. 7 and Fig. 8 shows the situation of shallow trench isolation from Sidewall angles relatively little (illustrated therein is the situation of minimum " 0 " angle), Fig. 7 and Fig. 8 shows shallow trench isolation from the relatively large situation of Sidewall angles.
When shallow trench isolation is less from Sidewall angles, namely dry etching can along shallow groove isolation edge down etch silicon, and the silicon that shallow trench isolated side wall stays can be fewer, there will be and lowly even lack during shallow groove isolation edge SiC growth.When shallow trench isolation is larger from Sidewall angles; shallow trench isolation can be protected the silicon below STI edge from silicon dioxide; decrease the loss of shallow trench isolated side wall silicon; the silicon that shallow trench isolated side wall stays can be many; provide " seed " needed for more SiC selective growth; strengthen SiC selective epitaxial growth ability, improve follow-up SiC semiconductor manufacturing process ability.But shallow trench isolation is also unfavorable for device layout and the utilization ratio to the silicon that shallow trench isolated side wall stays too greatly from Sidewall angles, and therefore above-mentioned angular range is preferred and favourable.
Like this, follow-uply can to manufacture with shallow trench isolation from the nmos device separated and/or PMOS device, specifically comprise the steps the conventional steps such as S11 to S21.
Then carry out step S11, carry out trap and inject formation N-type trap and/or P type trap.
Then carry out step S12, make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid.
Then continue step S13, the silicon dioxide layer of protection generated by atomic deposition, the silicon face of protection device, reduce the loss of surface silicon.
Then continue step S14, alternatively, perform light dope for input and output device region and inject the leakage light-dope structure forming peripheral input and output device.
Then continue step S15, make first grid side wall; Such as, the material of first grid side wall is SiN; Particularly, the step such as making first grid side wall comprises deposit and the etching of SiN.
Then continue step S16, carry out PMOS light dope and inject formation PMOS device leakage light-dope structure.
Then continue step S17, carry out germanium and silicon epitaxial growth technique.
Then continue step S18, carry out NMOS light dope and inject formation nmos device leakage light-dope structure.
Then continue step S19, make second grid side wall, second grid side wall comprises SiO
2layer and SiN layer; Such as, the formation of second grid side wall comprises deposit and the etching of many SiO2 and SiN.
Then continue step S20, form NMOS source and drain SiC epitaxial region.Wherein, formed with shallow trench isolation from adjacent U-type silicon groove, and in U-type silicon groove epitaxial growth SiC.
Then continue step S21, carry out source and drain and inject formation source-drain electrode.
Then pre-metal dielectric, through hole, metal plug and metal level is made.
Reasonably optimizing shallow groove isolation etching technique of the present invention; make shallow trench isolation digression degree larger; at this moment shallow trench isolation can be protected the silicon below STI edge from silicon dioxide; decrease the loss of shallow trench isolated side wall silicon; the silicon that shallow trench isolated side wall stays can be many; provide " seed " needed for more SiC selective growth, strengthen SiC selective epitaxial growth ability, improve follow-up SiC semiconductor manufacturing process ability.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. improve a method for shallow groove isolation edge SiC stress performance, it is characterized in that comprising: in a silicon substrate formed shallow trench isolation from, and manufacture with shallow trench isolation from the nmos device separated and/or PMOS device;
Wherein, in a silicon substrate formed carry out shallow trench isolation from step comprise the following step performed successively:
At surface of silicon successively deposit bed course silicon dioxide layer and bed course silicon nitride layer;
Active area photoetching and etching are carried out to form groove in a silicon substrate to bed course silicon dioxide layer, bed course silicon nitride layer and silicon substrate; Wherein, described groove sidewall relative to the line angulation vertical with silicon chip surface between 15 degree to 60 between;
Fill silicon dioxide in a groove and by cmp, planarization carried out to obtain shallow trench isolating main bodies to the silicon dioxide of filling;
Peel off bed course silicon nitride layer, and peel off bed course silicon dioxide layer.
2. the method improving shallow groove isolation edge SiC stress performance according to claim 1, is characterized in that, the sidewall of described groove relative to the line angulation vertical with silicon chip surface between 20 degree to 50 degree.
3. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, the sidewall of described groove relative to the line angulation vertical with silicon chip surface between 30 degree to 45 degree.
4. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, the sidewall of described groove is 35 degree relative to the line angulation vertical with silicon chip surface.
5. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, the sidewall of described groove is 40 degree relative to the line angulation vertical with silicon chip surface.
6. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, manufactures and comprises the steps: from the nmos device separated and/or PMOS device with shallow trench isolation
Carry out trap and inject formation N-type trap and/or P type trap;
Make grid oxic horizon, perform the deposit of gate polycrystalline silicon materials, and the photoetching carrying out grid polycrystalline silicon forms grid;
By the silicon dioxide layer of protection that atomic deposition generates, the silicon face of protection device, reduces the loss of surface silicon;
Make first grid side wall;
Carry out PMOS light dope and inject formation PMOS device leakage light-dope structure;
Carry out germanium and silicon epitaxial growth technique;
Carry out NMOS light dope and inject formation nmos device leakage light-dope structure.
Make second grid side wall, second grid side wall comprises SiO
2layer and SiN layer;
Form NMOS source and drain SiC epitaxial region.
7. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, the step of described formation NMOS source and drain SiC epitaxial region comprises:
Formed with shallow trench isolation from adjacent U-type silicon groove;
Epitaxial growth SiC in U-type silicon groove.
8. the method improving shallow groove isolation edge SiC stress performance according to claim 1 and 2, is characterized in that, described method is for the manufacture of cmos device.
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| CN201410664627.7A CN104392955A (en) | 2014-11-19 | 2014-11-19 | Method for improving SiC stress property of shallow trench isolation edge |
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| JP2009177063A (en) * | 2008-01-28 | 2009-08-06 | Toshiba Corp | Method for manufacturing semiconductor device and semiconductor device |
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| CN102522364A (en) * | 2011-12-22 | 2012-06-27 | 上海宏力半导体制造有限公司 | Shallow-groove partition structure and forming method thereof |
| CN103295953A (en) * | 2013-05-28 | 2013-09-11 | 上海宏力半导体制造有限公司 | Formation method of semiconductor device |
| CN103779223A (en) * | 2012-10-23 | 2014-05-07 | 中国科学院微电子研究所 | Manufacturing method of mosfet |
-
2014
- 2014-11-19 CN CN201410664627.7A patent/CN104392955A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070066074A1 (en) * | 2005-09-19 | 2007-03-22 | Nace Rossi | Shallow trench isolation structures and a method for forming shallow trench isolation structures |
| CN101207063A (en) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation |
| JP2009177063A (en) * | 2008-01-28 | 2009-08-06 | Toshiba Corp | Method for manufacturing semiconductor device and semiconductor device |
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Application publication date: 20150304 |