CN104409409A - Method for improving SiC stress property of shallow trench isolation edge - Google Patents

Method for improving SiC stress property of shallow trench isolation edge Download PDF

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CN104409409A
CN104409409A CN 201410664583 CN201410664583A CN104409409A CN 104409409 A CN104409409 A CN 104409409A CN 201410664583 CN201410664583 CN 201410664583 CN 201410664583 A CN201410664583 A CN 201410664583A CN 104409409 A CN104409409 A CN 104409409A
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trench isolation
shallow trench
silicon
layer
sic
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CN 201410664583
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周建华
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上海华力微电子有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not

Abstract

The invention provides a method for improving SiC stress property of a shallow trench isolation edge. The step of forming a shallow trench isolation in a silicon substrate comprises the steps: depositing a silicon dioxide cushion layer with a first thickness and a silicon nitride cushion layer with a second thickness on the surface of the silicon substrate in sequence; secondly, with respect to the utilized photoetching process, choosing the first thickness of the silicon dioxide cushion layer to adjust the height of the shallow trench isolation to be formed, wherein the first thickness of the silicon dioxide cushion layer is chosen to satisfy the photoetching requirement; thirdly, actively photoetching and etching the silicon dioxide cushion layer, the silicon nitride cushion layer and the silicon substrate so as to form a groove in the silicon substrate; fourthly, filling silicon dioxide in the groove and flattening the filled silicon dioxide through chemical and mechanical grinding to form shallow trench isolation; and finally, peeling off the silicon nitride cushion layer.

Description

改善浅沟槽隔离边缘SiC应力性能的方法 Shallow trench isolation method of improving edge performance SiC stress

技术领域 FIELD

[0001] 本发明涉及半导体制造领域,更具体地说,本发明涉及一种通过垫层氮化硅层工艺的优化来改善浅沟槽隔离边缘SiC应力性能的方法。 [0001] The present invention relates to the field of semiconductor manufacturing, and more particularly, the present invention relates to a method of optimizing the process underlaying silicon nitride layer to improve the edge of shallow trench isolation performance SiC by stress.

背景技术 Background technique

[0002] 随着超大规模集成电路技术的迅速发展,MOSFET器件的尺寸在不断减小,通常包括MOSFET器件沟道长度的减小,栅氧化层厚度的减薄等以获得更快的器件速度。 [0002] With the rapid development of VLSI technology, the size of the MOSFET devices continues to decrease, typically includes reducing the MOSFET device channel length, gate oxide thickness is thinned, and the like to obtain a faster device speed. 但是随着超大规模集成电路技术发展至超深亚微米级时,特别是90纳米及以下技术节点时,减小沟道长度会带来一系列问题,为了控制短沟道效应,会在沟道中掺以较高浓度的杂质,这会降低载流子的迁移率,从而导致器件性能下降,单纯的器件尺寸减小很难满足大规模集成电路技术的发展。 However, with the development of VLSI technology to when the ultra-deep sub-micron, especially 90 nm technology node and below, reducing the channel length will bring a series of problems, in order to control the short channel effect, the channel will doped with impurities in higher concentration, which may reduce the mobility of carriers, resulting in decreased device performance, device size reduction alone is difficult to meet the development of large scale integrated circuit technology. 因此,应力工程的广泛研究用来提高载流子的迁移率,从而达到更快的器件速度,并满足摩尔定律的规律。 Therefore, extensive studies of stress engineering to increase the mobility of carriers, so as to achieve a faster device speed, and Moore's law is satisfied.

[0003] 上世纪80年代到90年代,学术界就已经开始基于硅基衬底实现异质结构研究,直到本世纪初才实现商业应用。 [0003] In the 1980s and 1990s, academics have begun research on a silicon substrate-based heterostructures to achieve, until the beginning of this century to achieve commercial application. 其中有两种代表性的应力应用,一种是双轴应力技术(Biaxial Technique);另一种是单轴应力技术(Uniaxial Technique),即应力记忆技术(Stress Memorizat1n Technology)、nCESL及选择性(或嵌入)外延生长娃碳SiC漏源(参见文献“KWAng et al., IEDM Tech.Dig.,pp.1069,2004” 以及文献“YCLiu etal.,VLSI, pp.44-45,2007”)对NM0SFET的沟道施加张应力提高电子的迁移率,选择性(或嵌入)外延生长锗硅SiGe、pCESL对PM0SFET沟道施加压应力提高空穴的迁移率,从而提高器件的性能,见图2。 Wherein there are two typical stress applications a biaxial stress techniques (Biaxial Technique); the other is a uniaxial stress techniques (Uniaxial Technique), i.e. stress memorization technique (Stress Memorizat1n Technology), nCESL and optionally ( or embedded) epitaxial growth of SiC drain baby carbon source (see reference "KWAng et al., IEDM Tech.Dig., pp.1069,2004" and Document "YCLiu etal., VLSI, pp.44-45,2007") to NM0SFET tensile stress is applied to improve the channel mobility of electrons, selectively (or embedded) epitaxially grown silicon germanium SiGe, pCESL compression stress is applied to increase the mobility of holes PM0SFET the channel, thereby improving the performance of the device, shown in Figure 2.

[0004]目前,对于SiC外延生长工艺的研究主要集中于如何提高SiC中碳的浓度,碳的浓度越高,晶格失配越大,产生的应力越大,对载流子迁移率的提高越显著;另外,SiC的形状,SiC漏源接近多晶硅的边缘,即靠近器件沟道,应力越直接作用于器件沟道的载流子,对器件性能的提升明显。 [0004] At present, the SiC epitaxial growth process research has focused on ways to increase the concentration of carbon in SiC, the higher the concentration of carbon, the lattice mismatch, the greater the stress, improvement of the carrier mobility of the stream more significant; Further, SiC shape, SiC polycrystalline silicon near the edge of the drain-source, i.e., close to the device channel, the stress acting directly on the carrier device channel, significantly improve device performance.

[0005] 以上所有的研究开发都是基于硅衬底,也就是说,硅衬底提供SiC生长的种子,SiC沿着硅的晶格进行外延生长,但是,半导体工艺中,器件之间通过浅沟槽隔离工艺(STI)实现电学隔离,STI中使用二氧化硅进行填充,因此在STI与有源区边缘,SiC外延工艺会受到STI的影响,STI不能够提供足够的硅“种子”,就会出现SiC选择性外延工艺中的左右两侧STI边缘SiC生长低落甚至缺失。 [0005] All of the above research and development are based on the silicon substrate, i.e., a silicon substrate seed grown SiC, SiC epitaxial growth along the silicon crystal lattice, but the semiconductor process, between the device by a shallow trench isolation process (STI) to achieve electrical isolation, STI using silica filled, thus at the edge of the active region STI, SiC epitaxial process affected the STI, the STI silicon can not provide sufficient "seed", to the left and right edges of STI occur SiC SiC selective epitaxial growth process, low or absent.

发明内容 SUMMARY

[0006] 本发明所要解决的技术问题是针对现有技术中存在上述缺陷,提供一种能够通过垫层氮化硅层工艺的优化来改善浅沟槽隔离边缘SiC应力性能的方法。 [0006] The present invention solves the technical problem is directed to a method capable of improving the edge of shallow trench isolation stresses SiC cushion performance by optimizing the process of the presence of the silicon nitride layer disadvantages of the prior art, provided.

[0007] 为了实现上述技术目的,根据本发明,提供了一种改善浅沟槽隔离边缘SiC应力性能的方法,包括:在硅衬底中形成进行浅沟槽隔离;进行阱注入形成N型阱和/或P型阱;制作栅极氧化层,执行栅极多晶硅材料的淀积,并进行栅极多晶硅的光刻形成栅极;通过原子淀积生成的二氧化硅保护层;制作第一栅极侧墙;进行PMOS轻掺杂注入形成PMOS器件漏轻掺杂结构;进行锗娃外延生长工艺;进行NMOS轻掺杂注入形成NMOS器件漏轻掺杂结构;制作第二栅极侧墙,第二栅极侧墙包括Si02层和SiN层;形成NMOS源漏SiC外延区。 [0007] To achieve the above technical object, according to the present invention, there is provided a method of improving the edge of shallow trench isolation stress performance SiC, comprising: forming shallow trench isolation in a silicon substrate; well implantation for the N-type well and / or P-type well; prepared gate oxide layer, gate polysilicon material is deposited performed, photolithography and gate polysilicon gate is formed; atomic layer deposition silicon dioxide protective generated; forming a first gate electrode sidewalls; PMOS lightly doped implanted for forming lightly doped drain PMOS device structure; for baby germanium epitaxial growth process; for NMOS lightly doped implanted lightly doped drain NMOS devices formed structure; forming a second gate spacer, the first The gate sidewall spacer comprises two Si02 layer and a SiN layer; forming source and drain NMOS SiC epitaxial region.

[0008] 优选地,在硅衬底中形成进行浅沟槽隔离的步骤包括:在硅衬底表面依次淀积第一厚度的垫层二氧化硅层和第二厚度的垫层氮化硅层;其中,针对使用的光刻工艺,选择垫层二氧化硅层的第一厚度来调节将要形成的浅沟槽隔离的高度,并且选择垫层二氧化硅层的第一厚度以满足光刻条件;然后对垫层二氧化硅层、垫层氮化硅层和硅衬底进行有源区光刻和刻蚀以便在硅衬底中形成凹槽;随后在凹槽中填充二氧化硅并通过化学机械研磨对填充的二氧化硅进行平坦化处理以得到浅沟槽隔离;然后剥离垫层氮化硅层。 Step [0008] Preferably, the silicon substrate formed in a shallow trench isolation comprises: sequentially depositing the silicon nitride layer, cushion layer, a first silicon dioxide pad layer thickness and a second thickness at the surface of the silicon substrate ; wherein the lithography process used for selecting a first silicon dioxide layer thickness of the cushion layer is adjusted to be a shallow trench isolation formed height, the thickness of the cushion layer and the first silicon dioxide layer selected to satisfy the condition lithography ; then cushion silicon dioxide layer, a silicon nitride layer and the underlayer silicon substrate active region lithography and etching to form recesses in a silicon substrate; subsequently the silica filler in the recess by chemical mechanical polishing of silica filler to obtain a planarized shallow trench isolation; cushion silicon nitride layer is then stripped.

[0009] 优选地,垫层氮化硅层的第二厚度被选择为满足光刻条件的最大厚度,由此使得浅沟槽隔离的高度最大化。 [0009] Preferably, the thickness of the second silicon nitride layer mat is chosen to meet the maximum thickness of lithography conditions, thereby maximizing the height of such shallow trench isolation.

[0010] 优选地,在硅衬底中形成进行浅沟槽隔离的步骤使得浅沟槽隔离的上表面高于硅片衬底的上表面。 Step [0010] Preferably, the silicon substrate formed in shallow trench isolation such as shallow trench isolation higher than the upper surface of the upper surface of the silicon substrate.

[0011] 优选地,在硅衬底中形成进行浅沟槽隔离的步骤使得浅沟槽隔离的上表面不低于娃片衬底的上表面。 Step [0011] Preferably, the silicon substrate formed in shallow trench isolation such as shallow trench isolation is not lower than the upper surface of the substrate sheet on the surface of the doll.

[0012] 优选地,形成NMOS源漏SiC外延区的步骤包括:首先淀积作为SiC生长阻挡层的氮化硅层,利用氮化硅层进行光刻以定义SiC区域,接着针对SiC区域进行嵌壁硅干法刻蚀以形成U-型硅凹槽。 First depositing a silicon nitride layer grown SiC as a barrier layer, a silicon nitride layer using photolithography to define SiC region, followed by SiC region for the insert: [0012] Preferably, the step of NMOS source drain regions comprises forming the SiC epitaxial wall silicon dry etching to form silicon U- recess.

[0013] 本发明合理优化垫层垫层氮化硅层的厚度,从而控制浅沟槽隔离氧化硅层表面到有源区硅表面的厚度,使得能够既不影响光刻,又同时获得合理的浅沟槽隔离的高度,控制后续SiC工艺中嵌壁硅刻蚀工艺对浅沟槽隔离侧壁硅的损耗情况,增强了SiC外延生长能力,提高SiC半导体工艺制程能力。 [0013] The present invention is optimizing the thickness is reasonable cushion cushion silicon nitride layer, thereby controlling the surface of a shallow trench isolation silicon oxide layer to the thickness of the silicon surface of the active region, making it possible to not affect the lithography, and while obtaining reasonable STI height control subsequent processes SiC silicon recessed shallow trench isolation etching process where the side wall silicon loss, enhancing the ability to grow epitaxial SiC, the SiC semiconductor process technology to improve the capacity.

附图说明 BRIEF DESCRIPTION

[0014] 结合附图,并通过参考下面的详细描述,将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征,其中: [0014] conjunction with the accompanying drawings, and by reference to the following detailed description, it will be more readily with a more complete understanding of the present invention more readily understood, and its attendant advantages and features, wherein:

[0015] 图1示意性地示出了STI氧化硅层与有源区硅表面的高度差。 [0015] Figure 1 schematically shows a height STI silicon oxide layer and the silicon surface of the active zone differences.

[0016] 图2示意性地示出了根据本发明优选实施例的改善浅沟槽隔离边缘SiC应力性能的方法的流程图。 [0016] FIG. 2 schematically illustrates a flowchart of a method embodiment of the improved shallow trench isolation edge stress performance SiC according to a preferred embodiment of the present invention.

[0017] 图3至图6示意性地示出了根据本发明根据本发明优选实施例的改善浅沟槽隔离边缘SiC应力性能的方法的各个步骤。 [0017] FIGS. 3 to 6 schematically illustrate various steps of a method for improving the edge of the STI embodiment of SiC stress properties of the present invention according to a preferred embodiment of the present invention.

[0018] 图7至图10示意性地示出了不同厚度的垫层氮化硅层得到的不同器件结构。 [0018] Figures 7 to 10 schematically show different device structure cushion the silicon nitride layers of different thicknesses obtained.

[0019] 需要说明的是,附图用于说明本发明,而非限制本发明。 [0019] Incidentally, the drawings used to illustrate the present invention, not to limit the present invention. 注意,表示结构的附图可能并非按比例绘制。 Note that illustrates the configuration may not drawn to scale. 并且,附图中,相同或者类似的元件标有相同或者类似的标号。 Further, in the drawings, the same or similar elements are labeled with the same or similar reference numerals.

具体实施方式 detailed description

[0020] 为了使本发明的内容更加清楚和易懂,下面结合具体实施例和附图对本发明的内容进行详细描述。 [0020] In order to make the present invention clearer and more understandable, the following examples and in conjunction with the accompanying drawings of the present invention will be described in detail with embodiments.

[0021] 通过研究,发明人有利地发现,左右两侧STI边缘SiGe生长低落甚至缺失的原因是由于浅沟槽隔离(STI)氧化硅层到有源区硅表面的高度差造成的,当STI高度低于器件有源区硅AA表面时,在进行嵌壁硅刻蚀工艺时,STI表面以上的硅都被刻蚀掉,不能给后续的SiC生长提供硅“种子”,造成如左右两侧STI边缘SiC生长低落甚至缺失。 [0021] Through the research, the inventors have advantageously found that the reason the left and right edges of STI SiGe growth is due to low or absent shallow trench isolation (STI) layer of silicon oxide to the silicon surface height difference caused by the active region, when STI when the height is lower than the silicon surface of the device active region AA, recessed during silicon etching process, above the STI surface of the silicon are etched away, it can not give the subsequent growth provides SiC silicon "seed", causing the left and right sides as STI edges of SiC growth is low or absent. 因此,如图1所示,STI氧化硅层20与有源区10硅表面的高度差12,以及STI边缘硅(如图1的虚线所示)的多少,对SiC工艺至关重要。 Thus, how much 12, and the edge of the silicon STI silicon surface height difference 10 STI silicon oxide layer 20 and the active region (shown in dashed lines in FIG. 1) shown in Figure 1, the process is critical to SiC.

[0022] 本发明中,通过优化垫层二氧化硅层,控制STI氧化硅层到有源区硅表面的厚度,从而控制SiC工艺中嵌壁硅刻蚀工艺(Si Recess Etch,也称为硅凹槽刻蚀)对浅沟槽隔离侧壁硅的损耗,增强SiC选择性外延生长能力,提高SiC半导体工艺制程能力。 [0022] In the present invention, by optimizing the cushion silicon dioxide layer, a silicon oxide layer to control the thickness of the STI silicon surface of the active region, whereby the SiC process recessed silicon etching process (Si Recess Etch, also known as silicon recess etching) the silicon sidewall isolation loss shallow trench, selective epitaxial growth enhancing capabilities SiC, the SiC semiconductor process technology to improve the capacity.

[0023] 图2示意性地示出了根据本发明优选实施例的改善浅沟槽隔离边缘SiC应力性能的方法的流程图。 [0023] FIG. 2 schematically illustrates a flowchart of a method embodiment of the improved shallow trench isolation edge stress performance SiC according to a preferred embodiment of the present invention.

[0024] 具体地,如图2所示,根据本发明优选实施例的改善浅沟槽隔离边缘SiC应力性能的方法包括: [0024] Specifically, as shown in FIG SiC edge stress isolation performance improvement according to a preferred embodiment of the shallow trench method of the present invention comprises:

[0025] 首先进行步骤S10,在硅衬底10中形成进行浅沟槽隔离20。 [0025] firstly step S10, the silicon substrate 10 is formed in the shallow trench isolation 20.

[0026] 步骤SlO具体可包括下述步骤: [0026] Step SlO may specifically include the following steps:

[0027] 首先在硅衬底10表面依次淀积第一厚度的垫层二氧化硅层I和第二厚度的垫层氮化硅层2(如图3所示);其中,针对使用的光刻工艺,选择垫层二氧化硅层I的第一厚度来调节将要形成的浅沟槽隔离的高度,并且选择垫层二氧化硅层I的第一厚度以满足光刻条件;例如,优选地,垫层氮化硅层2的第二厚度被选择为满足光刻条件的最大厚度(由此能够得到当前情况下的最大的浅沟槽隔离的高度); Cushion Cushion silicon nitride layer and a second silicon dioxide layer thickness of I [0027] 10 first surface of the silicon substrate 2 sequentially depositing a first thickness (shown in Figure 3); wherein the light used for the etching process, selecting a first silicon dioxide layer thickness of the cushion I is adjusted to be a shallow trench isolation formed height, and selecting a first silicon dioxide layer thickness of the cushion I to satisfy the condition photolithography; for example, preferably the second silicon nitride layer thickness of the cushion 2 is selected to satisfy the maximum thickness of the lithography conditions (the maximum can be obtained in the present case the shallow trench isolation height);

[0028] 然后对垫层二氧化硅层1、垫层氮化硅层2和硅衬底10进行有源区光刻和刻蚀以便在硅衬底10中形成凹槽3 (如图4所示); [0028] The silicon dioxide layer 1 and then the cushion, the cushion layer 2 of silicon nitride and the silicon substrate 10 of the active region lithography and etching to form recesses in the silicon substrate 103 (FIG. 4 shown);

[0029] 随后在凹槽3中填充二氧化硅并通过化学机械研磨对填充的二氧化硅进行平坦化处理以得到浅沟槽隔离20(如图5所示); [0029] and subsequently planarized silicon dioxide is filled in the recess 3 by a chemical mechanical polishing to obtain a silica-filled shallow trench isolation 20 (Figure 5);

[0030] 然后剥离垫层氮化硅层2 (如图6所示)。 [0030] The silicon nitride layer is then stripped cushion 2 (shown in FIG. 6).

[0031] 如图7至图10所示,较厚的垫层氮化硅层2会得到较高的STI氧化层的高度。 [0031] As shown in FIG. 7 to FIG. 10, the silicon nitride layer 2 thick cushion will be higher height STI oxide layer. 图7和图8示出了垫层氮化硅层2厚度相对较小时STI氧化层的高度(如图8中的双箭头所示),图9和图10示出了垫层氮化硅层2厚度相对较大时STI氧化层的高度(如图8中的双箭头所示)。 Figures 7 and 8 illustrate the height STI oxide layer thickness of the cushion when the silicon nitride layer 2 is relatively small (FIG. 8 double arrows), FIG. 9 and FIG. 10 shows a cushion layer of silicon nitride STI height is relatively large thickness of the oxide layer 2 (indicated by the double arrow in FIG. 8).

[0032] 优选地,在硅衬底10中形成进行浅沟槽隔离20的步骤使得浅沟槽隔离20的上表面高于娃片衬底的上表面。 [0032] Preferably, the silicon substrate 10 is formed in the shallow trench isolation step 20 so that the upper surface of the shallow trench isolation 20 is higher than the upper surface of the substrate sheet baby.

[0033] 接着进行步骤SI I,进行阱注入形成N型阱和/或P型阱。 [0033] Next step SI I, well implantation for forming N-well and / or P-type well.

[0034] 接着进行步骤S12,制作栅极氧化层,执行栅极多晶硅材料的淀积,并进行栅极多晶娃的光刻形成栅极。 [0034] followed by step S12, making the gate oxide layer, gate polysilicon material is deposited performed, and the gate polycrystalline baby photolithography to form the gate.

[0035] 接着继续步骤S13,通过原子淀积生成的二氧化硅保护层,保护器件的硅表面,减少表面娃的损失。 [0035] Next continue step S13, the atomic layer deposition silicon dioxide protective generated, the silicon surface protection device to reduce the loss of surface Wa.

[0036] 接着继续步骤S14,可选地,针对输入输出器件区域执行轻掺杂注入形成外围的输入输出器件的漏轻掺杂结构。 [0036] Next continue step S14, alternatively, for the input-output device performs the lightly doped implanted regions forming the input and output of the peripheral device is a lightly doped drain structure.

[0037] 接着继续步骤S15,制作第一栅极侧墙;例如,第一栅极侧墙的材料是SiN ;具体地,例如制作第一栅极侧墙的步骤包括SiN的淀积和刻蚀。 [0037] Next continue step S15, producing the first gate spacer; e.g., a first gate spacer material is SiN; specifically, for example, a first step of forming a gate sidewall spacer comprises depositing and etching of SiN .

[0038] 接着继续步骤S16,进行PMOS轻掺杂注入形成PMOS器件漏轻掺杂结构。 [0038] Next continues with step S16, a PMOS lightly doped drain PMOS device formed by implanting lightly doped structure.

[0039] 接着继续步骤S17,进行锗硅外延生长工艺。 [0039] Next continue step S17, the process for epitaxial growth of silicon germanium.

[0040] 接着继续步骤S18,进行NMOS轻掺杂注入形成NMOS器件漏轻掺杂结构。 [0040] Next continue step S18, for NMOS lightly doped implanted lightly doped drain NMOS devices formed structure.

[0041] 接着继续步骤S19,制作第二栅极侧墙,第二栅极侧墙包括S12层和SiN层;例如,第二栅极侧墙的形成包括多Si02和SiN的淀积和刻蚀。 [0041] Next continue step S19, making the second gate spacer, the second spacer comprising a gate layer and a SiN layer S12; e.g., the second gate spacer is formed comprising a plurality of Si02 and SiN deposition and etching .

[0042] 接着继续步骤S20,形成NMOS源漏SiC外延区。 [0042] Next continue step S20, the NMOS source and drain forming SiC epitaxial region. 其中,首先淀积作为SiC生长阻挡层的氮化硅层,利用氮化硅层进行光刻以定义SiC区域,接着针对SiC区域进行嵌壁硅干法刻蚀以形成U-型硅凹槽。 Wherein the first deposited silicon nitride layer grown SiC as a barrier layer, a silicon nitride layer using photolithography to define SiC region, followed by dry etching recessed silicon region to form a U- SiC for silicon grooves.

[0043] 当STI上表面低于有源区硅表面时,高于STI上表面的所有硅都将被刻蚀,SiC会在STI边缘SiC生长低落甚至缺失。 [0043] When the surface is below the surface of the silicon active region STI, the STI above all the silicon surfaces are to be etched, SiC will grow low or absent in the STI edge SiC. 当STI上表面高于有源区硅表面时,STI氧化层会对其边缘侧壁的硅进行保护,如图1虚线圈出的范围,减少了STI侧壁硅的损耗,增强SiC外延生长能力,提高SiC半导体工艺制程能力。 When the surface of the STI above the upper surface of the active silicon region, STI silicon oxide layer may be an edge of its side wall protection range dotted circle shown in FIG. 1, reducing the loss of the STI sidewalls of the silicon, to enhance the ability to grow epitaxial SiC , SiC semiconductor process technology to improve the capacity.

[0044] 接着继续步骤S21,进行源漏注入形成源漏极。 [0044] Next continue step S21, the source and drain implantation for forming source and drain.

[0045] 接着制作金属前介质、通孔、金属插塞和金属层。 [0045] The medium is then made before the metal, vias, metal plugs and a metal layer.

[0046] 本发明合理优化垫层垫层氮化硅层的厚度,从而控制浅沟槽隔离氧化硅层表面到有源区硅表面的厚度,使得能够既不影响光刻,又同时获得合理的浅沟槽隔离的高度,控制后续SiC工艺中嵌壁硅刻蚀工艺对浅沟槽隔离侧壁硅的损耗情况,增强了SiC外延生长能力,提高SiC半导体工艺制程能力。 [0046] The present invention is optimizing the thickness is reasonable cushion cushion silicon nitride layer, thereby controlling the surface of a shallow trench isolation silicon oxide layer to the thickness of the silicon surface of the active region, making it possible to not affect the lithography, and while obtaining reasonable STI height control subsequent processes SiC silicon recessed shallow trench isolation etching process where the side wall silicon loss, enhancing the ability to grow epitaxial SiC, the SiC semiconductor process technology to improve the capacity.

[0047] 可以理解的是,虽然本发明已以较佳实施例披露如上,然而上述实施例并非用以限定本发明。 [0047] It will be appreciated that although the present invention has been disclosed as the preferred embodiment, however, the above-described embodiments are not intended to limit the present invention. 对于任何熟悉本领域的技术人员而言,在不脱离本发明技术方案范围情况下,都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。 For any skilled in the art, without departing from the scope of the technical solution of the present invention, can take advantage of the above-described technical contents disclosed that many possible variations and modifications of the technical solution of the present invention, as equivalent variations or modifications equivalent Example. 因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。 Thus, all without departing from the technical solutions of the present invention, any simple modification based on the technical essence of the present invention made of the above Example, equivalents, modifications and variations, provided they fall within the scope of protection of the present invention.

Claims (8)

  1. 1.一种改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于包括: 在硅衬底中形成进行浅沟槽隔离; 进行阱注入形成N型阱和/或P型阱; 制作栅极氧化层,执行栅极多晶硅材料的淀积,并进行栅极多晶硅的光刻形成栅极; 通过原子淀积生成的二氧化硅保护层。 A shallow trench isolation method for improving edge performance SiC stress, comprising: forming shallow trench isolation in a silicon substrate; well implantation for forming the N-type well and / or P-type well; gate production oxide layer, gate polysilicon material is deposited performed, photolithography and gate polysilicon gate is formed; atomic layer deposition silicon dioxide protective generated.
  2. 2.根据权利要求1所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于还包括: 制作第一栅极侧墙; 进行PMOS轻掺杂注入形成PMOS器件漏轻掺杂结构; 进行锗硅外延生长工艺; 进行NMOS轻掺杂注入形成NMOS器件漏轻掺杂结构; 制作第二栅极侧墙,第二栅极侧墙包括Si02层和SiN层; 形成NMOS源漏SiC外延区。 The shallow trench isolation method for improving edge performance SiC stress according to claim 1, characterized by further comprising: forming a first gate spacer; PMOS lightly doped implanted for forming lightly doped drain PMOS device structure; for SiGe epitaxial growth process; for NMOS lightly doped implanted lightly doped drain NMOS devices formed structure; forming a second gate spacer, the second gate spacer layer comprises Si02 and SiN layer; forming source and drain NMOS SiC epitaxial region .
  3. 3.根据权利要求1或2所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于,在硅衬底中形成进行浅沟槽隔离的步骤包括: 在硅衬底表面依次淀积第一厚度的垫层二氧化硅层和第二厚度的垫层氮化硅层;其中,针对使用的光刻工艺,选择垫层二氧化硅层的第一厚度来调节将要形成的浅沟槽隔离的高度,并且选择垫层二氧化硅层的第一厚度以满足光刻条件; 然后对垫层二氧化娃层、垫层氮化娃层和娃衬底进行有源区光刻和刻蚀以便在娃衬底中形成凹槽; 随后在凹槽中填充二氧化硅并通过化学机械研磨对填充的二氧化硅进行平坦化处理以得到浅沟槽隔离; 然后剥离垫层氮化硅层。 3. The improvement of claim 12 or method of shallow trench isolation edge stress performance SiC claim, wherein the step of forming shallow trench isolation in the silicon substrate comprises: sequentially depositing the silicon substrate surface wherein shallow trenches, the lithographic process used for selecting a first silicon dioxide layer thickness of the cushion layer is adjusted to be formed; cushion pad layer a silicon nitride layer and a silicon dioxide layer having a first thickness to a second thickness isolated height, the thickness of the cushion layer and the first silicon dioxide layer selected to satisfy the condition photolithography; then dioxide baby cushion layer, the cushion layer and a baby doll nitride substrate for lithography and etching the active region baby substrate so as to form a recess; subsequently the silica filler in the groove and planarized filling silica by chemical mechanical polishing to obtain a shallow trench isolation; cushion silicon nitride layer is then stripped.
  4. 4.根据权利要求3所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于,垫层氮化硅层的第二厚度被选择为满足光刻条件的最大厚度,由此使得浅沟槽隔离的高度最大化。 The method of shallow trench isolation SiC edge stress improved performance according to claim 3, characterized in that the thickness of the second silicon nitride layer cushion is selected to satisfy the maximum thickness of the lithography conditions, thereby making a shallow height maximize trench isolation.
  5. 5.根据权利要求1或2所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于,在硅衬底中形成进行浅沟槽隔离的步骤使得浅沟槽隔离的上表面高于硅片衬底的上表面。 5. The improvement of claim 12 or method of shallow trench isolation edge stress performance SiC claim, wherein the step of forming shallow trench isolation in the silicon substrate such that the upper surface of the STI above the upper surface of the silicon substrate.
  6. 6.根据权利要求1或2所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于,在硅衬底中形成进行浅沟槽隔离的步骤使得浅沟槽隔离的上表面不低于硅片衬底的上表面。 6. The improvement of claim 12 or method of shallow trench isolation edge stress performance SiC claim, wherein the step of forming shallow trench isolation in the silicon substrate such that the upper surface of the shallow trench isolation is not low the upper surface of the silicon substrate.
  7. 7.根据权利要求1或2所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于,形成NMOS源漏SiC外延区的步骤包括:首先淀积作为SiC生长阻挡层的氮化硅层,利用氮化硅层进行光刻以定义SiC区域,接着针对SiC区域进行嵌壁硅干法刻蚀以形成U-型硅凹槽。 7. The improvement of claim 12 or method of shallow trench isolation edge stress performance SiC claim, wherein the step of NMOS source drain regions comprises forming the SiC epitaxial: first deposited silicon nitride as a barrier layer grown SiC layer, a silicon nitride layer using photolithography to define SiC region, followed by dry etching recessed silicon region to form a U- SiC for silicon grooves.
  8. 8.根据权利要求1或2所述的改善浅沟槽隔离边缘SiC应力性能的方法,其特征在于,所述方法用于制造MOS晶体管。 The shallow trench isolation method for improving edge performance SiC stress claim 1 or claim 2, characterized in that the method for manufacturing a MOS transistor.
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