CN104392956A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN104392956A CN104392956A CN201410693479.1A CN201410693479A CN104392956A CN 104392956 A CN104392956 A CN 104392956A CN 201410693479 A CN201410693479 A CN 201410693479A CN 104392956 A CN104392956 A CN 104392956A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
Abstract
The invention discloses a semiconductor device manufacturing method. The semiconductor device manufacturing method comprises providing a substrate and depositing a mat oxygen layer and a silicon nitride layer on the substrate in turn; performing the shallow trench isolation process on the substrate so as to form a shallow isolation trench; depositing a mat oxygen layer and a silicon nitride layer in an substrate area except the shallow isolation trench in turn, wherein the area; performing the silicon nitride pull-back process; performing the mat oxygen layer deposition on the surface of the shallow isolation trench; performing the silicon oxide filling on the shallow isolation trench; manufacturing a CMOS (Complementary Metal Oxide Semiconductor) device in an active area of the substrate. According to the semiconductor device manufacturing method, the silicon nitride pull-back process is added and accordingly a certain thickness of silicon nitride is etched horizontally, the top width of STI (Shallow Trench Isolation) is increased, and accordingly the loss of the recessed silicon etching process in the subsequent silicon carbide selective epitaxial growth process on the silicon of the shallow trench isolation side wall can be controlled, the epitaxial growth capability of the silicon carbide is enhanced, and the silicon carbide semiconductor technology process capability is improved.
Description
Technical field
The present invention relates to IC manufacturing field, particularly a kind of method, semi-conductor device manufacturing method.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element, in continuous reduction, comprises the reduction of MOSFET element channel length, gate oxide thickness thinning etc., to obtain speed faster.But along with the development of very large scale integration technology, to sub-micro level particularly 90 nanometers and following technology node time, reduce channel length can bring series of problems.In order to control short-channel effect, can mix the impurity with higher concentration in channels, this can reduce the mobility of charge carrier, thus causes device performance to decline.That is, simple device size reduces to be difficult to the development meeting large scale integrated circuit technology.Therefore, how stress engineering improves the mobility of charge carrier in extensive research, reaches device speed faster, and meets the rule of Moore's Law.
The eighties in last century, academia just started to realize heterostructure research based on silicon-based substrate, until just realize business application the beginning of this century to the nineties.Wherein have two kinds of representational stress application, one is biaxial stress technology (Biaxial Technique); Another kind is simple stress technology (Uniaxial Technique).Namely, adopt SMT (stress memory technique, Stress Memorization Technology), nCESL (contact hole etching stop layer, Contact Etch Stop Layer) and the mode such as selectivity (or embedded) epitaxial growth carborundum (SiC), the mobility that tensile stress improves electronics is applied to the raceway groove of NMOSFET; Adopt selectivity (or embedded) epitaxial growth Ge-Si (SiGe), pCESL to apply compression to improve the mobility in hole to PMOSFET raceway groove, thus improve the performance of device.
At present, the research for silicon carbide epitaxial growth technique mainly concentrates on the concentration how improving carbon in carborundum, and the concentration of carbon is higher, and lattice mismatch is larger, and the stress of generation is larger, more remarkable to the raising of carrier mobility.In addition, carborundum more close to the edge of polysilicon namely the closer to device channel, stress more directly acts on the charge carrier of device channel, obvious to the lifting of device performance.
Research and development all are above all based on silicon substrate, and that is, silicon substrate provides the seed of growth of silicon carbide, and SiC carries out epitaxial growth along the lattice of silicon.But, as shown in Figure 1, in semiconductor technology, realize electric isolation by STI between device, in STI, use silicon dioxide to fill, and when STI edge sidewall is when carrying out wall embeded silicon etching process, the silicon of STI sidewall can be etched away, specifically as shown in part A in Fig. 2, the STI edge of part A provide silicon " seed " can not to follow-up SiC growth, causes STI edge SiC to grow and lowly even to lack.
Summary of the invention
The invention provides a kind of method, semi-conductor device manufacturing method, cause at edge SiC to grow the low problem even lacked to solve STI in prior art.
For solving the problems of the technologies described above, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: substrate is provided, substrate deposits oxygen pad layer and SiN layer successively; Shallow ditch groove separation process is carried out to form shallow isolated groove to substrate; Region over the substrate beyond shallow isolated groove deposits oxygen pad layer and silicon nitride layer successively; Carry out SiN to pull back technique; Oxygen pad layer deposition is carried out to shallow isolated groove surface; Carry out silica-filled to shallow isolated groove; Cmos device is manufactured in the active area of substrate.
As preferably, described in carry out SiN processing step of pulling back and comprise: wet etching is carried out to described silicon nitride layer, described SiN layer is etched away close to the side of shallow isolated groove.
As preferably, hot phosphoric acid is used to carry out wet etching to described silicon nitride layer.
As preferably, the percent by volume of described phosphoric acid is 85% ~ 88%, and solution temperature is 155 DEG C ~ 165 DEG C.
As preferably, also comprise SiN stripping technology.
As preferably, the described active area at substrate manufactures cmos device step and comprises: carry out ion implantation to substrate active area, to form N-type trap or P type trap; Described N-type trap or P type trap make grid oxic horizon; Form grid; At deposited on substrates silicon dioxide layer; Perform I/O device region light dope ion implantation, form I/O device light-dope structure; Make grid curb wall one; Carry out the injection of PMOS light dope, form PMOS device light-dope structure; Carry out germanium silicon technology; Make grid curb wall two; Carry out the injection of NMOS light dope, form nmos device light-dope structure; Carry out SiC selective epitaxial growth; Carry out source and drain ion implantation and form source-drain electrode; Make pre-metal dielectric, through hole, metal plug and metal level.
As preferably, described formation grid step comprises: carrying out polysilicon deposition for the formation of on the substrate of grid, and etch polysilicon forms grid.
As preferably, described in carry out SiC selective epitaxial growth step and comprise: the source-drain area of substrate is etched, forms groove; SiC selective epitaxial growth is carried out in described groove.
Compared with prior art, the present invention has the following advantages: invention increases SiN and to pull back technique, SiN is made to be etched away certain thickness in the horizontal, the top width of STI increases, thus the wall embeded silicon etching process that can control in follow-up SiC selective epitaxial growth process is to the loss of the silicon of shallow trench isolated side wall, strengthen SiC epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
Accompanying drawing explanation
Fig. 1 be in prior art STI technique complete after device architecture schematic diagram;
Fig. 2 be in prior art wall embeded silicon etching process complete after the schematic cross-section of semiconductor device;
Fig. 3 is method, semi-conductor device manufacturing method schematic flow sheet in the embodiment of the invention;
Fig. 4 is the schematic flow sheet forming cmos device in the embodiment of the invention in the active area of substrate;
Fig. 5 is the schematic diagram of technique of pulling back in the embodiment of the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.It should be noted that, accompanying drawing of the present invention all adopts the form of simplification and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 3, the invention provides a kind of method, semi-conductor device manufacturing method, comprising:
S1: provide substrate, substrate deposits oxygen pad layer and SiN layer successively;
S2: shallow ditch groove separation process is carried out to form shallow isolated groove to substrate;
S3: the region beyond shallow isolated groove over the substrate deposits oxygen pad layer and silicon nitride layer successively;
S4: carry out SiN and to pull back technique (SiN pull back).
Described step S4 comprises: use hot phosphoric acid to carry out wet etching to described silicon nitride layer, and described SiN layer is etched away close to the side of shallow isolated groove.The percent by volume of described hot phosphoric acid is 85% ~ 88%, and solution temperature is 155 DEG C ~ 165 DEG C.That is, as shown in Figure 5, the present invention carries out certain wet etching by hot phosphoric acid to SiN, SiN is made to be etched away certain thickness in the horizontal, STI top width increases, thus the wall embeded silicon etching process that can control in follow-up SiC selective epitaxial growth process is to the loss of the silicon of shallow trench isolated side wall, strengthen SiC epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
S5: carry out oxygen pad layer deposition to shallow isolated groove surface, then, carries out silica-filled to shallow isolated groove, then the SiN on stripping pad oxygen layer surface.
S6: form cmos device in the active area of substrate.This step comprises the following steps, see Fig. 4:
S601: carry out ion implantation to substrate active area, to form N-type trap or P type trap;
S602: form grid oxic horizon in described N-type trap or P type trap; Form grid, carrying out polysilicon deposition for the formation of on the substrate of grid, etch polysilicon forms grid.
S603: at deposited on substrates silicon dioxide layer, for the protection of the silicon face of device, reduces the loss of surface silicon.
S604: perform I/O device region light dope ion implantation, forms I/O device light-dope structure;
S605: make grid curb wall one.Specifically comprise: the deposit carrying out SiN in grid side, and grid curb wall one is formed to SiN etching;
S606: carry out the injection of PMOS light dope, forms PMOS device light-dope structure;
S607: carry out germanium silicon technology;
S608: make grid curb wall two, specifically comprise: carry out SiO at grid opposite side
2with the deposit of SiN, then etching forms grid curb wall two;
S609: carry out the injection of NMOS light dope, forms nmos device light-dope structure;
S610: carry out SiC selective epitaxial growth, described in carry out SiC selective epitaxial growth step and comprise: the source-drain area of substrate is etched, forms groove; SiC selective epitaxial growth is carried out in described groove.
Preferably; because SiN pulls back technique; the top width of STI is increased; therefore in the source-drain area etch step of substrate: the top width of STI is comparatively large, and the silicon dioxide making STI cover on the active area can be protected the silicon of STI edge sidewall, decreases the loss of STI sidewall silicon; the silicon that STI sidewall stays can be many; provide " seed " needed for more SiC growth, strengthen SiC epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
S611: carry out source and drain ion implantation and form source-drain electrode; Make pre-metal dielectric, through hole, metal plug and metal level.
In sum, the invention provides a kind of method, semi-conductor device manufacturing method, comprising: substrate is provided, substrate deposits oxygen pad layer and SiN layer successively; Shallow ditch groove separation process is carried out to form shallow isolated groove to substrate; Region over the substrate beyond shallow isolated groove deposits oxygen pad layer and silicon nitride layer successively; Carry out SiN to pull back technique; Oxygen pad layer deposition is carried out to shallow isolated groove surface; Carry out silica-filled to shallow isolated groove; Cmos device is manufactured in the active area of substrate.Invention increases SiN to pull back technique, SiN is made to be etched away certain thickness in the horizontal, the top width of STI increases, thus the wall embeded silicon etching process that can control in follow-up SiC selective epitaxial growth process is to the loss of the silicon of shallow trench isolated side wall, strengthen SiC epitaxial growth ability, improve SiC semiconductor manufacturing process ability.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. a method, semi-conductor device manufacturing method, is characterized in that, comprising:
Substrate is provided, substrate deposits oxygen pad layer and SiN layer successively;
Shallow ditch groove separation process is carried out to form shallow isolated groove to substrate;
Region over the substrate beyond shallow isolated groove deposits oxygen pad layer and silicon nitride layer successively;
Carry out SiN to pull back technique;
Oxygen pad layer deposition is carried out to shallow isolated groove surface;
Carry out silica-filled to shallow isolated groove;
Cmos device is manufactured in the active area of substrate.
2. method, semi-conductor device manufacturing method as claimed in claim 1, is characterized in that, described in carry out SiN processing step of pulling back and comprise: wet etching is carried out to described silicon nitride layer, described SiN layer is etched away close to the side of shallow isolated groove.
3. method, semi-conductor device manufacturing method as claimed in claim 2, is characterized in that, uses phosphoric acid to carry out wet etching to described silicon nitride layer.
4. method, semi-conductor device manufacturing method as claimed in claim 3, it is characterized in that, the percent by volume of described phosphoric acid is 85% ~ 88%, and solution temperature is 155 DEG C ~ 165 DEG C.
5. method, semi-conductor device manufacturing method as claimed in claim 1, is characterized in that, also comprise SiN stripping technology.
6. method, semi-conductor device manufacturing method as claimed in claim 1, is characterized in that, the described active area at substrate manufactures cmos device step and comprises:
Ion implantation is carried out to substrate active area, to form N-type trap or P type trap;
Described N-type trap or P type trap make grid oxic horizon;
Form grid;
At deposited on substrates silicon dioxide layer;
Perform I/O device region light dope ion implantation, form I/O device light-dope structure;
Make grid curb wall one;
Carry out the injection of PMOS light dope, form PMOS device light-dope structure;
Carry out germanium silicon technology;
Make grid curb wall two;
Carry out the injection of NMOS light dope, form nmos device light-dope structure;
Carry out SiC selective epitaxial growth;
Carry out source and drain ion implantation and form source-drain electrode;
Make pre-metal dielectric, through hole, metal plug and metal level.
7. method, semi-conductor device manufacturing method as claimed in claim 6, it is characterized in that, described formation grid step comprises: carrying out polysilicon deposition for the formation of on the substrate of grid, and etch polysilicon forms grid.
8. method, semi-conductor device manufacturing method as claimed in claim 6, is characterized in that, described in carry out SiC selective epitaxial growth step and comprise:
The source-drain area of substrate is etched, forms groove;
SiC selective epitaxial growth is carried out in described groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410693479.1A CN104392956A (en) | 2014-11-26 | 2014-11-26 | Semiconductor device manufacturing method |
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| CN201410693479.1A CN104392956A (en) | 2014-11-26 | 2014-11-26 | Semiconductor device manufacturing method |
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| CN104392956A true CN104392956A (en) | 2015-03-04 |
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| CN201410693479.1A Pending CN104392956A (en) | 2014-11-26 | 2014-11-26 | Semiconductor device manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345804A (en) * | 2021-05-24 | 2021-09-03 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of low-threshold-voltage NMOS (N-channel metal oxide semiconductor) tube with total dose resistance |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5940716A (en) * | 1996-03-15 | 1999-08-17 | Samsung Electronics Co., Ltd. | Methods of forming trench isolation regions using repatterned trench masks |
| US6093621A (en) * | 1999-04-05 | 2000-07-25 | Vanguard International Semiconductor Corp. | Method of forming shallow trench isolation |
| US20090294894A1 (en) * | 2008-05-28 | 2009-12-03 | International Business Machines Corporation | INTEGRATED CIRCUIT HAVING LOCALIZED EMBEDDED SiGe AND METHOD OF MANUFACTURING |
| US20100327329A1 (en) * | 2009-06-25 | 2010-12-30 | Hiroshi Itokawa | Semiconductor device and method of fabricating the same |
| CN102315152A (en) * | 2010-07-01 | 2012-01-11 | 中国科学院微电子研究所 | Isolation area, semiconductor device and forming method thereof |
| US20130069160A1 (en) * | 2011-09-15 | 2013-03-21 | International Business Machines Corporation | Trench isolation structure |
| CN103050443A (en) * | 2011-10-13 | 2013-04-17 | 国际商业机器公司 | Improving performance and reducing variation of narrow channel devices |
-
2014
- 2014-11-26 CN CN201410693479.1A patent/CN104392956A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5940716A (en) * | 1996-03-15 | 1999-08-17 | Samsung Electronics Co., Ltd. | Methods of forming trench isolation regions using repatterned trench masks |
| US6093621A (en) * | 1999-04-05 | 2000-07-25 | Vanguard International Semiconductor Corp. | Method of forming shallow trench isolation |
| US20090294894A1 (en) * | 2008-05-28 | 2009-12-03 | International Business Machines Corporation | INTEGRATED CIRCUIT HAVING LOCALIZED EMBEDDED SiGe AND METHOD OF MANUFACTURING |
| US20100327329A1 (en) * | 2009-06-25 | 2010-12-30 | Hiroshi Itokawa | Semiconductor device and method of fabricating the same |
| CN102315152A (en) * | 2010-07-01 | 2012-01-11 | 中国科学院微电子研究所 | Isolation area, semiconductor device and forming method thereof |
| US20130069160A1 (en) * | 2011-09-15 | 2013-03-21 | International Business Machines Corporation | Trench isolation structure |
| CN103050443A (en) * | 2011-10-13 | 2013-04-17 | 国际商业机器公司 | Improving performance and reducing variation of narrow channel devices |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345804A (en) * | 2021-05-24 | 2021-09-03 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of low-threshold-voltage NMOS (N-channel metal oxide semiconductor) tube with total dose resistance |
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Application publication date: 20150304 |