US9362357B2 - Blanket EPI super steep retrograde well formation without Si recess - Google Patents
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- US9362357B2 US9362357B2 US14/716,045 US201514716045A US9362357B2 US 9362357 B2 US9362357 B2 US 9362357B2 US 201514716045 A US201514716045 A US 201514716045A US 9362357 B2 US9362357 B2 US 9362357B2
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Definitions
- the present disclosure relates to formation of super steep retrograde well (SSRW) field effect transistors (FETs).
- SSRW super steep retrograde well
- FETs field effect transistors
- the present disclosure is particularly applicable to SSRW bulk CMOS-based devices for 22 nanometer (nm) technology nodes and beyond.
- AVT is known to deteriorate at high doping concentrations due to random dopant fluctuations (RDF) for very small devices such as SRAM devices. Since SSRW can provide low or no doping at the surface, AVT can be significantly improved. SSRW profile can also improve short channel issues due to the very high doping profile at sub-surface regions where punch-through can happen from the drain to the source.
- RDF random dopant fluctuations
- step height the height difference between the active region and field oxide (step height) causes process/device issues at the polysilicon gate and replacement metal gate (RMG) modules.
- RMG replacement metal gate
- some technical effects may be achieved in part by a method including: providing a SiN layer on a substrate; forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate; removing a top portion of the field oxide for each STI region by a controlled deglaze; removing the SiN layer; forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions; and epitaxially growing a silicon (Si) based layer on the substrate over the n-type and the p-type regions.
- aspects of the present disclosure include providing a sacrificial oxide layer on the substrate below the SiN layer.
- Other aspects include removing the sacrificial oxide layer by precleaning prior to epitaxially growing the Si based layer.
- Further aspects include removing 4 nm of field oxide from each STI region during precleaning
- Another aspect includes performing CMP on the STI regions down to a top surface of the SiN layer prior to the controlled deglaze.
- An additional aspect includes removing 5 to 10 nm of field oxide by the controlled deglaze.
- Other aspects include the controlled deglaze including a SiCoNi etch or a hydrogen fluoride (HF) etch followed by a SiCoNi etch followed by another HF etch.
- Further aspects include epitaxially growing the Si based layer by: epitaxially growing Si:C on the substrate to a thickness of 5 to 10 nm; and epitaxially growing Si on the Si:C to a thickness of 10 to 15 nm.
- Additional aspects include epitaxially growing the Si based layer over the p-type region by: forming a hardmask on the sacrificial oxide layer between the second and third STI regions after forming the n-type and p-type regions; removing the sacrificial oxide layer; and epitaxially growing Si, e.g. to a thickness of 15 to 20 nm, on the substrate over the n-type region.
- Further aspects include epitaxially growing the Si based layer over the p-type region by: forming a second hardmask on the Si over the n-type region; removing the first hardmask from between the second and third STI regions; removing the sacrificial oxide from between the second and third STI regions; epitaxially growing a Si:C layer to a thickness of 5 to 10 nm on the substrate over the p-type region; epitaxially growing Si, e.g. to a thickness of 10 to 15 nm, on the Si:C; and removing the second hardmask.
- Other aspects include removing the first hardmask from between the second and the third STI regions before the second hardmask deposition and forming the second hardmask on the Si over the n-type region.
- Additional aspects include epitaxially growing the Si based layer over the p-type region by: forming a hardmask on the sacrificial oxide layer between the first and the second STI regions after forming the n-type and p-type regions; removing the sacrificial oxide layer; epitaxially growing Si:C, e.g. to a thickness of 5 to 10 nm, on the substrate over the p-type region; epitaxially growing Si, e.g. to a thickness of 10 to 15 nm, on the Si:C.
- Further aspects include epitaxially growing a Si epitaxial layer over the n-type and p-type regions by: removing a first hardmask from between the first and the second STI regions; removing the sacrificial oxide from between the first and the second STI regions; and epitaxially growing Si, e.g. to a thickness of 10 to 15 nm on both n-type and p-type regions.
- FIGS. 2A through 2D schematically illustrate formation of a SSRW, in accordance with an exemplary embodiment
- FIGS. 3A through 3I schematically illustrate formation of a SSRW, in accordance with another exemplary embodiment.
- a controlled deglaze recesses the field oxide to a height of 25 nm above the substrate surface instead of 15 nm by conventional deglazing. As a result, no significant step height is created between the field oxide and epitaxially grown silicon.
- a deep well ion implantation is performed for each of NFET 209 and PFET 211 , followed by an anneal to drive the ions deep into the substrate to form the deep wells.
- B ions may be implanted at a dose of 1E12 to 5E13 per centimeter squared (cm 2 ) with an energy of 36 to 120 keV to form a B channel, or p-type region
- P or As may be implanted at a dose of 8E12 to 3E13 per cm 2 with an energy of 100 to 250 keV to form a P or As channel, or n-type region.
- Si:C 215 is epitaxially grown on the Si to a thickness of 5 nm to 10 nm, with a 0.5 to 2% carbon atomic concentration, on both the NFET 209 and the PFET 211 .
- Si 217 is epitaxially grown on the Si:C to a thickness of 10 nm to 15 nm. Because of the increased step height between the STI and the substrate over conventional processes, the epitaxial growth is limited to a substantially vertical growth between STI regions rather than extending laterally over the STI regions, which results in uniform and well-controlled Si and Si:C thicknesses. Any resulting step height at this point will be adjusted during a dummy gate oxide precleaning in the subsequent replacement metal gate process.
- the second hardmask 309 is etched from PFET 211 , exposing sacrificial oxide 201 , and the photoresist 311 is stripped, as illustrated in FIG. 3G .
- Another precleaning is performed to remove sacrificial oxide 201 , e.g. by a dry etch, from PFET 211 .
- a SiCoNi etch chemistry or a simple dry etch may be employed.
- Si 313 is epitaxially grown on the PFET 211 to a thickness of 15 to 20 nm, the sum of the thicknesses of Si:C 305 and Si 307 , as illustrated in FIG. 3H .
- second hardmask 309 covers NFET 209 , no further epitaxial growth occurs on NFET 209 .
- second hardmask 309 is removed from NFET 209 , for example by a wet or dry etch.
- the first hardmask may be removed from the PFET 211 before depositing the second hardmask 309 (not shown for illustrative convenience).
- the first hardmask 301 may be formed over the p-type region of the NFET 209 , and Si may be epitaxially grown to a thickness of 15 to 20 nm on the substrate over the n-type region.
- the second hardmask 309 may be formed over the Si over the n-type region, and the first hardmask and the sacrificial oxide may be removed from the p-type region.
- a Si:C layer may be epitaxially grown on the substrate in the p-type region to a thickness of 5 to 10 nm, followed by epitaxially growing Si over the Si:C to a thickness of 10 to 15 nm.
- the second hardmask 309 may be removed.
- the embodiments of the present disclosure can achieve several technical effects, controlled step height without Si RIE, uniform and well-controlled epitaxial growth thicknesses, resulting in improved gate height uniformity for replacement metal gates.
- the present disclosure enjoys industrial applicability in any of various types of highly integrated semiconductor devices for 22 nm technology products and beyond, particularly for 14 nm and 20 nm technology bulk CMOS-based products and beyond.
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---|---|---|---|---|
US9099525B2 (en) * | 2012-12-28 | 2015-08-04 | Globalfoundries Inc. | Blanket EPI super steep retrograde well formation without Si recess |
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US20150249129A1 (en) | 2015-09-03 |
US20140183551A1 (en) | 2014-07-03 |
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