CN114924437B

CN114924437B - Array substrate, preparation method thereof and display device

Info

Publication number: CN114924437B
Application number: CN202210549738.8A
Authority: CN
Inventors: 谢蒂旎; 王久石; 姚舜禹; 王利波; 吴仲远; 董学; 于静
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2022-05-20
Filing date: 2022-05-20
Publication date: 2024-01-12
Anticipated expiration: 2042-05-20
Also published as: WO2023221767A1; CN114924437A; WO2023221767A9

Abstract

The embodiment of the disclosure provides a preparation method of an array substrate, which comprises the following steps: preparing a pixel driving circuit on a substrate; preparing an insulating flat layer on the substrate which is completed with the steps; preparing a plurality of pixel electrodes on the substrate having the above steps completed; the pixel electrodes are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer; the pixel electrodes are arranged in an array; the interval distance between any two adjacent pixel electrodes along the row direction and/or the column direction of the array is smaller than or equal to a set value; the 2n-1 th pixel electrode is the first pixel electrode; the 2 n-th pixel electrode is a second pixel electrode; the preparing of the pixel electrode includes: the first pixel electrode is prepared through a first patterning process; the second pixel electrode is prepared through a second patterning process; wherein n is a positive integer.

Description

Array substrate, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display device.

Background

With the development of display technology, high resolution (PPI) liquid crystal display products are becoming popular because of finer picture display and better display effect.

Disclosure of Invention

In one aspect, an embodiment of the present disclosure provides a method for preparing an array substrate, including:

preparing a pixel driving circuit on a substrate;

preparing an insulating flat layer on the substrate which is completed with the steps;

preparing a plurality of pixel electrodes on the substrate having the above steps completed; the pixel electrodes are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer;

the pixel electrodes are arranged in an array; the interval distance between any two adjacent pixel electrodes along the row direction and/or the column direction of the array is smaller than or equal to a set value; the 2n-1 th pixel electrode is the first pixel electrode; the 2 n-th pixel electrode is a second pixel electrode;

the preparing of the pixel electrode includes: the first pixel electrode is prepared through a first patterning process; the second pixel electrode is prepared through a second patterning process; wherein n is a positive integer.

In some embodiments, preparing the first pixel electrode and the second pixel electrode includes:

forming a pattern of the first pixel electrode on the insulating planarization layer by using a patterning process; depositing a first insulating layer film;

Forming a pattern of the second pixel electrode on the first insulating layer film by a patterning process;

and etching to form a pattern of the first insulating layer by taking the pattern of the second pixel electrode as a mask.

forming a pattern of the first pixel electrode on the insulating planarization layer by using a patterning process;

depositing a first insulating layer film;

thinning a local area of the first insulating layer film through an etching process; the local region is a region of the first insulating layer film other than the pattern covering the first pixel electrode;

forming a pattern of the second pixel electrode in the thinned region of the first insulating layer film by adopting a patterning process;

annealing the first pixel electrode to crystallize the first pixel electrode;

Depositing to form a second pixel electrode film layer;

and forming a pattern of the second pixel electrode by adopting a patterning process.

forming a pattern of the first pixel electrode on the insulating flat layer by adopting a patterning process, and simultaneously retaining a first photoresist pattern on the pattern of the first pixel electrode; orthographic projection of the first photoresist pattern on the substrate only covers the pattern of the first pixel electrode;

depositing to form a second pixel electrode film layer;

forming a second photoresist pattern by adopting an exposure process; orthographic projection of the second photoresist pattern on the substrate only covers the pattern of the second pixel electrode;

etching to remove the second pixel electrode film layer in the area except the coverage area of the second photoresist pattern, and forming a pattern of the second pixel electrode;

and developing and removing the first photoresist pattern and the second photoresist pattern.

depositing a pixel electrode film layer on the insulating flat layer;

forming a positive photoresist pattern on the pixel electrode film layer by adopting an exposure process; orthographic projection of the positive photoresist pattern on the substrate only covers the pattern of the first pixel electrode;

Forming a negative photoresist pattern on the pixel electrode film layer by adopting an exposure process; the positive projection of the negative photoresist pattern on the substrate only covers the pattern of the second pixel electrode;

etching to form a pattern of the first pixel electrode and a pattern of the second pixel electrode;

and developing to remove the positive photoresist pattern and the negative photoresist pattern.

In some embodiments, further comprising: and depositing a second insulating layer on one side of the pattern of the first pixel electrode and one side of the pattern of the second pixel electrode, which are away from the substrate.

In a second aspect, an embodiment of the present disclosure further provides an array substrate, including: a substrate;

a pixel driving circuit on the substrate;

an insulating flat layer positioned on one side of the pixel driving circuit away from the substrate; the surface of one side of the insulating flat layer, which is away from the substrate, is a horizontal surface;

the pixel electrodes are positioned on one side of the insulating flat layer, which is away from the substrate, and are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer;

the pixel electrodes are arranged in an array;

the spacing distance between any two adjacent pixel electrodes along the row direction and/or the column direction of the array is less than or equal to 2 mu m; the two pixel electrodes which are arbitrarily adjacent are respectively a first pixel electrode and a second pixel electrode; the absolute value of the difference between the distance between the substrate and the side surface of the first pixel electrode facing away from the substrate and the distance between the substrate and the side surface of the second pixel electrode facing away from the substrate is in the range of 0 to 1500 angstroms.

In some embodiments, the pixel electrode includes a first sub-portion extending in a row direction of the array and a second sub-portion extending in a column direction of the array, and the first sub-portion and the second sub-portion are connected;

the extension length of the first sub-part is smaller than that of the second sub-part;

the orthographic projection of the via hole in the insulating flat layer on the substrate is positioned in the orthographic projection of the first sub-part on the substrate, and the first sub-part is connected with the pixel driving circuit through the via hole in the insulating flat layer.

In some embodiments, the second sub-portion of the first pixel electrode is equal in thickness to the second sub-portion of the second pixel electrode;

the first pixel electrode is in contact with the horizontal surface of the insulating planarization layer;

a first insulating layer is arranged between the second pixel electrode and the horizontal surface of the insulating flat layer;

the orthographic projection of the first insulating layer on the substrate coincides with the orthographic projection of the second pixel electrode on the substrate;

alternatively, the second pixel electrode is in contact with a horizontal surface of the insulating planarization layer.

In some embodiments, the thickness of the second sub-portion of the first pixel electrode is greater than the thickness of the second sub-portion of the second pixel electrode;

a first insulating layer is arranged between the second pixel electrode and the horizontal surface of the insulating flat layer; the orthographic projection of the first insulating layer on the substrate coincides with the orthographic projection of the second pixel electrode on the substrate;

the thickness of the second sub-portion of the first pixel electrode is equal to the sum of the thicknesses of the second sub-portion of the second pixel electrode and the first insulating layer.

In some embodiments, the pixel electrode further comprises a second insulating layer located on one side of the pixel electrode facing away from the substrate, and an orthographic projection of the second insulating layer on the substrate covers the whole substrate.

In a third aspect, an embodiment of the present disclosure further provides a display device, where the display device includes the above array substrate.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure, without limitation to the disclosure. The above and other features and advantages will become more readily apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

Fig. 1 is a schematic top view illustrating an arrangement of pixel electrodes in a display panel according to the disclosure.

Fig. 2 is a schematic top view of a structure of an array substrate according to an embodiment of the disclosure.

Fig. 3 is a cross-sectional view of one configuration along the AA' section line of fig. 2.

Fig. 4 is a cross-sectional view of another configuration along the AA' section line of fig. 2.

Fig. 5 is a further structural cross-sectional view taken along the AA' section line in fig. 2.

Fig. 6 is a further structural cross-sectional view taken along the AA' section line in fig. 2.

Fig. 7 is a structural cross-sectional flow chart of a manufacturing method of the array substrate of fig. 3-5.

Fig. 8 is a top view of a process for fabricating the array substrate of fig. 7.

Fig. 9 is a structural cross-sectional flow chart of another manufacturing method for manufacturing the array substrate of fig. 3.

Fig. 10 is a structural cross-sectional flow chart of a manufacturing method of the array substrate of fig. 6.

Fig. 11 is a structural cross-sectional flow chart of another manufacturing method for manufacturing the array substrate of fig. 6.

Fig. 12 is a structural cross-sectional flow chart of still another preparation method for preparing the array substrate of fig. 6.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following describes in further detail the array substrate, the preparation method thereof, and the display device provided by the embodiments of the present disclosure with reference to the accompanying drawings and detailed description.

Embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configuration formed based on the manufacturing process. Thus, the regions illustrated in the figures have schematic properties and the shapes of the regions illustrated in the figures illustrate specific shapes of the regions, but are not intended to be limiting.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

For the same size liquid crystal display panel, the high resolution pixel arrangement compresses the distance between the pixel electrodes. In the disclosed technology, the pixel electrode is prepared by first depositing a single-layer light-transmitting conductive film (such as an ITO film), and then forming a pattern of the pixel electrode through steps of exposure, development and wet etching. When the distance between adjacent pixel electrodes is small (e.g., less than 1 μm or 2 μm), it is difficult to thoroughly expose the photoresist to form a pattern, such as to only locally expose the photoresist to form a pattern, and photoresist pattern blocking (i.e., no thorough exposure between patterns) occurs at some small pattern gaps, so that uniformity of the pixel electrode patterns in the display panel cannot be ensured.

Referring to fig. 1, a schematic top view of an arrangement of pixel electrodes in a display panel according to the disclosed technology is shown; in a high-resolution display panel, the gaps between adjacent pixel electrodes 3 are small, and smaller gap patterns between the pixel electrodes 3 need to be manufactured when the patterns of the pixel electrodes 3 are prepared; if the gap width a is less than or equal to 0.9 μm; in the process for preparing the patterns of the pixel electrode 3, when the gap width a between the adjacent pixel electrodes 3 is 0.9 μm, the gap width between the adjacent photoresist patterns corresponding to the adjacent pixel electrode 3 patterns formed in advance is required to be 0.4 μm, and the etching residue of the pixel electrode film layer at the photoresist pattern gap is easily caused by wet etching the patterns of the pixel electrode 3 under the gaps of the adjacent photoresist patterns which are small.

When the above process for preparing the pixel electrode patterns adopts the digital exposure equipment, the gap width value between adjacent photoresist patterns is input to the digital exposure equipment to be 0.4 μm, and meanwhile, the empirical value of 0.5 is subtracted on the basis of 0.4 μm, so that the gap width between adjacent pixel electrodes can be finally obtained in theory; however, at this time, the input value of the digital exposure apparatus becomes-0.1, so that the digital exposure apparatus cannot realize the gap width between adjacent photoresist patterns of 0.4 μm at all, and thus cannot realize the preparation of the gap width between adjacent pixel electrodes of 0.9 μm at all.

In order to solve the above-mentioned problems in the prior art, in a first aspect, an embodiment of the present disclosure provides an array substrate, referring to fig. 2 and 3, fig. 2 is a schematic top view of the structure of the array substrate in the embodiment of the present disclosure; FIG. 3 is a cross-sectional view of one configuration along the AA' section line of FIG. 2; wherein, include: a substrate 1; a pixel driving circuit 2 on the substrate 1; an insulating planarization layer 4 on a side of the pixel driving circuit 2 facing away from the substrate 1; the side surface of the insulating flat layer 4 facing away from the substrate 1 is a horizontal surface; a plurality of pixel electrodes 3 located on a side of the insulating planarization layer 4 facing away from the substrate 1, and connected to the pixel driving circuit 2 through via holes 40 formed in the insulating planarization layer 4, respectively; the plurality of pixel electrodes 3 are arranged in an array; the spacing distance b between any two adjacent pixel electrodes 3 along the row direction X and/or the column direction Y of the array is less than or equal to a set value; any two adjacent pixel electrodes 3 are a first pixel electrode 31 and a second pixel electrode 32, respectively; the absolute value of the difference between the distance between the side surface of the first pixel electrode 31 facing away from the substrate 1 and the distance between the side surface of the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 ranges from 0 to 1500 angstroms; the set value was 2. Mu.m.

In some embodiments, the set point is 0.9 μm. In some embodiments, the set point is 1 μm. In some embodiments, the set point is 1.2 μm.

In the present embodiment, the description is made with the interval distance b between the first pixel electrode 31 and the second pixel electrode 32 in the row direction X of the array being smaller than the set value. For example: in the present embodiment, the separation distance b between the first pixel electrode 31 and the second pixel electrode 32 is 0.9 μm. The distance between the side surface of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is h1, and the distance between the side surface of the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is h2, then 0.ltoreq. |h1-h2|.ltoreq.1500 angstroms.

The array substrate provided in the embodiment is applied to a TN (Twisted Nematic) type liquid crystal display panel, that is, the array substrate and the counter-cell substrate form a gap, and the gap is filled with liquid crystal. An entire common electrode is arranged on the opposite box substrate, and an electric field capable of deflecting liquid crystal is formed between the common electrode and the pixel electrode on the array substrate. And a backlight source is arranged on one side of the array substrate, which is away from the opposite box substrate, and the backlight provided by the backlight source is used for realizing the display of the whole liquid crystal display panel after passing through the pixel electrode, the liquid crystal layer and the common electrode.

In some embodiments, referring to fig. 3, the pixel driving circuit 2 includes a transistor 20, an active layer 201, a gate 202, a source 203 and a drain 204 of the transistor 20 are disposed on the substrate 1, the source 203 and the drain 204 are disposed on the same film, and the active layer 201, the gate 202 and the source 203 are sequentially distributed away from the substrate 1; a gate insulating layer 205 is further provided between the gate electrode 202 and the active layer 201; the source electrode 203 and the drain electrode 204 are arranged on the same layer, and an intermediate dielectric layer 206 is arranged between the grid electrode 202 and the source electrode 203 and the drain electrode 204; the insulating planarization layer 4 is located on the source electrode 203 and the drain electrode 204, and the insulating planarization layer 4 can fill up the surface of the substrate 1 where the entire source electrode 203 and the drain electrode 204 are located, and a surface of the insulating planarization layer 4 facing away from the substrate 1 is a horizontal surface, so that a pattern of the pixel electrode 3 is formed on the horizontal surface later. In addition, a light shielding metal layer 207 is further disposed on a side of the active layer 201, which is close to the substrate 1, and a buffer layer 208 is further disposed between the light shielding metal layer 207 and the active layer 201; the light shielding metal layer 207 can shield light irradiated onto the active layer 201, thereby ensuring that the switching performance of the transistor 20 is not affected by light.

In some embodiments, referring to fig. 2, the pixel electrode 3 includes a first sub-portion 301 and a second sub-portion 302, the first sub-portion 301 extending along a row direction X of the array, the second sub-portion 302 extending along a column direction Y of the array, and the first sub-portion 301 and the second sub-portion 302 being connected; the extension length of the first sub-portion 301 is smaller than the extension length of the second sub-portion 302; the orthographic projection of the via hole 40 in the insulating planarization layer 4 on the substrate 1 is located within the orthographic projection of the first sub-portion 301 on the substrate 1, and the first sub-portion 301 is connected to the pixel driving circuit 2 through the via hole 40 in the insulating planarization layer 4. The first sub-portion 301 is connected to the drain 204 of the transistor 20 in the pixel driving circuit 2 through the via 40 in the insulating planarization layer 4.

In some embodiments, referring to fig. 2, the second sub-portion 302 of the first pixel electrode 31 and the second sub-portion 302 of the second pixel electrode 32 are parallel to each other and sequentially arranged along the row direction X of the array; the first sub-portion 301 of the first pixel electrode 31 and the first sub-portion 301 of the second pixel electrode 32 are parallel to each other and are sequentially arranged along the column direction Y of the array. By the arrangement, the arrangement of the pixel electrodes 3 on the array substrate can be more dense, so that the resolution of a display panel adopting the array substrate is improved.

In some embodiments, the front projection of the first sub-portion 301 onto the substrate 1 is rectangular, and the front projection of the second sub-portion 302 onto the substrate 1 is rectangular.

In some embodiments, referring to fig. 2, the orthographic projection of the pixel driving circuit on the substrate 1 is located at a spacing region between adjacent pixel electrodes 3 along the column direction Y of the array; the orthographic projection of the transistor 20 on the substrate 1 partially overlaps the first sub-portion 301 of the pixel electrode 3; the orthographic projection of the pixel driving circuit on the substrate 1 does not overlap with the second sub-portion 302 of the pixel electrode 3, thereby ensuring that the backlight light can normally pass through the pixel electrode 3 for display.

In some embodiments, referring to fig. 2, the array substrate further includes a plurality of gate lines 7 and a plurality of data lines 8, the gate lines 7 extending along a row direction X of the array, and the plurality of gate lines 7 being respectively located between two adjacent rows of pixel electrodes 3; the orthographic projection of the gate line 7 on the substrate 1 may partially overlap the first sub-portion 301 of the pixel electrode 3; the orthographic projection of the gate line 7 on the substrate 1 does not overlap the second sub-portion 302 of the pixel electrode 3. The data lines 8 extend along the column direction Y of the array, and the plurality of data lines 8 are respectively located between two adjacent columns of pixel electrodes 3; the orthographic projection of the data line 8 on the substrate 1 may partially overlap or not overlap the second sub-portion 302 of the pixel electrode 3. For example: when the width of the data line 8 in the array row direction X is 1.2 μm, since the interval distance between the adjacent two pixel electrodes 3 in the row direction X is 0.9 μm, the orthographic projection of the data line 8 on the substrate 1 partially overlaps the second sub-portion 302 of the pixel electrode 3.

In some embodiments, referring to fig. 3, the second sub-portion of the first pixel electrode 31 is equal in thickness to the second sub-portion of the second pixel electrode 32; the first pixel electrode 31 is in contact with the horizontal surface of the insulating planarization layer 4; a first insulating layer 5 is further provided between the second pixel electrode 32 and the horizontal surface of the insulating planarization layer 4; the front projection of the first insulating layer 5 onto the substrate 1 coincides with the front projection of the second pixel electrode 32 onto the substrate 1.

In some embodiments, referring to fig. 3, the insulating planarization layer 4 includes an organic insulating layer. The thickness of the organic insulating layer may be made thicker, thereby facilitating the formation of a horizontal surface on the side thereof facing away from the substrate 1.

In some embodiments, the material of the organic insulating layer may be PI (polyimide), PC (polycarbonate), PMMA (polymethyl methacrylate), or the like.

In some embodiments, the thickness of the second sub-portion of the first pixel electrode 31 ranges from 400 to 1200 angstroms; the thickness of the second sub-portion of the second pixel electrode 32 ranges from 400 to 1200 angstroms. In some embodiments, the thickness of the first insulating layer 5 ranges from 50 to 800 angstroms.

In some embodiments, the thicknesses of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 may be 800 angstroms, respectively; accordingly, the thickness of the first insulating layer 5 may be 50 angstroms or 800 angstroms. In some embodiments, the thicknesses of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 may be 400 angstroms, respectively; accordingly, the thickness of the first insulating layer 5 may be 600 angstroms.

In some embodiments, the material of the first and second pixel electrodes 31 and 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide. In some embodiments, the material of the first insulating layer 5 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

In some embodiments, referring to FIG. 4, there is shown another structural cross-sectional view along the AA' section line of FIG. 2; the insulating planarization layer 4 includes an organic insulating layer 41 and an inorganic insulating layer 42, and the organic insulating layer 41 and the inorganic insulating layer 42 are stacked apart from the substrate 1 in order. The provision of the inorganic insulating layer 42 can improve or avoid damage to the organic insulating layer 41 caused by etching to form the pattern of the first insulating layer 5.

In some embodiments, the material of inorganic insulating layer 42 includes any of silicon nitride, silicon oxide, silicon oxynitride.

In some embodiments, referring to FIG. 5, there is yet another structural cross-sectional view along the AA' section line of FIG. 2; the thickness of the second sub-portion of the first pixel electrode 31 is greater than the thickness of the second sub-portion of the second pixel electrode 32; the first pixel electrode 31 is in contact with the horizontal surface of the insulating planarization layer 4; a first insulating layer 5 is further provided between the second pixel electrode 32 and the horizontal surface of the insulating planarization layer 4; the front projection of the first insulating layer 5 on the substrate 1 coincides with the front projection of the second pixel electrode 32 on the substrate 1; the thickness of the second sub-portion of the first pixel electrode 31 is equal to the sum of the thicknesses of the second sub-portion of the second pixel electrode 32 and the first insulating layer 5.

The first pixel electrode 31 and the second pixel electrode 32 respectively form an electric field with an entire common electrode disposed on the opposite box substrate side, and the above arrangement can enable a side surface of the first pixel electrode 31, which is away from the substrate 1, to be flush with a side surface of the second pixel electrode 32, which is away from the substrate 1, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the second pixel electrode 32 have the same display brightness when displaying gray scale signals with the same size, and display stripes (that is, gray scale mura phenomenon is improved or avoided) are improved or avoided, and a display effect of a display panel using the array substrate is improved.

In some embodiments, referring to fig. 5, the second sub-portion of the first pixel electrode 31 has a thickness of 1200 angstroms; the second sub-portion of the second pixel electrode 32 has a thickness of 400 angstroms; the thickness of the first insulating layer 5 is 800 angstroms.

In some embodiments, referring to FIG. 6, there is yet another structural cross-sectional view along the AA' section line of FIG. 2; the second sub-portion of the first pixel electrode 31 is equal in thickness to the second sub-portion of the second pixel electrode 32; the first pixel electrode 31 is in contact with the horizontal surface of the insulating planarization layer 4; the second pixel electrode 32 is in contact with the horizontal surface of the insulating planarization layer 4.

In some embodiments, the material of the first pixel electrode 31 includes any one of crystallized indium tin oxide, crystallized indium zinc oxide, crystallized indium gallium zinc oxide; the material of the second pixel electrode 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide.

In some embodiments, the material of the first pixel electrode 31 includes any one of indium tin oxide, indium zinc oxide, indium gallium zinc oxide; the material of the second pixel electrode 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide. Wherein the first pixel electrode 31 and the second pixel electrode 32 are the same material.

In some embodiments, referring to fig. 3-6, the array substrate further comprises a second insulating layer 6, located on a side of the pixel electrode 3 facing away from the substrate 1, and an orthographic projection of the second insulating layer 6 on the substrate 1 covers the entire substrate 1. The second insulating layer 6 is provided to facilitate subsequent formation of the alignment film, spacers, and the like thereon.

In some embodiments, the second insulating layer 6 material comprises any of silicon nitride, silicon oxide, silicon oxynitride.

In some embodiments, the thickness of the second insulating layer 6 ranges from 800 to 2000 angstroms.

In some embodiments, referring to fig. 3, when the insulating planarization layer 4 includes only an organic insulating layer, etching is performed on the region of the insulating planarization layer 4 not covered by the pixel electrode 3 when patterning the first insulating layer 5, so that the second insulating layer 6 partially penetrates into the insulating planarization layer 4 at the region of the insulating planarization layer 4 not covered by the pixel electrode 3.

Based on the above structure of the array substrate, in a second aspect, an embodiment of the present disclosure further provides a method for manufacturing the array substrate, where the method includes: step S01: a pixel driving circuit is prepared on a substrate.

Step S02: an insulating planarization layer is prepared on the substrate on which the above steps are completed.

Step S03: a plurality of pixel electrodes are prepared on the substrate on which the above steps are completed.

The pixel electrodes are respectively connected with the pixel driving circuit through via holes arranged in the insulating flat layer; the pixel electrodes are arranged in an array; the interval distance between any two adjacent pixel electrodes along the row direction and/or the column direction of the array is smaller than or equal to a set value; the 2n-1 th pixel electrode is the first pixel electrode; the 2 n-th pixel electrode is a second pixel electrode; the preparation of the pixel electrode includes: the first pixel electrode is prepared through a first patterning process; the second pixel electrode is prepared through a second patterning process; wherein n is a positive integer.

In this example, the set value was 2. Mu.m. The first pixel electrode is prepared by a first patterning process by causing a first pixel electrode to be formed along a row direction and/or a column direction of the array; compared with the scheme that all pixel electrodes are prepared through one-time composition technology in the prior art, the preparation of the ultra-small gaps between adjacent pixel electrodes can be realized under the exposure precision of the existing exposure equipment, so that accurate patterns of the pixel electrodes are formed, and the uniformity of the patterns of the pixel electrodes in the array substrate is ensured.

In some embodiments, in the subsequent structural cross-sectional views of the steps of the manufacturing method of the array substrate, only the manufacturing processes of the first pixel electrode, the second pixel electrode, the first insulating layer and the second insulating layer on the insulating planarization layer are illustrated, the structure of the pixel driving circuit and the manufacturing steps are not illustrated in the structural cross-sectional views, and the pixel driving circuit may employ the pixel driving circuit structure in fig. 3. Referring to fig. 7, a structural cross-sectional flow chart of one manufacturing method for manufacturing the array substrate of fig. 3 to 5; FIG. 8 is a top view of a process for fabricating the array substrate of FIG. 7; wherein the first pixel electrode 31 and the second pixel electrode 32 are prepared above the insulating planarization layer 4, comprising: step S101: forming a pattern of a first pixel electrode 31 on the insulating planarization layer 4 using a patterning process; a first insulating layer film 9 is deposited.

In this step, the pattern of the first pixel electrode 31 is formed by a sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching process. A first insulating layer film 9 of silicon nitride material is deposited by chemical vapor deposition.

Step S102: a pattern of the second pixel electrode 32 is formed on the first insulating layer film 9 using a patterning process.

In this step, the pattern of the second pixel electrode 32 is formed by a sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching process.

Step S103: the pattern of the first insulating layer 5 is etched using the pattern of the second pixel electrode 32 as a mask.

In this step, the first insulating layer 5 is patterned by etching through a dry etching process, and there is a risk of damage to the region of the insulating flat layer 4 of the organic insulating material that is not covered by the first pixel electrode 31 and the second pixel electrode 32, and if the insulating flat layer 4 of the organic insulating material is damaged through the dry etching process, the slope angle of the edge end faces of the second pixel electrode 32 and the first insulating layer 5 increases, and the slope becomes steep.

Step S104: a second insulating layer 6 is deposited on the side of the pattern of first pixel electrodes 31 and the pattern of second pixel electrodes 32 facing away from the substrate 1.

In this step, the second insulating layer 6 is formed by chemical vapor deposition.

In some embodiments, when preparing the array substrate in fig. 3, the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 is 800 angstroms; the thickness of the first insulating layer 5 is 800 angstroms. The step difference between the first pixel electrode 31 and the second pixel electrode 32 is higher, and the etching of the first insulating layer 5 has a larger damage risk to the insulating flat layer 4, if the etching of the first insulating layer 5 causes a larger damage to the insulating flat layer 4, the edge end face of the second pixel electrode 32 forms a steep slope, the slope angle is larger, and the climbing fracture risk of the second insulating layer 6 is high.

In some embodiments, when preparing the array substrate in fig. 3, the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 is 400 angstroms; the thickness of the first insulating layer 5 is 600 angstroms. Compared with the above-mentioned pixel electrode thickness scheme, the distance difference between the surface of the side of the first pixel electrode 31, which is away from the substrate 1, and the substrate 1 is reduced, so that the difference of the display brightness of the sub-pixel using the first pixel electrode 31 and the sub-pixel using the second pixel electrode 32 is reduced when the same gray scale signal is displayed, and the display fringe phenomenon (i.e. mura phenomenon) can be improved; at the same time, the risk of damage to the insulating planarization layer 4 by etching of the first insulating layer 5 is also improved.

In some embodiments, the thickness of the second sub-portion of the first pixel electrode 31 is 1200 angstroms when the array substrate of fig. 5 is prepared; the second sub-portion of the second pixel electrode 32 has a thickness of 400 angstroms; the thickness of the first insulating layer 5 is 800 angstroms. Compared with the thickness scheme of the second sub-portion of the pixel electrode, the difference between the distance between the surface of the side of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is 0, so that the sub-pixel using the first pixel electrode 31 and the sub-pixel using the second pixel electrode 32 have the same display brightness when displaying the gray scale signals with the same size, and the display fringe phenomenon (i.e. display mura phenomenon) can be further improved or avoided; however, the first pixel electrode 31 is thick, and the first pixel electrode film layer is easy to be partially crystallized due to the heat accumulation effect when the first pixel electrode film layer is deposited, so that etching residues appear when the first pixel electrode 31 pattern is formed by etching; in addition, etching of the first insulating layer 5 may risk a certain damage to the insulating planarization layer 4.

In some embodiments, when the array substrate in fig. 4 is prepared, the preparation of the insulating flat layer 4 includes sequentially preparing an organic insulating layer and an inorganic insulating layer above the substrate 1, and by adopting the preparation method of the array substrate in fig. 7, the damage of the first insulating layer 5 to the insulating flat layer 4 caused by etching is reduced; however, since the insulating planarization layer 4 is formed by two layers of an organic insulating layer and an inorganic insulating layer, the transmittance of the array substrate is reduced, and a mask process is required to be added to prepare a via hole in the inorganic insulating layer, where the via hole is a via hole capable of realizing connection between the pixel electrode and the drain electrode of the transistor.

In some embodiments, referring to fig. 9, a structural cross-sectional flow chart of another fabrication method for fabricating the array substrate of fig. 3; a first pixel electrode 31 and a second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S201: a patterning process is used to form a pattern of the first pixel electrode 31 on the insulating planarization layer 4.

In this step, the pattern of the first pixel electrode 31 is formed by a sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching process.

Step S202: a first insulating layer film 9 is deposited.

In this step, a first insulating layer film 9 of silicon nitride material is deposited by chemical vapor deposition.

Step S203: thinning the local area of the first insulating layer film 9 by an etching process; the partial region is a region of the first insulating layer film 9 other than the pattern covering the first pixel electrode 31.

In this step, while forming a via pattern connecting the second pixel electrode 32 and the drain electrode of the transistor in the first insulating layer film 9, a partial region of the first insulating layer film 9 is thinned from 800 angstroms to several tens of angstroms by a halftone mask dry etching process.

Step S204: a patterning process is used to form a pattern of the second pixel electrode 32 in the thinned region of the first insulating layer film 9.

Step S205: the pattern of the first insulating layer 5 is etched using the pattern of the second pixel electrode 32 as a mask.

In this step, the first insulating layer 5 is patterned by a dry etching process.

Step S206: a second insulating layer 6 is deposited on the side of the pattern of first pixel electrodes 31 and the pattern of second pixel electrodes 32 facing away from the substrate 1.

In some embodiments, the thicknesses of the second sub-portions of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 are 800 angstroms, respectively, when the array substrate of fig. 3 is prepared; the thickness of the first insulating layer 5 is several tens of angstroms. Compared with the preparation scheme of the pixel electrode in fig. 7, the distance difference between the side surface of the first pixel electrode 31, away from the substrate 1, and the substrate 1 is reduced, so that the difference of display brightness between the sub-pixel adopting the first pixel electrode 31 and the sub-pixel adopting the second pixel electrode 32 is reduced when the same gray scale signal is displayed, the display fringe phenomenon (i.e. the display mura phenomenon) can be improved, and the display effect of the display panel adopting the array substrate is improved. However, when the pattern of the first insulating layer 5 is formed by etching, there is a large risk of damage to the insulating flat layer 4 of the organic insulating material, if the damage is large, the edge end face of the second pixel electrode 32 will form a steep slope, and the slope angle is large, so that the risk of climbing and breaking of the second insulating layer 6 is high.

In some embodiments, referring to fig. 10, a structural cross-sectional flow diagram of one fabrication method for fabricating the array substrate of fig. 6; a first pixel electrode 31 and a second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S301: a patterning process is used to form a pattern of the first pixel electrode 31 on the insulating planarization layer 4.

Step S302: the first pixel electrode 31 is annealed to crystallize the first pixel electrode 31.

In this step, the first pixel electrode 31 is annealed at a high temperature of 230 ℃. The annealing process can crystallize the material of the first pixel electrode 31, such as crystallizing an indium tin oxide material, and the crystallized material of the first pixel electrode 31 is not etched away when the second pixel electrode film 10 is etched to form a pattern later.

Step S303: the second pixel electrode film layer 10 is deposited.

In this step, the second pixel electrode film layer 10 is formed by sputtering deposition, and the orthographic projection of the second pixel electrode film layer 10 on the substrate 1 covers the entire substrate 1.

Step S304: a patterning process is used to pattern the second pixel electrode 32.

In this step, the pattern of the second pixel electrode 32 is formed by a sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching process. During this etching process, etching damage is not caused to the pattern of the first pixel electrode 31.

Step S305: a second insulating layer 6 is deposited on the side of the pattern of first pixel electrodes 31 and the pattern of second pixel electrodes 32 facing away from the substrate 1.

In this embodiment, in the method for manufacturing an array substrate in fig. 10, the distance difference between the surface of the side of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is made to be 0, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the second pixel electrode 32 have the same display brightness when displaying the same gray scale signal, and the display fringe phenomenon (i.e. the mura phenomenon) can be avoided, thereby improving the display effect of the display panel using the array substrate. Meanwhile, the method for manufacturing the array substrate in fig. 10 does not need to form the first insulating layer, so that the method does not cause any damage to the insulating planarization layer 4 of the organic insulating material and/or the inorganic insulating material that is not covered by the first pixel electrode 31 and the second pixel electrode 32, and further the second insulating layer 6 does not have a risk of climbing and breaking.

In some embodiments, referring to fig. 11, a structural cross-sectional flow chart of another manufacturing method for manufacturing the array substrate of fig. 6; a first pixel electrode 31 and a second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S401: forming a pattern of the first pixel electrode 31 on the insulating planarization layer 4 by a patterning process while retaining the first photoresist pattern 11 on the pattern of the first pixel electrode 31; the orthographic projection of the first photoresist pattern 11 on the substrate 1 covers only the pattern of the first pixel electrode 31.

Step S402: the second pixel electrode film layer 10 is deposited.

Step S403: forming a second photoresist pattern 12 using an exposure process; the orthographic projection of the second photoresist pattern 12 on the substrate 1 covers only the pattern of the second pixel electrode 32.

In this step, the exposure process includes steps of exposure and development.

Wherein both the first photoresist pattern 11 and the second photoresist pattern 12 may use either a positive photoresist or a negative photoresist.

Step S404: the second pixel electrode film layer 10 is etched away except the area covered by the second photoresist pattern 12 to form a pattern of the second pixel electrode 32.

In this step, the second pixel electrode 32 is patterned by a wet etching process.

Step S405: and developing and removing the first photoresist pattern and the second photoresist pattern.

Step S406: a second insulating layer 6 is deposited on the side of the pattern of first pixel electrodes 31 and the pattern of second pixel electrodes 32 facing away from the substrate 1.

In this embodiment, in the method for manufacturing an array substrate in fig. 11, the distance difference between the surface of the side of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is made to be 0, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the second pixel electrode 32 have the same display brightness when displaying the same gray scale signal, and the display fringe phenomenon (i.e. the mura phenomenon) can be avoided, thereby improving the display effect of the display panel using the array substrate. Meanwhile, the method for manufacturing the array substrate in fig. 11 does not need to form the first insulating layer, so that the method does not cause any damage to the insulating planarization layer 4 of the organic insulating material and/or the inorganic insulating material that is not covered by the first pixel electrode 31 and the second pixel electrode 32, and further the second insulating layer 6 does not have a risk of climbing fracture. However, when the second pixel electrode film layer 10 is formed by deposition, the photoresist material of the first photoresist pattern 11 is easy to splash out, pollute the deposition chamber, and cause poor deposition of the second pixel electrode film layer 10.

In some embodiments, referring to fig. 12, a structural cross-sectional flow chart of yet another fabrication method for fabricating the array substrate of fig. 6; a first pixel electrode 31 and a second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S501: a pixel electrode film layer 13 is deposited on the insulating planarization layer 4.

In this step, the pixel electrode film layer 13 is formed by sputtering deposition, and the orthographic projection of the pixel electrode film layer 13 on the substrate 1 covers the entire substrate 1.

Step S502: forming a positive photoresist pattern 14 on the pixel electrode film layer 13 by an exposure process; the orthographic projection of the positive photoresist pattern 14 on the substrate 1 covers only the pattern of the first pixel electrode.

In this step, the exposure process includes the steps of film coating, exposure using the mask plate 16, and development.

Step S503: forming a negative photoresist pattern 15 on the pixel electrode film layer 13 by adopting an exposure process; the positive projection of the negative photoresist pattern 15 onto the substrate 1 covers only the pattern of the second pixel electrode.

Step S504: etching forms a pattern of the first pixel electrode 31 and a pattern of the second pixel electrode 32.

In this step, the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 are formed by a wet etching process.

Step S505: and developing to remove the positive photoresist pattern and the negative photoresist pattern.

Step S506: a second insulating layer 6 is deposited on the side of the pattern of first pixel electrodes 31 and the pattern of second pixel electrodes 32 facing away from the substrate 1.

In this embodiment, in the method for manufacturing an array substrate in fig. 12, the distance difference between the surface of the side of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is made to be 0, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the second pixel electrode 32 have the same display brightness when displaying the same gray scale signal, and the display fringe phenomenon (i.e. the mura phenomenon) can be avoided, thereby improving the display effect of the display panel using the array substrate. Meanwhile, the method for manufacturing the array substrate in fig. 12 does not need to form the first insulating layer, so that the method does not cause any damage to the insulating planarization layer 4 of the organic insulating material and/or the inorganic insulating material that is not covered by the first pixel electrode 31 and the second pixel electrode 32, and further the second insulating layer 6 does not have a risk of climbing and breaking. However, in this method, when the negative photoresist film layer is coated and developed to form the negative photoresist pattern 15, the developer is liable to damage the positive photoresist pattern 14, resulting in the defect of the first pixel electrode 31 pattern.

The array substrate and the preparation method thereof provided by the embodiment of the disclosure are characterized in that the 2n-1 th pixel electrode is prepared by a first composition process along the row direction and/or the column direction of the pixel electrode array; compared with the scheme that all pixel electrodes are prepared through one-time composition process in the prior art, the preparation of ultra-small gaps between adjacent pixel electrodes can be realized under the exposure precision of the current exposure equipment, so that accurate patterns of the pixel electrodes are formed, and the uniformity of the patterns of the pixel electrodes in the array substrate is ensured; and further, the preparation of the high-resolution array substrate can be better realized.

In a third aspect, an embodiment of the present disclosure further provides a display panel, where the display panel includes the array substrate in the foregoing embodiment.

In some embodiments, the display panel further includes a counter substrate, the array substrate and the counter substrate form a gap with respect to the cell, and the gap is filled with liquid crystal. That is, the display panel in this embodiment is a liquid crystal display panel.

In some embodiments, the display panel is a TN (Twisted Nematic) type liquid crystal display panel, that is, a whole surface of a common electrode is disposed on a cell substrate, and an electric field capable of deflecting liquid crystal is formed between the common electrode and a pixel electrode on an array substrate. And a backlight source is arranged on one side of the array substrate, which is away from the opposite box substrate, and the backlight provided by the backlight source is used for realizing the display of the whole liquid crystal display panel after passing through the pixel electrode, the liquid crystal layer and the common electrode.

By adopting the array substrate in the embodiment, the high-resolution display of the display panel can be realized, so that the display quality of the display panel is improved.

In a fourth aspect, embodiments of the present disclosure further provide a display device including the display panel in the above embodiments.

By adopting the display panel in the embodiment, the high-resolution display of the display device can be realized, so that the display quality of the display device is improved.

The display device may be: LCD panel, LCD TV, mobile phone, tablet computer, notebook computer, display, digital photo frame, navigator, etc.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims

1. The preparation method of the array substrate comprises the following steps:

preparing a pixel driving circuit on a substrate;

2. The method of manufacturing an array substrate according to claim 1, wherein manufacturing the first pixel electrode and the second pixel electrode includes:

3. The method of manufacturing an array substrate according to claim 1, wherein manufacturing the first pixel electrode and the second pixel electrode includes:

depositing a first insulating layer film;

4. The method of manufacturing an array substrate according to claim 1, wherein manufacturing the first pixel electrode and the second pixel electrode includes:

annealing the first pixel electrode to crystallize the first pixel electrode;

depositing to form a second pixel electrode film layer;

5. The method of manufacturing an array substrate according to claim 1, wherein manufacturing the first pixel electrode and the second pixel electrode includes:

depositing to form a second pixel electrode film layer;

6. The method of manufacturing an array substrate according to claim 1, wherein manufacturing the first pixel electrode and the second pixel electrode includes:

depositing a pixel electrode film layer on the insulating flat layer;

7. The method for manufacturing an array substrate according to any one of claims 1 to 6, further comprising: and depositing a second insulating layer on one side of the pattern of the first pixel electrode and one side of the pattern of the second pixel electrode, which are away from the substrate.