KR100928491B1 - LCD and its manufacturing method - Google Patents

Abstract

It is possible to prevent open defects in the boundary regions (steps) between the data lines and the drain electrodes overlapping the gate lines and the gate electrodes, and to minimize signal distortion caused by the Cgd fluctuations by minimizing the overall Cgd fluctuations even when the gate electrodes are shifted. In order to provide a liquid crystal display device and a method of manufacturing the same, a liquid crystal display device for achieving the above object is arranged in one direction on the substrate, the gate line is provided with a bent formed on the inside and the protrusion formed on the outside; A gate electrode protruding from one side of the gate line and having a groove on one side; A gate insulating film formed on the entire surface of the substrate; A data line intersecting the gate line to define a pixel area, the data line overlapping a portion of an inner bend of the gate line; A source electrode protruding from the data line; A drain electrode having a predetermined distance from the source electrode and overlapping the groove of one side of the gate electrode and the protrusion of the gate line; An active layer formed under the data line, the source electrode and the drain electrode; And a pixel electrode formed in the pixel region.

Gate line, gate electrode, bend, protrusion, groove, Cgd

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is an enlarged plan view illustrating a unit pixel of a liquid crystal display according to the related art.

2 is an enlarged plan view illustrating a unit pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

40a: groove 40b: protrusion

41: gate line 42: data line

42a: source electrode 42b: drain electrode

42c: upper storage electrode 43: active layer

44a: first contact hole 44b: second contact hole

45: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and is particularly suitable for preventing the opening of the data line and the drain electrode in the boundary region of the data line and the gate line and the boundary region of the drain electrode and the gate electrode (step). A liquid crystal display device and a manufacturing method thereof.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways, such as a television for receiving and displaying broadcast signals, and a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display device in various parts as a general screen display device, the key to development is how much high definition images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel. The liquid crystal panel has a predetermined space, and includes an upper substrate, a lower substrate, and the upper and lower substrates. It is composed of a liquid crystal layer formed between the lower substrate.

Here, the lower substrate (TFT array substrate) includes a plurality of gate wirings arranged in one direction at a predetermined interval, a plurality of data wirings arranged at regular intervals in a direction perpendicular to the respective gate wirings, and the respective gate wirings. A plurality of pixel electrodes formed in a matrix form in each pixel region defined by intersections of the data lines and a plurality of thin film transistors which are switched by signals of the gate lines to transfer the signals of the data lines to the pixel electrodes. Is formed.

In the upper substrate (color filter substrate), a black matrix layer for blocking light except for the pixel region, an R, G, and B color filter layer for expressing color colors, and a common electrode for implementing an image are formed. do.

In addition, the upper substrate and the lower substrate thus formed have a predetermined space by a spacer for maintaining a cell gap, and are bonded by a sealant. And liquid crystal is formed in the space inside a seal material.

When manufacturing a liquid crystal display device having such a structure, instead of forming one liquid crystal panel on one substrate, a plurality of liquid crystal panels are simultaneously formed on one large substrate according to the size of the substrate and the size of the liquid crystal panel.                         

Hereinafter, a liquid crystal display according to the prior art will be described in more detail.

1 is an enlarged plan view illustrating a unit pixel of a liquid crystal display according to the related art.

In the liquid crystal display according to the related art, as shown in FIG. 1, gate lines 1 are arranged in parallel in one direction at a predetermined interval on a lower substrate (not shown), and in one direction from the gate lines 1. The gate electrode 1a is formed to protrude.

In this case, the storage lower electrode of the storage capacitor is integrally formed with the front gate line 1. That is, the front gate line 1 serves as a storage lower electrode.

In addition, a gate insulating film (not shown) is formed on the lower substrate including the gate line 1 and the gate electrode 1a, and a data line intersecting with the gate line 1 on the gate insulating film to define a pixel region. There is (2).

There is a source electrode 2a protruding from the data line 2, and a drain electrode 2b spaced apart from the source electrode 2a by a predetermined interval.

In this case, the source electrode 2a forms a '홈' shaped groove, and the drain electrode 2b is formed inside the '⊂' shaped groove spaced apart from the source electrode 2a by a predetermined distance, and the source electrode ( A '⊂' shaped channel region is defined between 2a) and the drain electrode 2b.

The active layer 3 is formed in a pattern on the gate insulating film.

In this case, the active layer 3 is formed to have a wider width under the data line 2, the source electrode 2a, and the drain electrode 2b, and is formed by stacking an amorphous silicon layer and an n + amorphous silicon layer. do.

The storage upper electrode 2c is formed in one region of the front gate line 1 serving as the storage lower electrode.

In addition, a protective film (not shown) having a first contact hole 4a and a second contact hole 4b formed in one region of the drain electrode 2b is formed on one surface of the drain electrode 2b.

The pixel electrode 5 is formed in the pixel area such that the drain electrode 2b is contacted through the first contact hole 4a and the storage upper electrode 2c is contacted through the second contact hole 4b.

The data line 2, the source electrode 2a, and the drain electrode 2b are manufactured by depositing a conductive film on a gate insulating film and then patterning the same by wet etching.

In the case where the gate electrode 1a is shifted, an area in which the gate line 1 and the data line 2 overlap with each other is changed, and thus a change in Cgd may occur, thereby causing a signal distortion problem.

When the data line, the source electrode, and the drain electrode are patterned by wet etching, the lengths of the boundary regions (stepped portions) of the gate line 1 and the data line 2 are shown in region A of FIG. 1. Since it is short (indicated by the arrow ↔), the data line 2 is eroded by the etching solution in the boundary region (step portion) overlapping with the gate line 1, so that disconnection defects are likely to occur.

Also, as shown in region B of FIG. 1, the length of the boundary region (stepped portion) between the gate electrode 1a and the drain electrode 2b (indicated by an arrow ↔) is short, so that the gate electrode 1a is provided. The drain electrode 2b is eroded by the etching solution in the boundary region (stepped portion) overlapping with each other, so that disconnection defects are likely to occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal suitable for preventing an open defect in a boundary region (step) of a data line and a drain electrode overlapping a gate line and a gate electrode. A display device and a method of manufacturing the same are provided.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can reduce the signal distortion caused by the Cgd variation by minimizing the overall Cgd variation even when the gate electrode is shifted.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a gate line arranged in one direction on a substrate and having a curved portion formed inwardly and a protrusion formed outwardly; A gate electrode protruding from one side of the gate line and having a groove on one side; A gate insulating film formed on the entire surface of the substrate; A data line intersecting the gate line to define a pixel area, the data line overlapping a portion of an inner bend of the gate line; A source electrode protruding from the data line; A drain electrode having a predetermined distance from the source electrode and overlapping the groove of one side of the gate electrode and the protrusion of the gate line; An active layer formed under the data line, the source electrode and the drain electrode; And a pixel electrode formed in the pixel region.

The groove on one side of the gate electrode crosses the lower side of the drain electrode.

The lengths of the left and right widths of the protrusions of the gate lines are the same as the left and right widths of the grooves on one side of the gate electrode.

The curved portion formed inwardly of the gate line and the protrusion formed outwardly and the groove of the gate electrode may further include a curved shape.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the method including: forming a gate line having one side arranged on one side of a substrate and having a curved portion formed inwardly and a protrusion formed outwardly; Forming a gate electrode protruding from one side of the gate line and having a groove on one side; Depositing a gate insulating film on the substrate including the gate line; Interposing the gate line to define a pixel area, and forming a data line to overlap a portion of the curved area of the gate line; Forming a source electrode protruding from the data line; Forming a drain electrode at regular intervals from the source electrode and overlapping the groove of one side of the gate electrode and the protrusion of the gate line; Forming an active layer under the data line, the source electrode and the drain electrode; And forming a pixel electrode in the pixel region.

The groove of one side of the gate electrode is formed to intersect the lower side of the drain electrode, and the length of the left and right widths of the protrusion of the gate line is formed to be equal to the left and right width of the groove of the one side of the gate electrode.

The curve formed inwardly of the gate line and the protrusion formed outwardly and the groove of the gate electrode are formed to be curved.

The data line is made of any one of a metal such as chromium (Cr), molybdenum (Mo), titanium, or tantalum, or a molybdenum alloy (Mo alloy) such as MoW, MoTa, or MoNo.

The pixel electrode is made of one of Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), and Indium-Tin-Zinc-Oxide (ITZO).

Hereinafter, a liquid crystal display and a manufacturing method thereof according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

The present invention not only prevents the defective opening of the data line at the intersection of the gate line and the data line, but also prevents the defective opening of the drain electrode at the intersection of the gate electrode and the drain electrode, and prevents flicker due to Cgd dispersion. The structure and method of changing the pattern shape of the gate electrode and the gate line to minimize the) is characterized.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described.

2 is an enlarged plan view illustrating a unit pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 2, the gate lines 41 are arranged in parallel in one direction at a predetermined interval on a transparent lower substrate (not shown), and the gate lines 41 are arranged in the same manner. ), The gate electrode 41a protrudes in one direction.

One region of the gate line 41 of the previous stage serves as a storage lower electrode of the storage capacitor.

A gate insulating film (not shown) is formed on the lower substrate including the gate line 41 and the gate electrode 41a, and an active layer 43 is patterned on the gate insulating film in a predetermined shape.

A data line 42 is formed on the gate insulating layer to intersect the gate line 41 to define a pixel area.

A source electrode 42a protrudes from the data line 42, and a drain electrode 42b is formed to be spaced apart from the source electrode 42a by a predetermined interval.

In this case, the source electrode 42a is formed to have a '⊂'-shaped groove, and the drain electrode 42b is formed to be spaced apart from the source electrode 42a by a predetermined interval inside the groove of the source electrode 42a. As a result, a '⊂' shaped channel region is defined between the source electrode 42a and the drain electrode 42b.

The active layer 43 has a wider width under the data line 42, the source electrode 42a, and the drain electrode 42b, and is formed by stacking an amorphous silicon layer and an n + amorphous silicon layer. do.

A groove 40a is formed on one side of the gate electrode 41a that crosses the lower side of the drain electrode 42b, and a protrusion portion is formed on one side of the gate line 41 so as to overlap one region of the drain electrode 42b. 40b) is formed.

The protrusion 40b of the gate line 41 is formed to compensate for the reduction in the area overlapping with the drain electrode 42b by the groove 40a of the gate electrode 41a that is shifted up and down.

In order to compensate for the change of the Cgs due to the vertical shift as described above, only the lengths of the left and right widths of the protrusions 40b of the gate line 41 are the left and right width lengths of the grooves 40a on one side of the gate electrode 41a. The height of the protrusion 40b may be formed at a level not exceeding the drain electrode 42b.

Further, in the lower boundary region (stepped portion) where the gate line 41 and the data line 42 intersect, the gate line 41 is formed to have an inward curvature.

In this case, the groove 40a on one side of the gate electrode 41a and the bend and the protrusion 40b of the gate line 41 may be curved.

As described above, the bend of the portion where the gate line 41 and the data line 42 cross each other, and the groove 40b of the portion where the gate electrode 41a and the drain electrode 42b cross each other is not only a vertical component but also a horizontal component. It is inserted.

In this configuration, as can be seen when comparing the 'C' region and the 'D' region of FIG. 2 with the 'A' region and the 'B' region of FIG. 1, respectively, the gate line 41 and the data of the present invention. The length of the lower boundary region where the lines 42 cross and the length of the boundary region where the gate electrode 41a and the drain electrode 42b cross each other are increased.                     

In addition, even if the gate electrode 41a is shifted left and right, the area where the gate line 41 overlaps the data line 42 is compensated to some extent by the bending of the lower boundary region (stepped portion).

In addition, the protrusion 40b formed at one side of the gate line 41 is formed by the groove 40a formed at the intersection of the lower portion of the gate electrode 41a and the drain electrode 42b as described above. Not only can the compensation for the overlapping area of the drain electrode 42b be reduced, but also the flicker phenomenon due to the Cgd deviation can be improved by eliminating the variation in the overlap area due to the overlay variation.

 In addition, a storage upper electrode 42c is formed on an upper portion of the previous gate line 41 serving as the storage lower electrode.

A protective film (not shown) having a first contact hole 44a in one region of the drain electrode 42b and a second contact hole 44b in one region of the storage upper electrode 42c is formed on the entire surface of the lower substrate. It is.

The pixel electrode 45 is formed in the pixel area to be in contact with the drain electrode 42b through the first contact hole 44a and to contact the storage upper electrode 42c through the second contact hole 44b.

At this time, the data line 42 is made of any one of a metal such as chromium (Cr), molybdenum (Mo), titanium or tantalum, or a molybdenum alloy (Mo alloy) such as MoW, MoTa, or MoNo.

The protective layer may be an inorganic insulator such as silicon nitride (Si 3 N 4) or silicon oxide (SiO 2), or an acrylic organic compound, Teflon, BCB (benzocyclobuten), cytotope, or perfluorocyclobutane (PFCB). It consists of at least one among organic substances, such as these.

The pixel electrode 45 is made of one of Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), and Indium-Tin-Zinc-Oxide (ITZO).

Next, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention having the above configuration will be described.

3A to 3C are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, one of conductive metal films such as chromium, aluminum, aluminum alloy (AlNd), tantalum, and molybdenum (Mo) is deposited on a lower substrate (not shown), and then photographed using a first mask. By etching, the gate line 41 arranged in one direction and the gate electrode 41a protruding from one side of the gate line 41 are formed.

The gate electrode 41a is formed with a groove 40a on one side, and the groove 40a is formed at a portion to cross the lower side of the drain electrode to be formed later.

The gate line 41 not only forms a lower boundary region (step portion) to be intersected with a data line to be formed later, but also forms a protrusion 40b to overlap a predetermined region with a drain electrode to be formed later. .

The lengths of the left and right widths of the protrusions 40b of the gate line 41 are equal to the left and right widths of the grooves 40a of one side of the gate electrode 41a.                     

Since the curved portion of the lower portion of the gate line 41 and the groove 40a on one side of the gate electrode 41a are mixed vertically and horizontally, the length of the boundary region between the data line and the drain electrode is increased. It is possible to reduce the possibility that the data line and the drain electrode to be eroded and opened by the etching solution in the boundary region (step portion) overlapping the gate line 41 and the gate electrode 41a.

In this case, the curved lines, the protrusions 40b, and the grooves 40a of the gate line 41 and the gate electrode 41a may be formed to have a curved shape.

The conductive metal film is formed of two layers, a lower layer made of aluminum or aluminum-neodymium (AlNd) alloy and an upper layer made of molybdenum (Mo), or a lower layer made of chromium and an upper layer made of aluminum-neodymium alloy. It can also be formed from a double layer of.

Thereafter, a gate insulating layer (not shown) is formed on the entire lower substrate including the gate line 41.

Subsequently, as shown in FIG. 3B, an amorphous silicon layer for forming an active layer (not shown) and an n + amorphous silicon layer (not shown) are sequentially deposited on the gate insulating film, and then chromium (Cr) and molybdenum are deposited on the entire lower substrate. A conductive film made of any one of a metal such as (Mo), titanium or tantalum, or a molybdenum alloy such as MoW, MoTa, or MoNo is deposited.

Next, although not shown in the drawing, after the conductive film is wet etched using the second mask to form the conductive film pattern, an amorphous silicon layer (not shown) and an n + amorphous silicon layer are formed using the conductive film pattern as a mask. Dry etch.

In the second mask, a portion where the channel region is to be formed is patterned with halftones.

Thereafter, the second mask over the channel region is removed, and the conductive layer pattern is etched using the mask to form the data line 42, the source electrode 42a, the drain electrode 42b, and the storage upper electrode 42c. do.

Then, the ohmic contact layer (not shown) and the active layer 43 are removed by ashing the n + amorphous silicon layer on the amorphous silicon layer by using the data line 42, the source electrode 42a, and the drain electrode 42b as a mask. Form.

In this case, the source electrode 42a is formed to overlap the upper portion of the gate electrode 41a to have a '⊂'-shaped groove, and the drain electrode 42b is overlapped to an upper portion of the gate electrode 41a to' '. The groove is formed to be spaced apart from the source electrode 42a by a predetermined interval inside the groove.

By the above process, the active channel existing between the source electrode 42a and the drain electrode 42b has a '⊂' shape, and the data line 42, the source electrode 42a, and the drain electrode 42b have an active layer. It has a narrower width than (43).

Next, although not shown in the drawings, a protective film is deposited on the lower substrate.

In this case, the protective layer may be an inorganic insulating material such as silicon nitride (Si 3 N 4) or silicon oxide (SiO 2), or an acrylic organic compound, Teflon, BCB (benzocyclobuten), Cytop, or PFCB (Perfluorocyclobutane). At least one of the organic materials may be selected and formed.

Then, a photosensitive film (not shown) is coated on the protective film, and the photosensitive film is selectively patterned by an exposure and development process.

In this case, the photoresist layer is patterned to expose the protective layer on the drain electrode 42b and the upper storage upper electrode 42c of the front gate line 41.

Subsequently, as shown in FIG. 3C, the protective layer is etched using the third mask (patterned photoresist) as a mask to form a first contact hole 44a in one region of the drain electrode 42b, and the front gate line 41. A second contact hole 44b is formed in one region of the upper storage upper electrode 42c.

Next, after the transparent electrode is deposited on the lower substrate, the pixel electrode 45 is formed in the pixel region including the first contact hole 44a and the second contact hole 44b by a photolithography process using a fourth mask.

In this case, the pixel electrode 45 is made of one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin oxide (ITZO).

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be defined by the claims.

The liquid crystal display of the present invention and a method of manufacturing the same have the following effects.

First, since a groove is formed on one side of the gate electrode that crosses the lower side of the drain electrode, the length at the boundary with the drain electrode is increased, thereby preventing the problem of opening the drain electrode at the boundary.

Second, an area overlapping the drain electrode can be compensated by forming a protrusion in the gate line to overlap the drain electrode.

Third, since the lower boundary portion of the gate line overlapping the data line has a curvature, the length at the boundary portion is increased, thereby reducing the problem of opening the data line at the boundary portion.

Fourth, since the protrusion may be formed on the gate line to compensate for the Cgd fluctuation, the signal distortion caused by the Cgd fluctuation may be improved.

Claims (10)

A gate line arranged in one direction on the substrate and having a curved portion formed inwardly and a protrusion formed outwardly; A gate electrode protruding from one side of the gate line and having a groove on one side; A gate insulating film formed on the entire surface of the substrate; A data line intersecting the gate line to define a pixel area, the data line overlapping a portion of an inner bend of the gate line; A source electrode protruding from the data line; A drain electrode having a predetermined distance from the source electrode and overlapping the groove of one side of the gate electrode and the protrusion of the gate line; An active layer formed under the data line, the source electrode and the drain electrode; And a pixel electrode formed in the pixel region. The method of claim 1, And a groove of one side of the gate electrode intersects a lower side of the drain electrode. The method of claim 1, The left and right widths of the protrusions of the gate line are the same as the left and right widths of the grooves on one side of the gate electrode. The method of claim 1, And a curved portion formed inwardly of the gate line, a protrusion formed outwardly, and a groove of the gate electrode. Forming a gate line arranged in one direction on the substrate and having a curvature formed inwardly and a protrusion formed outwardly; Forming a gate electrode protruding from one side of the gate line and having a groove on one side; Depositing a gate insulating film on the substrate including the gate line; Interposing the gate line to define a pixel area, and forming a data line to overlap a portion of the curved area of the gate line; Forming a source electrode protruding from the data line; Forming a drain electrode at regular intervals from the source electrode and overlapping the groove of one side of the gate electrode and the protrusion of the gate line; Forming an active layer under the data line, the source electrode and the drain electrode; And forming a pixel electrode in the pixel region. The method of claim 5, wherein The groove of one side of the gate electrode is formed to cross the lower side of the drain electrode. The method of claim 5, wherein The left and right width depths of the protrusions of the gate line are formed to be the same as the left and right widths of the grooves on one side of the gate electrode. The method of claim 5, wherein And the curved portion formed inwardly of the gate line and the protruding portion formed outwardly and the groove of the gate electrode are curved to form a curved line. The method of claim 5, wherein The data line is made of a metal such as chromium (Cr), molybdenum (Mo), titanium or tantalum, or a molybdenum alloy (Mo alloy) such as MoW, MoTa or MoNo. Way. The method of claim 5, wherein The pixel electrode may be made of one of Indium-Tin-Oxide (ITO), Indium-Zinc-Oxide (IZO), and Indium-Tin-Zinc-Oxide (ITZO).

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