CN114924437A

CN114924437A - Array substrate, preparation method thereof and display device

Info

Publication number: CN114924437A
Application number: CN202210549738.8A
Authority: CN
Inventors: 谢蒂旎; 王久石; 姚舜禹; 王利波; 吴仲远; 董学; 于静
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2022-05-20
Filing date: 2022-05-20
Publication date: 2022-08-19
Anticipated expiration: 2042-05-20
Also published as: WO2023221767A1; CN114924437B; WO2023221767A9

Abstract

The embodiment of the present disclosure provides a method for manufacturing an array substrate, including: preparing a pixel driving circuit on a substrate; preparing an insulating flat layer on the substrate after the steps are completed; preparing a plurality of pixel electrodes on the substrate on which the above steps are completed; the pixel electrodes are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer; the plurality of pixel electrodes are arranged in an array; along the row direction and/or the column direction of the array, the spacing distance between any two adjacent pixel electrodes is smaller than or equal to a set value; the 2n-1 th pixel electrode is a first pixel electrode; the 2 nth pixel electrode is a second pixel electrode; the preparing the pixel electrode includes: the first pixel electrode is prepared through a first composition process; the second pixel electrode is prepared through a second composition process; wherein n is a positive integer.

Description

Array substrate, preparation method thereof and display device

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display device.

Background

With the development of display technology, high-resolution (PPI) liquid crystal display products are increasingly popular with people because the picture display is finer and the display effect is better.

Disclosure of Invention

In one aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate, including:

preparing a pixel driving circuit on a substrate;

preparing an insulating flat layer on the substrate after the steps are completed;

preparing a plurality of pixel electrodes on the substrate on which the above steps are completed; the pixel electrodes are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer;

the plurality of pixel electrodes are arranged in an array; along the row direction and/or the column direction of the array, the spacing distance between any two adjacent pixel electrodes is smaller than or equal to a set value; the 2n-1 th pixel electrode is a first pixel electrode; the 2 nth pixel electrode is a second pixel electrode;

the preparing the pixel electrode includes: the first pixel electrode is prepared through a first composition process; the second pixel electrode is prepared through a second composition process; wherein n is a positive integer.

In some embodiments, preparing the first pixel electrode and the second pixel electrode includes:

forming a graph of the first pixel electrode on the insulating flat layer by adopting a composition process; depositing a first insulating layer film;

forming a pattern of the second pixel electrode on the first insulating layer film by adopting a composition process;

and etching to form a pattern of the first insulating layer by taking the pattern of the second pixel electrode as a mask.

forming a graph of the first pixel electrode on the insulating flat layer by adopting a composition process;

depositing a first insulating layer film;

thinning a local area of the first insulating layer film by an etching process; the local area is an area of the first insulating layer film except for the pattern covering the first pixel electrode;

forming a pattern of the second pixel electrode in the area where the first insulating layer film is thinned by adopting a composition process;

annealing the first pixel electrode to crystallize the first pixel electrode;

depositing to form a second pixel electrode film layer;

and forming a pattern of the second pixel electrode by adopting a patterning process.

forming a graph of the first pixel electrode on the insulation flat layer by adopting a composition process, and simultaneously reserving a first photoresist graph on the graph of the first pixel electrode; the orthographic projection of the first photoresist pattern on the substrate only covers the pattern of the first pixel electrode;

depositing to form a second pixel electrode film layer;

forming a second photoresist pattern by adopting an exposure process; the orthographic projection of the second photoresist pattern on the substrate only covers the pattern of the second pixel electrode;

etching and removing the second pixel electrode film layer in the area outside the coverage area of the second photoresist pattern to form a pattern of the second pixel electrode;

and developing to remove the first photoresist pattern and the second photoresist pattern.

depositing a pixel electrode film layer on the insulating flat layer;

forming a positive photoresist pattern on the pixel electrode film layer by adopting an exposure process; the positive photoresist pattern only covers the pattern of the first pixel electrode in the orthographic projection on the substrate;

forming a negative photoresist pattern on the pixel electrode film layer by adopting an exposure process; the positive projection of the negative photoresist pattern on the substrate only covers the pattern of the second pixel electrode;

etching to form a pattern of the first pixel electrode and a pattern of the second pixel electrode;

and developing and removing the positive photoresist pattern and the negative photoresist pattern.

In some embodiments, further comprising: and depositing and forming a second insulating layer on one side of the pattern of the first pixel electrode and the pattern of the second pixel electrode, which faces away from the substrate.

In a second aspect, an embodiment of the present disclosure further provides an array substrate, including: a substrate;

a pixel driving circuit on the substrate;

the insulating flat layer is positioned on one side, away from the substrate, of the pixel driving circuit; the surface of one side of the insulating flat layer, which is far away from the substrate, is a horizontal surface;

the pixel electrodes are positioned on one side, away from the substrate, of the insulating flat layer and are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer;

the plurality of pixel electrodes are arranged in an array;

the spacing distance between any two adjacent pixel electrodes is less than or equal to 2 μm along the row direction and/or the column direction of the array; any two adjacent pixel electrodes are respectively a first pixel electrode and a second pixel electrode; the absolute value range of the difference between the distance between the surface of one side of the first pixel electrode, which is far away from the substrate, and the substrate and the distance between the surface of one side of the second pixel electrode, which is far away from the substrate, and the substrate is 0-1500 angstroms.

In some embodiments, the pixel electrode includes a first sub-portion extending in a row direction of the array and a second sub-portion extending in a column direction of the array, and the first sub-portion and the second sub-portion are connected;

the extension length of the first sub-portion is smaller than that of the second sub-portion;

the orthographic projection of the via hole in the insulating flat layer on the substrate is positioned in the orthographic projection of the first sub-portion on the substrate, and the first sub-portion is connected with the pixel driving circuit through the via hole in the insulating flat layer.

In some embodiments, the second sub-portion of the first pixel electrode is equal in thickness to the second sub-portion of the second pixel electrode;

the first pixel electrode is in contact with the horizontal surface of the insulating flat layer;

a first insulating layer is arranged between the second pixel electrode and the horizontal surface of the insulating flat layer;

an orthographic projection of the first insulating layer on the substrate is coincided with an orthographic projection of the second pixel electrode on the substrate;

or the second pixel electrode is in contact with the horizontal surface of the insulating flat layer.

In some embodiments, a thickness of the second sub-portion of the first pixel electrode is greater than a thickness of the second sub-portion of the second pixel electrode;

a first insulating layer is arranged between the second pixel electrode and the horizontal surface of the insulating flat layer; an orthographic projection of the first insulating layer on the substrate is coincided with an orthographic projection of the second pixel electrode on the substrate;

the thickness of the second sub-portion of the first pixel electrode is equal to the sum of the thicknesses of the second sub-portion of the second pixel electrode and the first insulating layer.

In some embodiments, the display device further comprises a second insulating layer located on a side of the pixel electrode facing away from the substrate, and an orthographic projection of the second insulating layer on the substrate covers the whole substrate.

In a third aspect, an embodiment of the present disclosure further provides a display device, including the array substrate.

Drawings

The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a schematic top view illustrating an arrangement of pixel electrodes in a display panel according to the prior art.

Fig. 2 is a schematic top view of the structure of the array substrate according to the embodiment of the disclosure.

FIG. 3 is a cross-sectional view of a structure taken along line AA' of FIG. 2.

FIG. 4 is a cross-sectional view of an alternative embodiment taken along line AA' of FIG. 2.

FIG. 5 is a cross-sectional view of an alternative embodiment of the structure taken along line AA' of FIG. 2.

FIG. 6 is a cross-sectional view of an alternative embodiment of the structure taken along line AA' of FIG. 2.

Fig. 7 is a cross-sectional view of a method for manufacturing the array substrate of fig. 3-5.

Fig. 8 is a structural top view flowchart of the method for manufacturing the array substrate of fig. 7.

Fig. 9 is a cross-sectional view of another method for fabricating the array substrate of fig. 3.

Fig. 10 is a cross-sectional view of a method for manufacturing the array substrate of fig. 6.

Fig. 11 is a sectional view of the array substrate of fig. 6 according to another exemplary embodiment.

Fig. 12 is a flow chart showing a cross-sectional structure of another method for manufacturing the array substrate of fig. 6.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the embodiments of the present disclosure, the array substrate, the manufacturing method thereof, and the display device provided in the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and the detailed description.

The embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The disclosed embodiments are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on a manufacturing process. Thus, the regions illustrated in the figures have schematic properties, and the shapes of the regions shown in the figures illustrate specific shapes of regions, but are not intended to be limiting.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

For the same size of liquid crystal display panel, the high resolution pixel arrangement compresses the distance between the pixel electrodes. In the disclosed technology, the pixel electrode is prepared by depositing a single layer of transparent conductive film (such as an ITO film) at a time, and then patterning the pixel electrode through the steps of exposure, development, and wet etching. Due to the limitation of the exposure accuracy of the exposure equipment (at present, the exposure accuracy of the exposure equipment is in a micron order), when the distance between adjacent pixel electrodes is small (for example, less than 1 μm or 2 μm), it is difficult to completely expose the photoresist to form a pattern, for example, the photoresist can only be partially exposed to form a pattern, and adhesion of the photoresist pattern can occur at certain small pattern gaps (that is, the pattern and the pattern cannot be completely exposed), so that the uniformity of the pixel electrode pattern in the display panel cannot be ensured.

Referring to fig. 1, a schematic top view of the arrangement of pixel electrodes in the display panel in the prior art is shown; in a high-resolution display panel, the gaps between adjacent pixel electrodes 3 are small, and the small gap patterns between the pixel electrodes 3 need to be manufactured when the patterns of the pixel electrodes 3 are prepared; if the gap width a is less than or equal to 0.9 μm; in the disclosed technology, in the process for preparing the pattern of the pixel electrode 3, when the gap width a between adjacent pixel electrodes 3 is 0.9 μm, the gap width between adjacent photoresist patterns corresponding to adjacent pixel electrode 3 patterns formed in the previous step needs to be 0.4 μm, and the formation of the pattern of the pixel electrode 3 by wet etching under such a small gap between adjacent photoresist patterns is likely to cause etching residue of the pixel electrode film layer at the gap between the photoresist patterns.

When the process for preparing the pixel electrode patterns adopts digital exposure equipment, the gap width value between adjacent photoresist patterns is input into the digital exposure equipment to be 0.4 mu m, and meanwhile, an empirical value of 0.5 is subtracted on the basis of 0.4 mu m, so that the gap width between adjacent pixel electrodes can be finally obtained theoretically; however, the input value of the digital exposure apparatus becomes-0.1 at this time, and thus the digital exposure apparatus cannot achieve the gap width between the adjacent photoresist patterns of 0.4 μm at all, and thus cannot achieve the preparation of the gap width between the adjacent pixel electrodes of 0.9 μm at all.

In order to solve the above problems in the prior art, in a first aspect, an embodiment of the present disclosure provides an array substrate, referring to fig. 2 and fig. 3, where fig. 2 is a schematic top view of a structure of the array substrate in the embodiment of the present disclosure; FIG. 3 is a cross-sectional view of a structure taken along line AA' of FIG. 2; wherein, include: a substrate 1; a pixel driving circuit 2 on the substrate 1; the insulating flat layer 4 is positioned on one side, away from the substrate 1, of the pixel driving circuit 2; the surface of one side of the insulating flat layer 4, which is far away from the substrate 1, is a horizontal surface; the pixel electrodes 3 are positioned on one side, away from the substrate 1, of the insulating flat layer 4 and are respectively connected with the pixel driving circuit 2 through via holes 40 formed in the insulating flat layer 4; the plurality of pixel electrodes 3 are arranged in an array; along the row direction X and/or the column direction Y of the array, the spacing distance b between any two adjacent pixel electrodes 3 is less than or equal to a set value; any two adjacent pixel electrodes 3 are a first pixel electrode 31 and a second pixel electrode 32 respectively; the absolute value range of the difference between the distance between the surface of the first pixel electrode 31 facing away from the substrate 1 and the distance between the surface of the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is 0-1500 angstroms; the set value was 2 μm.

In some embodiments, the set value is 0.9 μm. In some embodiments, the set value is 1 μm. In some embodiments, the set value is 1.2 μm.

In this embodiment, the distance b between the first pixel electrode 31 and the second pixel electrode 32 in the row direction X of the array is smaller than a set value. For example: in the present embodiment, the spacing distance b between the first pixel electrode 31 and the second pixel electrode 32 is 0.9 μm. The distance between the surface of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is h1, and the distance between the surface of the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is h2, then 0 ≦ h1-h2 ≦ 1500 angstroms.

The array substrate provided in this embodiment is applied to a TN (Twisted Nematic) liquid crystal display panel, that is, the array substrate and the cell alignment substrate form a gap therebetween, and the gap is filled with liquid crystal. The whole surface common electrode is arranged on the opposite box substrate, and an electric field capable of deflecting liquid crystals is formed between the common electrode and the pixel electrode on the array substrate. And a backlight source is arranged on one side of the array substrate, which deviates from the opposite box substrate, and the backlight source provides backlight to realize the display of the whole liquid crystal display panel after passing through the pixel electrode, the liquid crystal layer and the common electrode.

In some embodiments, referring to fig. 3, the pixel driving circuit 2 includes a transistor 20, an active layer 201, a gate 202, a source 203, and a drain 204 of the transistor 20 are disposed on the substrate 1, the source 203 and the drain 204 are located on the same film, and the active layer 201, the gate 202, and the source 203 are sequentially distributed away from the substrate 1; a gate insulating layer 205 is further arranged between the gate 202 and the active layer 201; the source electrode 203 and the drain electrode 204 are arranged at the same layer, and an intermediate dielectric layer 206 is arranged between the gate electrode 202 and the source electrode 203 and the drain electrode 204; the insulating flat layer 4 is located on the source electrode 203 and the drain electrode 204, the insulating flat layer 4 can fill and level the whole surface of the substrate 1 where the source electrode 203 and the drain electrode 204 are located, and the surface of one side of the insulating flat layer 4, which is far away from the substrate 1, is a horizontal surface, so that a pattern of the pixel electrode 3 can be formed on the horizontal surface later. In addition, a light-shielding metal layer 207 is further disposed on one side of the active layer 201 close to the substrate 1, and a buffer layer 208 is further disposed between the light-shielding metal layer 207 and the active layer 201; the light-shielding metal layer 207 can shield light irradiated onto the active layer 201, thereby ensuring that the switching performance of the transistor 20 is not affected by light.

In some embodiments, referring to fig. 2, the pixel electrode 3 includes a first sub-portion 301 and a second sub-portion 302, the first sub-portion 301 extends along a row direction X of the array, the second sub-portion 302 extends along a column direction Y of the array, and the first sub-portion 301 and the second sub-portion 302 are connected; the extension of the first sub-portion 301 is smaller than that of the second sub-portion 302; the orthographic projection of the via 40 in the insulating flat layer 4 on the substrate 1 is positioned in the orthographic projection of the first sub-part 301 on the substrate 1, and the first sub-part 301 is connected with the pixel driving circuit 2 through the via 40 in the insulating flat layer 4. Wherein the first sub-section 301 is connected to the drain 204 of the transistor 20 in the pixel driving circuit 2 through the via 40 in the insulating flat layer 4.

In some embodiments, referring to fig. 2, the second sub-portions 302 of the first pixel electrodes 31 and the second sub-portions 302 of the second pixel electrodes 32 are parallel to each other and are sequentially arranged along the row direction X of the array; the first sub-portion 301 of the first pixel electrode 31 and the first sub-portion 301 of the second pixel electrode 32 are parallel to each other and are sequentially arranged along the column direction Y of the array. So set up, enable the arrangement of pixel electrode 3 on the array substrate more densely to improve the resolution ratio of the display panel who adopts this array substrate.

In some embodiments, the orthographic shape of the first sub-portion 301 on the substrate 1 is rectangular, and the orthographic shape of the second sub-portion 302 on the substrate 1 is rectangular.

In some embodiments, referring to fig. 2, the orthographic projection of the pixel drive circuits on the substrate 1 is located at a spacing region between adjacent pixel electrodes 3 in the column direction Y of the array; the orthographic projection of the transistor 20 on the substrate 1 partially overlaps with the first sub-section 301 of the pixel electrode 3; the orthographic projection of the pixel driving circuit on the substrate 1 does not overlap with the second sub-portion 302 of the pixel electrode 3, thereby ensuring that backlight light can normally transmit through the pixel electrode 3 for display.

In some embodiments, referring to fig. 2, the array substrate further includes a plurality of gate lines 7 and a plurality of data lines 8, the gate lines 7 extend along a row direction X of the array, and the plurality of gate lines 7 are respectively located between two adjacent rows of pixel electrodes 3; the orthographic projection of the gate line 7 on the substrate 1 may partially overlap the first sub-section 301 of the pixel electrode 3; the orthogonal projection of the gate line 7 on the substrate 1 does not overlap the second sub-section 302 of the pixel electrode 3. The data lines 8 extend along the column direction Y of the array, and the data lines 8 are respectively located between two adjacent columns of pixel electrodes 3; the orthographic projection of the data line 8 on the substrate 1 may partially overlap or not overlap with the second sub-portion 302 of the pixel electrode 3. For example: when the width of the data line 8 in the array row direction X is 1.2 μm, since the spacing distance between two adjacent pixel electrodes 3 in the row direction X is 0.9 μm, the orthographic projection of the data line 8 on the substrate 1 partially overlaps the second sub-portion 302 of the pixel electrode 3.

In some embodiments, referring to fig. 3, the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 have the same thickness; the first pixel electrode 31 is in contact with the horizontal surface of the insulating planarization layer 4; a first insulating layer 5 is further provided between the second pixel electrode 32 and the horizontal surface of the insulating flat layer 4; an orthogonal projection of the first insulating layer 5 on the substrate 1 coincides with an orthogonal projection of the second pixel electrode 32 on the substrate 1.

In some embodiments, referring to fig. 3, the insulating planarization layer 4 includes an organic insulating layer. The thickness of the organic insulating layer can be made thicker in order to facilitate the formation of a horizontal surface at the side thereof facing away from the substrate 1.

In some embodiments, the material of the organic insulating layer may be PI (polyimide), PC (polycarbonate), PMMA (polymethyl methacrylate), or the like.

In some embodiments, the thickness of the second sub-portion of the first pixel electrode 31 is in a range of 400 to 1200 angstroms; the thickness of the second sub-portion of the second pixel electrode 32 is 400-1200 angstroms. In some embodiments, the thickness of the first insulating layer 5 is in a range of 50 to 800 angstroms.

In some embodiments, the thicknesses of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 may be 800 angstroms, respectively; accordingly, the thickness of the first insulating layer 5 may be 50 angstroms or 800 angstroms. In some embodiments, the thicknesses of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 may be 400 angstroms, respectively; accordingly, the thickness of the first insulating layer 5 may be 600 angstroms.

In some embodiments, the material of the first pixel electrode 31 and the second pixel electrode 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide. In some embodiments, the material of the first insulating layer 5 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

In some embodiments, referring to FIG. 4, a cross-sectional view of another structure taken along line AA' of FIG. 2; the insulating planarization layer 4 includes an organic insulating layer 41 and an inorganic insulating layer 42, and the organic insulating layer 41 and the inorganic insulating layer 42 are stacked in order away from the substrate 1. The inorganic insulating layer 42 is provided to improve or prevent damage to the organic insulating layer 41 when the pattern of the first insulating layer 5 is formed by etching.

In some embodiments, the material of the inorganic insulating layer 42 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

In some embodiments, referring to FIG. 5, a cross-sectional view of another structure taken along line AA' of FIG. 2; the thickness of the second sub-section of the first pixel electrode 31 is greater than the thickness of the second sub-section of the second pixel electrode 32; the first pixel electrode 31 is in contact with the horizontal surface of the insulating flat layer 4; a first insulating layer 5 is further arranged between the second pixel electrode 32 and the horizontal surface of the insulating flat layer 4; the orthographic projection of the first insulating layer 5 on the substrate 1 is superposed with the orthographic projection of the second pixel electrode 32 on the substrate 1; the thickness of the second sub-section of the first pixel electrode 31 is equal to the sum of the thicknesses of the second sub-section of the second pixel electrode 32 and the first insulating layer 5.

The first pixel electrode 31 and the second pixel electrode 32 respectively form an electric field with a whole common electrode arranged on the opposite box substrate side, and the arrangement enables one side surface of the first pixel electrode 31 departing from the substrate 1 to be flush with one side surface of the second pixel electrode 32 departing from the substrate 1, so that the display brightness of the sub-pixels adopting the first pixel electrode 31 and the sub-pixels adopting the second pixel electrode 32 is the same when gray scale signals with the same size are displayed, display stripes (namely, the gray scale mura phenomenon is improved or avoided) are improved or avoided, and the display effect of the display panel adopting the array substrate is improved.

In some embodiments, referring to fig. 5, the thickness of the second sub-portion of the first pixel electrode 31 is 1200 angstroms; the thickness of the second sub-portion of the second pixel electrode 32 is 400 angstroms; the thickness of the first insulating layer 5 was 800 angstroms.

In some embodiments, referring to FIG. 6, a cross-sectional view of the structure taken along line AA' of FIG. 2; the second sub-section of the first pixel electrode 31 and the second sub-section of the second pixel electrode 32 have the same thickness; the first pixel electrode 31 is in contact with the horizontal surface of the insulating planarization layer 4; the second pixel electrode 32 is in contact with the horizontal surface of the insulating planarization layer 4.

In some embodiments, the material of the first pixel electrode 31 includes any one of crystallized indium tin oxide, crystallized indium zinc oxide, and crystallized indium gallium zinc oxide; the material of the second pixel electrode 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide.

In some embodiments, the material of the first pixel electrode 31 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide; the material of the second pixel electrode 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide. The first pixel electrode 31 and the second pixel electrode 32 are made of the same material.

In some embodiments, referring to fig. 3 to 6, the array substrate further includes a second insulating layer 6 located on a side of the pixel electrode 3 facing away from the substrate 1, and an orthographic projection of the second insulating layer 6 on the substrate 1 covers the entire substrate 1. The second insulating layer 6 is provided to facilitate subsequent formation of an alignment film, a spacer, and the like thereon.

In some embodiments, the second insulating layer 6 material comprises any one of silicon nitride, silicon oxide, and silicon oxynitride.

In some embodiments, the second insulating layer 6 has a thickness in the range of 800 to 2000 angstroms.

In some embodiments, referring to fig. 3, when the insulating planarization layer 4 only includes an organic insulating layer, when the pattern of the first insulating layer 5 is formed by etching, an area of the insulating planarization layer 4 not covered by the pixel electrode 3 is etched, so that the second insulating layer 6 is partially penetrated into the insulating planarization layer 4 in the area of the insulating planarization layer 4 not covered by the pixel electrode 3.

Based on the above structure of the array substrate, in a second aspect, an embodiment of the present disclosure further provides a method for manufacturing the array substrate, where the method includes: step S01: a pixel driving circuit is fabricated on a substrate.

Step S02: and preparing an insulating flat layer on the substrate after the steps are finished.

Step S03: and preparing a plurality of pixel electrodes on the substrate after the steps are completed.

The pixel electrodes are respectively connected with the pixel driving circuit through via holes formed in the insulating flat layer; the plurality of pixel electrodes are arranged in an array; along the row direction and/or the column direction of the array, the spacing distance between any two adjacent pixel electrodes is smaller than or equal to a set value; the 2n-1 th pixel electrode is a first pixel electrode; the 2 nth pixel electrode is a second pixel electrode; the preparing of the pixel electrode includes: the first pixel electrode is prepared through a first composition process; the second pixel electrode is prepared through a second composition process; wherein n is a positive integer.

In this example, the set value is 2 μm. Preparing a first pixel electrode by a first patterning process along a row direction and/or a column direction of the array; compared with the scheme that all the pixel electrodes are prepared through the primary composition process in the prior art, the method has the advantages that the ultra-small gap between the adjacent pixel electrodes can be prepared under the exposure precision of the existing exposure equipment, so that the accurate pattern of the pixel electrodes is formed, and the uniformity of the pattern of the pixel electrodes in the array substrate is ensured.

In some embodiments, in a structural cross-sectional view subsequent to the array substrate manufacturing method step, only the manufacturing processes of the first pixel electrode, the second pixel electrode, the first insulating layer and the second insulating layer on the insulating planarization layer are shown, the structure of the pixel driving circuit and the manufacturing steps are not shown in the structural cross-sectional view, and the pixel driving circuit may adopt the pixel driving circuit structure in fig. 3. Referring to fig. 7, a cross-sectional view of a method for manufacturing the array substrate of fig. 3-5 is shown; FIG. 8 is a top view of the structure of the method for fabricating the array substrate of FIG. 7; here, preparing the first pixel electrode 31 and the second pixel electrode 32 over the insulating planarization layer 4 includes: step S101: forming a pattern of the first pixel electrode 31 on the insulating flat layer 4 by using a patterning process; a first insulating layer film 9 is deposited.

In this step, a pattern of the first pixel electrode 31 is formed by sputtering deposition of an indium tin oxide film layer, coating of a photoresist, exposure, development, and wet etching processes. The first insulating layer film 9 of a silicon nitride material is deposited by chemical vapor deposition.

Step S102: a pattern of the second pixel electrode 32 is formed on the first insulating layer film 9 using a patterning process.

In this step, a pattern of the second pixel electrode 32 is formed by sputtering deposition of an indium tin oxide film layer, coating of a photoresist, exposure, development, and wet etching processes.

Step S103: the pattern of the first insulating layer 5 is formed by etching using the pattern of the second pixel electrode 32 as a mask.

In this step, a pattern of the first insulating layer 5 is formed by etching through a dry etching process, the dry etching process has a risk of damaging a region of the insulating flat layer 4 of the organic insulating material, which is not covered by the first pixel electrode 31 and the second pixel electrode 32, and if the dry etching process damages the insulating flat layer 4 of the organic insulating material, the slope angles of the edge end surfaces of the second pixel electrode 32 and the first insulating layer 5 are increased, and the slope angles are steep.

Step S104: a second insulating layer 6 is deposited on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 facing away from the substrate 1.

In this step, the second insulating layer 6 is formed by chemical vapor deposition.

In some embodiments, when the array substrate in fig. 3 is prepared, the thickness of each of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 is 800 angstroms; the thickness of the first insulating layer 5 was 800 angstroms. The step difference between the first pixel electrode 31 and the second pixel electrode 32 is high, and the etching of the first insulating layer 5 has a large risk of damaging the insulating flat layer 4, and if the etching of the first insulating layer 5 causes a large damage to the insulating flat layer 4, the edge end face of the second pixel electrode 32 forms a steep slope, and the slope angle is large, so that the risk of climbing and breaking of the second insulating layer 6 is high.

In some embodiments, when the array substrate in fig. 3 is prepared, the thickness of each of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 is 400 angstroms; the thickness of the first insulating layer 5 was 600 angstroms. Compared with the pixel electrode thickness scheme, the distance difference between the surface of the first pixel electrode 31 and the surface of the second pixel electrode 32, which is away from the substrate 1, and the substrate 1 is reduced, so that the display brightness difference of the sub-pixels adopting the first pixel electrode 31 and the sub-pixels adopting the second pixel electrode 32 when displaying the same gray scale signal is reduced, and the display stripe phenomenon (i.e. the display mura phenomenon) can be improved; at the same time, the risk of damage to the insulating planarization layer 4 by etching of the first insulating layer 5 is also improved.

In some embodiments, when the array substrate in fig. 5 is prepared, the thickness of the second sub-portion of the first pixel electrode 31 is 1200 angstroms; the thickness of the second sub-portion of the second pixel electrode 32 is 400 angstroms; the thickness of the first insulating layer 5 was 800 angstroms. Compared with the thickness scheme of the second sub-portion of the pixel electrode, the distance difference between the surface of the first pixel electrode 31 and the surface of the second pixel electrode 32, which is away from the substrate 1, and the substrate 1 is 0, so that the sub-pixels adopting the first pixel electrode 31 and the sub-pixels adopting the second pixel electrode 32 have the same display brightness when displaying gray scale signals of the same size, and the display stripe phenomenon (i.e. the display mura phenomenon) can be further improved or avoided; however, the first pixel electrode 31 is thick, and when the first pixel electrode film is deposited, the first pixel electrode film is easily locally crystallized due to a heat accumulation effect, so that etching residues occur when the first pixel electrode 31 is etched and formed; in addition, the etching of the first insulating layer 5 may have a certain risk of damage to the insulating planar layer 4.

In some embodiments, in the preparation of the array substrate in fig. 4, the preparation of the insulating planarization layer 4 includes sequentially preparing an organic insulating layer and an inorganic insulating layer over the substrate 1, and by using the preparation method of the array substrate in fig. 7, damage to the insulating planarization layer 4 due to etching of the first insulating layer 5 is reduced; however, since the insulating planarization layer 4 is composed of two layers, namely, an organic insulating layer and an inorganic insulating layer, the transmittance of the array substrate is reduced, and a mask process is required to be added to prepare a via hole in the inorganic insulating layer, where the via hole is a via hole capable of connecting the pixel electrode and the drain electrode of the transistor.

In some embodiments, referring to fig. 9, a cross-sectional flow diagram of another fabrication method for fabricating the array substrate of fig. 3 is shown; the first pixel electrode 31 and the second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S201: a patterning process is used to pattern the first pixel electrode 31 on the insulating planarization layer 4.

In this step, a pattern of the first pixel electrode 31 is formed by sputtering deposition of an indium tin oxide film layer, coating of a photoresist, exposure, development, and wet etching processes.

Step S202: a first insulating layer film 9 is deposited.

In this step, a first insulating layer film 9 of a silicon nitride material is deposited by chemical vapor deposition.

Step S203: thinning a local area of the first insulating layer film 9 by an etching process; the partial region is a region of the first insulating layer film 9 other than the pattern covering the first pixel electrode 31.

In this step, while forming a via pattern connecting the second pixel electrode 32 and the transistor drain in the first insulating layer film 9, a local area of the first insulating layer film 9 is thinned from 800 angstroms to several tens of angstroms by a halftone mask dry etching process.

Step S204: a pattern of the second pixel electrode 32 is formed in the thinned region of the first insulating layer film 9 by a patterning process.

In this step, a pattern of the second pixel electrode 32 is formed by sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.

Step S205: and etching to form the pattern of the first insulating layer 5 by using the pattern of the second pixel electrode 32 as a mask.

In this step, the first insulating layer 5 is patterned by a dry etching process.

Step S206: a second insulating layer 6 is deposited on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 facing away from the substrate 1.

In some embodiments, when the array substrate of fig. 3 is prepared, the thicknesses of the second sub-portions of the first and

second pixel electrodes

31 and 32 are 800 angstroms, respectively; the thickness of the first insulating layer 5 is several tens of angstroms. Compared with the preparation scheme of the pixel electrode in fig. 7, the distance difference between the surface of the first pixel electrode 31 and the surface of the second pixel electrode 32, which is away from the substrate 1, and the substrate 1 is reduced, so that the display brightness difference is reduced when the sub-pixels adopting the first pixel electrode 31 and the sub-pixels adopting the second pixel electrode 32 display gray scale signals of the same size, the display stripe phenomenon (i.e., the display mura phenomenon) can be improved, and the display effect of the display panel adopting the array substrate is improved. However, when the pattern of the first insulating layer 5 is formed by etching, there is a great risk of damage to the insulating flat layer 4 made of an organic insulating material, and if a great damage is caused, a steep slope is formed on the edge end face of the second pixel electrode 32, and the slope angle is large, so that the risk of climbing and breaking of the second insulating layer 6 is high.

In some embodiments, referring to fig. 10, a cross-sectional flow diagram of a method for manufacturing the array substrate of fig. 6 is shown; the first pixel electrode 31 and the second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S301: a pattern of the first pixel electrode 31 is formed on the insulating planarization layer 4 using a patterning process.

Step S302: the first pixel electrode 31 is annealed to crystallize the first pixel electrode 31.

In this step, the first pixel electrode 31 is annealed at a high temperature of 230 ℃. The annealing process can crystallize the material of the first pixel electrode 31, for example, crystallize the ito material, and the crystallized material of the first pixel electrode 31 is not removed by etching when the second pixel electrode film 10 is subsequently etched to form a pattern.

Step S303: and depositing to form a second pixel electrode film layer 10.

In this step, a second pixel electrode film layer 10 is formed by sputtering deposition, and the orthographic projection of the second pixel electrode film layer 10 on the substrate 1 covers the whole substrate 1.

Step S304: the second pixel electrode 32 is patterned using a patterning process.

In this step, a pattern of the second pixel electrode 32 is formed by sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes. In this etching process, no etching damage is caused to the pattern of the first pixel electrode 31.

Step S305: a second insulating layer 6 is deposited on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 facing away from the substrate 1.

In this embodiment, in the method for manufacturing the array substrate in fig. 10, the distance difference between the surface of the first pixel electrode 31 and the surface of the second pixel electrode 32, which is away from the substrate 1, and the substrate 1 is 0, so that the display brightness of the sub-pixels using the first pixel electrode 31 is the same as that of the sub-pixels using the second pixel electrode 32 when displaying the same gray-scale signal, thereby avoiding the display stripe phenomenon (i.e., the display mura phenomenon) and improving the display effect of the display panel using the array substrate. Meanwhile, in the preparation method of the array substrate in fig. 10, the first insulating layer does not need to be formed, so that the preparation method does not cause any damage to the insulating flat layer 4 of the organic insulating material and/or the inorganic insulating material which is not covered by the first pixel electrode 31 and the second pixel electrode 32, and further the second insulating layer 6 does not have the risk of climbing and breaking.

In some embodiments, referring to fig. 11, a cross-sectional flow diagram of another fabrication method for fabricating the array substrate of fig. 6 is shown; the first pixel electrode 31 and the second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S401: forming a pattern of a first pixel electrode 31 on the insulating flat layer 4 by using a patterning process while maintaining a first photoresist pattern 11 on the pattern of the first pixel electrode 31; the orthographic projection of the first photoresist pattern 11 on the substrate 1 covers only the pattern of the first pixel electrode 31.

Step S402: and depositing to form a second pixel electrode film layer 10.

Step S403: forming a second photoresist pattern 12 by using an exposure process; the orthographic projection of the second photoresist pattern 12 on the substrate 1 only covers the pattern of the second pixel electrode 32.

In this step, the exposure process includes exposure and development steps.

Wherein, the first photoresist pattern 11 and the second photoresist pattern 12 may both use a positive photoresist or a negative photoresist.

Step S404: and etching to remove the second pixel electrode film layer 10 in the region except the region covered by the second photoresist pattern 12, thereby forming a pattern of a second pixel electrode 32.

In this step, the second pixel electrode 32 is patterned through a wet etching process.

Step S405: and developing to remove the first photoresist pattern and the second photoresist pattern.

Step S406: a second insulating layer 6 is deposited on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 facing away from the substrate 1.

In this embodiment, in the manufacturing method of the array substrate in fig. 11, the distance difference between the surface of one side of the first pixel electrode 31 and the surface of one side of the second pixel electrode 32, which is away from the substrate 1, and the substrate 1 is 0, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the second pixel electrode 32 have the same display brightness when displaying gray-scale signals of the same size, a display stripe phenomenon (i.e., a display mura phenomenon) can be avoided, and the display effect of the display panel using the array substrate is improved. Meanwhile, in the preparation method of the array substrate in fig. 11, the first insulating layer is not required to be formed, so that the preparation method does not cause any damage to the insulating flat layer 4 of the organic insulating material and/or the inorganic insulating material which is not covered by the first pixel electrode 31 and the second pixel electrode 32, and further the second insulating layer 6 does not have a risk of climbing and breaking. However, when the second pixel electrode film layer 10 is formed by deposition, the photoresist material of the first photoresist pattern 11 is easily sputtered to contaminate the deposition chamber, which results in poor deposition of the second pixel electrode film layer 10.

In some embodiments, referring to fig. 12, a cross-sectional flow diagram of a structure of another manufacturing method for manufacturing the array substrate of fig. 6 is shown; the first pixel electrode 31 and the second pixel electrode 32 are prepared over the insulating planarization layer 4, including: step S501: a pixel electrode film layer 13 is deposited on the insulating planarization layer 4.

In this step, a pixel electrode film layer 13 is formed by sputtering deposition, and an orthographic projection of the pixel electrode film layer 13 on the substrate 1 covers the entire substrate 1.

Step S502: forming a positive photoresist pattern 14 on the pixel electrode film layer 13 by using an exposure process; the orthographic projection of the positive photoresist pattern 14 on the substrate 1 covers only the pattern of the first pixel electrode.

In this step, the exposure process includes steps of coating a film layer, performing exposure using the mask plate 16, and developing.

Step S503: forming a negative photoresist pattern 15 on the pixel electrode film layer 13 by using an exposure process; the positive projection of the negative photoresist pattern 15 on the substrate 1 covers only the pattern of the second pixel electrode.

In this step, the exposure process includes steps of coating a film layer, exposing with the mask 16, and developing.

Step S504: the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 are formed by etching.

In this step, the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 are formed by a wet etching process.

Step S505: and developing to remove the positive photoresist pattern and the negative photoresist pattern.

Step S506: a second insulating layer 6 is deposited on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 facing away from the substrate 1.

In this embodiment, in the manufacturing method of the array substrate in fig. 12, the distance difference between the surface of one side of the first pixel electrode 31 and the surface of one side of the second pixel electrode 32, which is away from the substrate 1, and the substrate 1 is 0, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the second pixel electrode 32 have the same display brightness when displaying gray-scale signals of the same size, a display stripe phenomenon (i.e., a display mura phenomenon) can be avoided, and the display effect of the display panel using the array substrate is improved. Meanwhile, in the preparation method of the array substrate in fig. 12, the first insulating layer does not need to be formed, so that the preparation method does not cause any damage to the insulating flat layer 4 of the organic insulating material and/or the inorganic insulating material which is not covered by the first pixel electrode 31 and the second pixel electrode 32, and further the second insulating layer 6 does not have a risk of climbing and breaking. However, in the preparation method, when the negative photoresist film layer is coated and developed to form the negative photoresist pattern 15, the developing solution is liable to damage the positive photoresist pattern 14, which causes a defect in the pattern of the first pixel electrode 31.

The array substrate and the preparation method thereof provided by the embodiment of the disclosure are characterized in that the 2n-1 th pixel electrode is prepared by a first composition process along the row direction and/or the column direction of the pixel electrode array; compared with the scheme that all the pixel electrodes are prepared through the primary composition process in the prior art, the method has the advantages that the preparation of the ultra-small gap between the adjacent pixel electrodes can be realized under the exposure precision of the existing exposure equipment, so that the accurate pattern of the pixel electrodes is formed, and the uniformity of the pattern of the pixel electrodes in the array substrate is ensured; and then the preparation of the high-resolution array substrate can be better realized.

In a third aspect, an embodiment of the present disclosure further provides a display panel, which includes the array substrate in the foregoing embodiment.

In some embodiments, the display panel further includes a pair-cell substrate, and the array substrate and the pair-cell substrate form a gap therebetween, and the gap is filled with liquid crystal. That is, the display panel in this embodiment is a liquid crystal display panel.

In some embodiments, the display panel is a TN (Twisted Nematic) liquid crystal display panel, i.e., a full-area common electrode is disposed on the cell substrate, and an electric field capable of deflecting liquid crystals is formed between the common electrode and the pixel electrode on the array substrate. And a backlight source is arranged on one side of the array substrate, which deviates from the opposite box substrate, and the backlight source provides backlight to realize the display of the whole liquid crystal display panel after passing through the pixel electrode, the liquid crystal layer and the common electrode.

By adopting the array substrate in the embodiment, high-resolution display of the display panel can be realized, so that the display quality of the display panel is improved.

In a fourth aspect, an embodiment of the present disclosure further provides a display device, including the display panel in the foregoing embodiment.

By adopting the display panel in the embodiment, high-resolution display of the display device can be realized, so that the display quality of the display device is improved.

The display device may be: any product or component with a display function, such as an LCD panel, an LCD television, a mobile phone, a tablet computer, a notebook computer, a display, a digital photo frame, a navigator and the like.

It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.

Claims

1. A preparation method of an array substrate comprises the following steps:

preparing a pixel driving circuit on a substrate;

2. The method of manufacturing an array substrate according to claim 1, wherein the manufacturing the first pixel electrode and the second pixel electrode includes:

forming a graph of the first pixel electrode on the insulation flat layer by adopting a composition process; depositing a first insulating layer film;

forming a graph of the second pixel electrode on the first insulating layer film by adopting a composition process;

3. The method of manufacturing an array substrate according to claim 1, wherein the manufacturing the first pixel electrode and the second pixel electrode includes:

depositing a first insulating layer film;

4. The method of manufacturing an array substrate according to claim 1, wherein the manufacturing the first pixel electrode and the second pixel electrode includes:

forming a graph of the first pixel electrode on the insulation flat layer by adopting a composition process;

annealing the first pixel electrode to crystallize the first pixel electrode;

depositing to form a second pixel electrode film layer;

5. The method of manufacturing an array substrate according to claim 1, wherein the manufacturing the first pixel electrode and the second pixel electrode includes:

depositing to form a second pixel electrode film layer;

and developing and removing the first photoresist pattern and the second photoresist pattern.

6. The method of manufacturing an array substrate according to claim 1, wherein the manufacturing the first pixel electrode and the second pixel electrode includes:

depositing a pixel electrode film layer on the insulating flat layer;

and developing to remove the positive photoresist pattern and the negative photoresist pattern.

7. The method of fabricating an array substrate according to any one of claims 1 to 6, further comprising: and depositing and forming a second insulating layer on one side, which is far away from the substrate, of the pattern of the first pixel electrode and the pattern of the second pixel electrode.

8. An array substrate, comprising: a substrate;

a pixel driving circuit on the substrate;

the plurality of pixel electrodes are arranged in an array;

along the row direction and/or the column direction of the array, the spacing distance between any two adjacent pixel electrodes is less than or equal to 2 μm; any two adjacent pixel electrodes are respectively a first pixel electrode and a second pixel electrode; the absolute value range of the difference between the distance between the surface of one side of the first pixel electrode, which is far away from the substrate, and the substrate and the distance between the surface of one side of the second pixel electrode, which is far away from the substrate, and the substrate is 0-1500 angstroms.

9. The array substrate of claim 8, wherein the pixel electrode includes a first sub-portion and a second sub-portion, the first sub-portion extending in a row direction of the array, the second sub-portion extending in a column direction of the array, and the first sub-portion and the second sub-portion being connected;

the extension length of the first sub-part is less than that of the second sub-part;

10. The array substrate of claim 9, wherein the second sub-portion of the first pixel electrode is equal in thickness to the second sub-portion of the second pixel electrode;

a first insulating layer is further arranged between the second pixel electrode and the horizontal surface of the insulating flat layer;

11. The array substrate of claim 9, wherein the thickness of the second sub-portion of the first pixel electrode is greater than the thickness of the second sub-portion of the second pixel electrode;

a first insulating layer is further arranged between the second pixel electrode and the horizontal surface of the insulating flat layer; an orthographic projection of the first insulating layer on the substrate is coincided with an orthographic projection of the second pixel electrode on the substrate;

12. The array substrate of any one of claims 10-11, further comprising a second insulating layer on a side of the pixel electrode facing away from the substrate, wherein an orthographic projection of the second insulating layer on the substrate covers the entire substrate.

13. A display device comprising the array substrate of any one of claims 8 to 12.