CN110190132A - Film transistor device and preparation method thereof - Google Patents
Film transistor device and preparation method thereof Download PDFInfo
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- CN110190132A CN110190132A CN201910414809.1A CN201910414809A CN110190132A CN 110190132 A CN110190132 A CN 110190132A CN 201910414809 A CN201910414809 A CN 201910414809A CN 110190132 A CN110190132 A CN 110190132A
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- film transistor
- gate insulating
- transistor device
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- 238000002360 preparation method Methods 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims description 401
- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000011241 protective layer Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000005516 engineering process Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 238000010849 ion bombardment Methods 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- BHPQYMZQTOCNFJ-UHFFFAOYSA-N Calcium cation Chemical compound [Ca+2] BHPQYMZQTOCNFJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910001424 calcium ion Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- -1 helium ion Chemical class 0.000 claims description 3
- 229910010272 inorganic material Inorganic materials 0.000 claims description 3
- 239000011147 inorganic material Substances 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910052725 zinc Inorganic materials 0.000 claims 1
- 239000011701 zinc Substances 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 47
- 230000000694 effects Effects 0.000 abstract description 12
- 238000010304 firing Methods 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 27
- 239000000377 silicon dioxide Substances 0.000 description 17
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- 239000012212 insulator Substances 0.000 description 7
- 230000001105 regulatory effect Effects 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 239000003153 chemical reaction reagent Substances 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Abstract
The present invention provides a kind of film transistor device and preparation method thereof, and the film transistor device includes: substrate, active layer, gate insulating layer, conductive layer and grid layer.The preparation method of the thin film transistor (TFT) is the following steps are included: light shield layer preparation step, buffer layer preparation step, active layer preparation step and grid layer preparation step.The technical effects of the invention are that, on gate insulating layer upper surface there is conductive layer in various loci, so that corresponding active layer can be adjusted below entire gate insulating layer, increase the firing current of film transistor device, the electrology characteristic of enhanced film transistor device improves the display effect of display device.
Description
Technical field
The present invention relates to field of display, in particular to a kind of film transistor device and preparation method thereof.
Background technique
Since the TFT (Thin Film Transistor, thin film transistor (TFT)) of top gate structure has lower parasitic capacitance,
More excellent electrology characteristic, is therefore widely used in display device.
In the prior art make top gate structure film transistor device TFT when, due to grid G ate to be used with
The self-registered technology of gate insulator pattern GI, and grid G ate generallys use wet-etching technology production, gate insulator pattern GI
It is made by dry etch process, when using wet-etching technology etching grid Gate, since etching liquid can be under photoresist
Face etches a small distance more, leads to grid G ate short compared to gate insulator pattern GI a small distance, i.e. grid out in this way
Gate cannot be completely coincident with orthographic projection of the gate insulator pattern GI on underlay substrate.Due to two above gate insulator pattern GI
There is a small distance non-grid Gate in side, leads to lack the active layer figure below the gate insulator pattern GI of grid G ate covering
Case IGZO is not regulated and controled by grid G ate, and then causes the firing current of the TFT of top gate structure insufficient, to influence top-gated TFT
Electrology characteristic so that the display effect of display device is also affected.
Summary of the invention
It is an object of the present invention to solve in existing film transistor device at gate insulating layer top surface edge without grid
Pole layer, causes the edge of the active layer below gate insulating layer not to be adjusted, the electrology characteristic of film transistor device is poor, aobvious
The technical problems such as showing device poor display effect.
To achieve the above object, the present invention provides a kind of film transistor device, comprising: substrate；Active layer is set to described
The surface of substrate side；Gate insulating layer, the surface set on the active layer far from the substrate side；Conductive layer is set to institute
State surface of the gate insulating layer far from the active layer side；And grid layer, it is exhausted far from the grid to be set to the conductive layer
The surface of edge layer side.
Further, the material of the conductive layer includes oxide semiconductor, and the oxide semiconductor includes indium gallium zinc
Oxide；The conductor layer with a thickness of 100A~400A.
Further, the size of the conductive layer is consistent with the size of the gate insulating layer, and the conductive layer and institute
Gate insulating layer is stated to be oppositely arranged；The size of the grid layer be less than the conductive layer size, and the grid layer with it is described
Conductive layer is oppositely arranged.
Further, the film transistor device further include: light shield layer, set on the surface of the substrate side；And
Buffer layer, the surface set on the light shield layer far from the substrate side；Wherein, it is separate to be set to the buffer layer for the active layer
The surface of the substrate side, and be oppositely arranged with the light shield layer.
Further, the film transistor device further include: dielectric layer is set to the grid layer far from the conductive layer
The surface of side；Dielectric layer via hole passes through the dielectric layer, and is oppositely arranged with the active layer；Source-drain electrode layer is set to described
Surface of the dielectric layer far from the buffer layer side, and pass through the dielectric layer via hole and be connected to the active layer；Protective layer, if
In the surface of the source-drain electrode layer and the dielectric layer far from the buffer layer side；Protective layer via hole passes through the protective layer,
And it is oppositely arranged with the source-drain electrode layer；And pixel electrode layer, it is set to the protective layer via hole inner sidewall, and extend to described
Surface of the protective layer far from source-drain electrode layer side, the pixel electrode layer are connected to the source-drain electrode layer.
To achieve the above object, the present invention also provides a kind of preparation methods of film transistor device to include the following steps:
Light shield layer preparation step prepares a light shield layer on a substrate；Buffer layer preparation step, in the light shield layer and the substrate
Upper surface prepare a buffer layer；Active layer preparation step prepares an active layer in the upper surface of the buffer layer；And
Grid layer preparation step is sequentially prepared out gate insulating layer, conductive layer and grid layer in the upper surface of the active layer.
Further, the grid layer preparation step is the following steps are included: inorganic layer forming step, in the active layer and
The upper surface inorganic material of the buffer layer forms an inorganic layer；Semiconductor layer forming step, in the upper of the inorganic layer
Surface deposition oxide semiconductor material forms semi-conductor layer；Metal layer forming step, in the upper surface of the semiconductor layer
Deposited metal material forms a metal layer；And etch step, etch grid layer, conductive layer and gate insulating layer.
Further, the etch step is the following steps are included: photoresist application step, in the upper of the first metal layer
Surface is coated with a photoresist；The metal layer is etched into grid layer using wet-etching technology by the first etch step；Second quarter
Step is lost, the semiconductor layer is etched into conductive layer using dry etch process, the inorganic layer is etched into gate insulator
Layer, so that the size of the conductive layer is consistent with the size of the gate insulating layer；Photoresist lift off step, stripping photoresist；
And conductor step, the active layer that conductorization processing is not covered by the gate insulating layer.
Further, in second etch step, etching gas includes boron chloride.
Further, in the conductor step, ion bombardment processing or ion implanting handle the substrate；Wherein,
The ion of the ion bombardment processing includes argon gas ion or helium ion；The ion of the ion implanting processing includes aluminium ion
Or calcium ion.
The technical effects of the invention are that increasing by a conductive layer between grid layer and gate insulating layer, and the conduction
Layer etches gained using same etching technics with the gate insulating layer, so that conductive pattern and gate insulating layer are on substrate
Orthographic projection is overlapped, i.e., various loci has conductive layer on gate insulating layer upper surface, and the conductive layer compensates for the prior art
The defect of top a small distance non-grid of middle gate insulating layer edge, so that corresponding below entire gate insulating layer have
Active layer can be regulated and controled by grid layer, increase the firing current of film transistor device, the electricity of enhanced film transistor device
Characteristic improves the display effect of display device.
Detailed description of the invention
Fig. 1 is the flow chart of the preparation method of film transistor device described in the embodiment of the present invention；
Fig. 2 is the structural representation of the film transistor device after buffer layer preparation step described in the embodiment of the present invention
Figure；
Fig. 3 is the structural representation of the film transistor device after active layer preparation step described in the embodiment of the present invention
Figure；
Fig. 4 is the flow chart of grid layer preparation step described in the embodiment of the present invention；
Fig. 5 is the flow chart of etch step described in the embodiment of the present invention；
Fig. 6 is the structural representation of the film transistor device after grid layer preparation step described in the embodiment of the present invention
Figure；
Fig. 7 is the structural representation of the film transistor device after dielectric layer opening step described in the embodiment of the present invention
Figure；
Fig. 8 is the structural representation of the film transistor device after source-drain electrode layer preparation step described in the embodiment of the present invention
Figure；
Fig. 9 is the structural representation of the film transistor device after protective layer opening step described in the embodiment of the present invention
Figure；
Figure 10 is the structural schematic diagram of film transistor device described in the embodiment of the present invention.
Members mark is as follows:
1, substrate；2, light shield layer；3, buffer layer；4, active layer；41, semiconductor portion；42, conductor portion；5, gate insulating layer；
6, conductive layer；7, grid layer；
8, dielectric layer；81, dielectric layer via hole；9, source-drain electrode layer；10, protective layer；101, protective layer via hole；11, pixel electricity
Pole layer.
Specific embodiment
Below in conjunction with Figure of description, the preferred embodiments of the present invention are described in detail, with complete to those of skill in the art
It is whole to introduce technology contents of the invention, prove that the present invention can be implemented with citing, so that technology contents disclosed by the invention are more
It is clear, so that will more readily understand how implement the present invention by those skilled in the art.However the present invention can pass through many differences
The embodiment of form emerges from, and protection scope of the present invention is not limited only to the embodiment mentioned in text, Examples below
The range that is not intended to limit the invention of explanation.
The direction term that the present invention is previously mentioned, for example, "upper", "lower", "front", "rear", "left", "right", "inner", "outside", "
Side " etc. is only the direction in attached drawing, and direction term used herein is of the invention for explanation and illustration, rather than is used
To limit the scope of protection of the present invention.
In the accompanying drawings, the identical component of structure is indicated with same numbers label, everywhere the similar component of structure or function with
Like numeral label indicates.In addition, in order to facilitate understanding and description, the size and thickness of each component shown in the drawings are any
It shows, the present invention does not limit the size and thickness of each component.
When certain components, when being described as " " another component "upper", the component can be placed directly within described another group
On part；There may also be an intermediate module, the component is placed on the intermediate module, and the intermediate module is placed in another group
On part.When a component is described as " installation is extremely " or " being connected to " another component, the two can be understood as direct " installation "
Or " connection " or a component pass through an intermediate module " installation is extremely " or " being connected to " another component.
As shown in Fig. 1~10, the present embodiment provides a kind of preparation methods of film transistor device, include the following steps S1
~S8.
S1 light shield layer preparation step deposits light screening material, the shape after yellow light technique and etching technics in the upper surface of substrate 1
At shading layer pattern, i.e. light shield layer 2.
S2 buffer layer preparation step deposits padded coaming in the upper surface of light shield layer 2 and substrate 1, through yellow light technique and quarter
Buffering layer pattern, i.e. buffer layer 3 (referring to fig. 2) are formed after etching technique, buffer layer 3 is silica SiO2Film layer or titanium dioxide
Silicon SiO2, silicon nitride SiNxMultiple-level stack, wherein silica SiO2Film layer is set to top layer.
S3 active layer preparation step, in the upper surface deposited semiconductor material of buffer layer 3, preferably indium gallium zinc oxide
IGZO, forms semiconductor pattern, i.e. active layer 4 (referring to Fig. 3) after yellow light technique and etching technics, and the film layer of active layer 4 is thick
Degree is 300A~500A, preferably 400A.
S4 grid layer preparation step prepares gate insulating layer 5, conductive layer 6 in the upper surface of active layer 4 and buffer layer 3
And grid layer 7.
As shown in figures 4-6, the grid layer preparation step specifically includes following steps S41~S44.
It is inorganic to form one in active layer 4 and the upper surface inorganic material of buffer layer 3 for S41 inorganic layer preparation step
Layer.S42 semiconductor layer preparation step, in the upper surface deposition oxide semiconductor material in the inorganic layer of the inorganic layer
Material, the oxide semiconductor material are indium gallium zinc oxide IGZO, form semi-conductor layer.S43 the first metal layer forms step
Suddenly, in the upper surface deposited metal material of the semiconductor layer, the metal material includes copper Cu or molybdenum Mo, forms one first gold medal
Belong to layer.
S44 etch step etches grid layer, conductive layer and gate insulating layer, and the first metal layer is etched into grid
Pole layer 7, is etched into conductive layer 6 for semiconductor layer, inorganic layer is etched into gate insulating layer 5, the etch step includes following
Step S441~S445.
S441 photoresist application step is coated with a layer photoresist PR in the upper surface of the first metal layer.S442 first
The first metal layer is etched into grid layer 7 using wet-etching technology by etch step.The principle of the wet etching is handle
Substrate is immersed in chemical reagent or reagent solution, makes that a part of film surface and reagent for not having to be sheltered by resist
It chemically reacts and is removed.The semiconductor layer is etched into conductive layer using dry etch process by the second etch step of S443
6, the inorganic layer is etched into gate insulating layer 5, so that the size of conductive layer 6 is identical as the size of gate insulating layer 5 or phase
Seemingly, the size of conductive layer 6 is overlapped with the orthographic projection of gate insulating layer 5 on substrate 1.The etching gas of the dry etching is preferred
Boron chloride BCL3.S444 photoresist lift off step, stripping photoresist.S445 conductor step, the processing of autoregistration conductorization is not
The active layer covered by grid layer insulating 5.The conductorization processing includes that ion bombardment processing or ion implanting are handled,
In, the ion of the ion bombardment processing includes argon gas ion or helium ion；It includes aluminium that the ion implanting processing, which is ion,
Ion or calcium ion.At this point, active layer 4 is divided into semiconductor portion 41 and conductor portion 42, semiconductor portion 41 is by gate insulating layer 5
The part of covering, conductor portion 42 are the active layer that 41 two sides of semiconductor portion are not covered by gate insulating layer 5 (referring to Fig. 6).
Increase conductive layer 6 between gate insulating layer 5 and grid layer 7, so that the upper surface of gate insulating layer 5 is deposited everywhere
In conductive pattern, the defect of the edge non-grid of gate insulating layer upper surface in the prior art is compensated for, grid can be made
The corresponding active layer semiconductor portion 41 in 5 lower section of insulating layer can be regulated and controled by grid layer 7, increase the unlatching electricity of film transistor device
Stream, the electrology characteristic of enhanced film transistor device.It, can be according to not using the lithographic method of wet etching and dry etching
The film layer of same material etches different patterns.
S5 dielectric layer preparation step, in buffer layer 3 and the upper surface deposit dielectric layer material of grid layer 7, through yellow light technique
And dielectric layer 8 and dielectric layer via hole 81 are formed after etching technics, more than two dielectric layer via holes 81 pass through dielectric layer 8, dielectric layer
Via hole 81 and the conductor portion 42 of active layer are oppositely arranged, convenient for subsequent circuit conducting (referring to Fig. 7).
S6 source-drain electrode layer preparation step deposits a metal material in dielectric layer via hole 81, forms a second metal layer, institute
It states second metal layer and extends to dielectric layer 8, after yellow light technique and etching technics, the second metal layer forms source-drain electrode layer 9,
Source-drain electrode layer 9 passes through the conductor portion 42 that dielectric layer via hole 81 is connected to active layer, guarantees the electrical property of source-drain electrode layer 9 and active layer 4
Connection, guarantees that the circuit connection of entire film transistor device is unimpeded (referring to Fig. 8).
S7 protective layer preparation step deposits passivating material in the upper surface of source-drain electrode layer 9 and dielectric layer 8, through yellow light technique
And after etching technics, protective layer 10 and protective layer via hole 101 are formed, protective layer via hole 101 passes through protective layer 10, with source-drain electrode layer
9 are oppositely arranged, and provide electrical connecting passage for subsequent pixel electrode layer (referring to Fig. 9).
S8 pixel electrode layer preparation step, the pixel deposition electrode material tin indium oxide ITO in protective layer via hole 101, and
The upper surface for extending to protective layer 10 forms pixel electrode layer 11 after yellow light technique and etching technics, and pixel electrode layer 11 is logical
Overprotection layer via hole 101 is connected to source-drain electrode layer 9, completes the circuit connection of film transistor device.
The preparation method of film transistor device described in the present embodiment has technical effect that, exhausted in grid layer and grid
Increase by a conductive layer between edge layer, and the conductive layer and the gate insulating layer are made using same etching technics etching gained
It obtains conductive pattern to be overlapped with orthographic projection of the gate insulating layer on substrate, i.e., various loci exists on gate insulating layer upper surface
Conductive layer, the conductive layer compensate for lacking for top a small distance non-grid of gate insulating layer edge in the prior art
It falls into, so that corresponding active layer can be regulated and controled by grid layer below entire gate insulating layer, increases film transistor device
Firing current, the electrology characteristic of enhanced film transistor device improve the display effect of display device.
As shown in Figure 10, the present embodiment also provides a kind of film transistor device, including substrate 1, light shield layer 2, buffer layer
3, active layer 4, gate insulating layer 5, conductive layer 6, grid layer 7, dielectric layer 8, source-drain electrode layer 9, protective layer 10 and pixel electrode layer
11。
Light shield layer 2 is set to the upper surface of substrate 1, and light shield layer 2 does not cover entire substrate 1, and light shield layer 2 plays shading work
With.
Buffer layer 3 is set to the upper surface of light shield layer 2 and substrate 1, and buffer layer 3 plays buffer function, and the material of buffer layer 3 is
Silica SiO2Or the nitride SiN of siliconx, can be single layer SiO2Film layer or silica SiO2, silicon nitride SiNx
Multiple-level stack, and silica SiO2Film layer is set to top layer.
Active layer 4 is set to the upper surface of buffer layer 3, and is oppositely arranged with light shield layer 2.Active layer 4 includes semiconductor portion 41
And conductor portion 42, conductor portion 42 are set to the outside of semiconductor portion 41, semiconductor portion 41 keeps characteristic of semiconductor.The material of active layer 4
Matter is oxide semiconductor, such as indium gallium zinc oxide IGZO, with a thickness of 300A~500A, in the present embodiment, active layer 4
Thickness is preferably 400A.
Gate insulating layer 5 is set to the upper surface of active layer 4 and buffer layer 3, and gate insulating layer 5 can be single layer SiO2Film layer or
Person's silica SiO2, silicon nitride SiNxMultiple-level stack, and silica SiO2Film layer is set to bottom.
Conductive layer 6 is set to the upper surface of gate insulating layer 5, and identical or closely similar as the size of gate insulating layer, leads
Electric layer 6 is overlapped with the orthographic projection of gate insulating layer 5 on substrate 1, and the material of conductive layer 6 is oxide semiconductor, such as indium gallium
Zinc oxide IGZO, with a thickness of 100A~400A.
Conductive layer 6 and the size of gate insulating layer 5 are same or similar, lead so that the upper surface of gate insulating layer 5 all exists
Electrical pattern compensates for the defect of non-grid at gate insulating layer top surface edge in the prior art, so that below gate insulating layer 5
The semiconductor portion 41 of corresponding active layer can be regulated and controled by grid layer 7, increase the firing current of film transistor device, enhance thin
The electrology characteristic of film transistor device improves the display effect of display device.
Grid layer 7 is set to the upper surface of conductive layer 6, and size is less than the size of conductive layer 6, i.e. grid layer 7 on substrate 1
Orthographic projection area be less than the orthographic projection of conductive layer 6 on substrate 1 area.The material of grid layer 7 is metal, such as copper Cu or
Molybdenum Mo.
Dielectric layer 8 is set to the upper surface of grid layer 7 and buffer layer 3, and dielectric layer 8 is equipped with more than two dielectric layer via holes
81, dielectric layer via hole 81 passes through dielectric layer 8, and is oppositely arranged with the conductor portion of active layer 4 42, provides for subsequent source drain electrode layer logical
Road.
Source-drain electrode layer 9 is set in dielectric layer via hole 81, and extends to the upper surface of dielectric layer 8, and source-drain electrode layer 9 has been connected to
The conductor portion 42 of active layer 4 forms the electric connection of source-drain electrode layer 9 and active layer 4.The material of source-drain electrode layer 9 is metal.
Protective layer 10 is set to the upper surface of source-drain electrode layer 9 and dielectric layer 8, and protective layer 10 is also passivation layer, plays under protection
The effect of each film layer in face.Protective layer 10 is equipped with protective layer via hole 101, and protective layer via hole 101 passes through protective layer 10, and and source and drain
Pole layer 9 is oppositely arranged, and provides the channel of electrical connection for later pixel electrode layer.
Pixel electrode layer 11 is set to 101 bottom of protective layer via hole and inner sidewall, is connected to source-drain electrode layer 9, and extend to guarantor
The upper surface of sheath 10, the material of pixel electrode layer 11 are tin indium oxide ITO.
Having technical effect that for film transistor device described in the present embodiment, increases between grid layer and gate insulating layer
Add a conductive layer, and the conductive layer and the gate insulating layer etch gained using same etching technics, so that conductive pattern
It is overlapped with orthographic projection of the gate insulating layer on substrate, i.e., various loci has conductive layer on gate insulating layer upper surface, institute
The defect that conductive layer compensates for top a small distance non-grid of gate insulating layer edge in the prior art is stated, so that entirely
Corresponding active layer can be regulated and controled by the grid layer of top below gate insulating layer, increase the unlatching electricity of film transistor device
Stream, the electrology characteristic of enhanced film transistor device improve the display effect of display device.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of film transistor device characterized by comprising
Substrate；
Active layer, set on the surface of the substrate side；
Gate insulating layer, the surface set on the active layer far from the substrate side；
Conductive layer, the surface set on the gate insulating layer far from the active layer side；And
Grid layer, the surface set on the conductive layer far from the gate insulating layer side.
2. film transistor device as described in claim 1, which is characterized in that
The material of the conductive layer includes oxide semiconductor, and the oxide semiconductor includes indium gallium zinc；
The conductor layer with a thickness of 100A~400A.
3. film transistor device as described in claim 1, which is characterized in that
The size of the conductive layer is consistent with the size of the gate insulating layer, and the conductive layer and the gate insulating layer phase
To setting；
The size of the grid layer is less than the size of the conductive layer, and the grid layer is oppositely arranged with the conductive layer.
4. film transistor device as described in claim 1, which is characterized in that further include:
Light shield layer, set on the surface of the substrate side；And
Buffer layer, the surface set on the light shield layer far from the substrate side；
Wherein, the active layer is set to surface of the buffer layer far from the substrate side, and opposite with the light shield layer sets
It sets.
5. film transistor device as described in claim 1, which is characterized in that further include:
Dielectric layer, the surface set on the grid layer far from the conductive layer side；
Dielectric layer via hole passes through the dielectric layer, and is oppositely arranged with the active layer；
Source-drain electrode layer, the surface set on the dielectric layer far from the buffer layer side, and pass through the dielectric layer via hole and connect
To the active layer；
Protective layer, the surface set on the source-drain electrode layer and the dielectric layer far from the buffer layer side；
Protective layer via hole passes through the protective layer, and is oppositely arranged with the source-drain electrode layer；And
Pixel electrode layer is set to the protective layer via hole inner sidewall, and extends to the protective layer far from the source-drain electrode layer one
The surface of side, the pixel electrode layer are connected to the source-drain electrode layer.
6. a kind of preparation method of film transistor device, which comprises the steps of:
Light shield layer preparation step prepares a light shield layer on a substrate；
Buffer layer preparation step prepares a buffer layer in the upper surface of the light shield layer and the substrate；
Active layer preparation step prepares an active layer in the upper surface of the buffer layer；And
Grid layer preparation step is sequentially prepared out gate insulating layer, conductive layer and grid layer in the upper surface of the active layer.
7. the preparation method of film transistor device as claimed in claim 6, which is characterized in that
The grid layer preparation step the following steps are included:
Inorganic layer forming step forms an inorganic layer in the active layer and the upper surface inorganic material of the buffer layer；
Semiconductor layer forming step forms semi-conductor layer in the upper surface deposition oxide semiconductor material of the inorganic layer；
Metal layer forming step forms a metal layer in the upper surface deposited metal material of the semiconductor layer；And
Etch step etches grid layer, conductive layer and gate insulating layer.
8. the preparation method of film transistor device as claimed in claim 7, which is characterized in that
The etch step the following steps are included:
Photoresist application step is coated with a photoresist in the upper surface of the first metal layer；
The metal layer is etched into grid layer using wet-etching technology by the first etch step；
The semiconductor layer is etched into conductive layer using dry etch process, the inorganic layer is etched by the second etch step
At gate insulating layer, so that the size of the conductive layer is consistent with the size of the gate insulating layer；
Photoresist lift off step, stripping photoresist；And
Conductor step, the active layer that conductorization processing is not covered by the gate insulating layer.
9. the preparation method of film transistor device as claimed in claim 8, which is characterized in that
In second etch step, etching gas includes boron chloride.
10. the preparation method of film transistor device as claimed in claim 8, which is characterized in that
In the conductor step,
Ion bombardment processing or ion implanting handle the substrate；
Wherein, the ion of the ion bombardment processing includes argon gas ion or helium ion；The ion of the ion implanting processing
Including aluminium ion or calcium ion.
Priority Applications (2)
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| CN201910414809.1A CN110190132A (en) | 2019-05-17 | 2019-05-17 | Film transistor device and preparation method thereof |
| PCT/CN2019/089783 WO2020232747A1 (en) | 2019-05-17 | 2019-06-03 | Thin-film transistor device and preparation method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910414809.1A CN110190132A (en) | 2019-05-17 | 2019-05-17 | Film transistor device and preparation method thereof |
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Cited By (1)
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|---|---|---|---|---|
| CN111403488A (en) * | 2020-03-31 | 2020-07-10 | 合肥鑫晟光电科技有限公司 | Thin film transistor, preparation method thereof, substrate for display and display device |
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