CN107546205B - 芯片封装件的篡改检测 - Google Patents
芯片封装件的篡改检测 Download PDFInfo
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- CN107546205B CN107546205B CN201710506432.3A CN201710506432A CN107546205B CN 107546205 B CN107546205 B CN 107546205B CN 201710506432 A CN201710506432 A CN 201710506432A CN 107546205 B CN107546205 B CN 107546205B
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- 238000001514 detection method Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 230000008859 change Effects 0.000 claims description 8
- 238000012544 monitoring process Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 8
- 230000033001 locomotion Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 239000000523 sample Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/44—Testing lamps
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- H—ELECTRICITY
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- H01L23/495—Lead-frames or other flat leads
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- H01L2224/0554—External layer
- H01L2224/0555—Shape
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/195,029 | 2016-06-28 | ||
US15/195,029 US10651135B2 (en) | 2016-06-28 | 2016-06-28 | Tamper detection for a chip package |
Publications (2)
Publication Number | Publication Date |
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CN107546205A CN107546205A (zh) | 2018-01-05 |
CN107546205B true CN107546205B (zh) | 2021-01-26 |
Family
ID=60677063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710506432.3A Expired - Fee Related CN107546205B (zh) | 2016-06-28 | 2017-06-28 | 芯片封装件的篡改检测 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10651135B2 (zh) |
CN (1) | CN107546205B (zh) |
TW (1) | TWI660184B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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FR3077678B1 (fr) * | 2018-02-07 | 2022-10-21 | St Microelectronics Rousset | Procede de detection d'une atteinte a l'integrite d'un substrat semi-conducteur d'un circuit integre depuis sa face arriere, et dispositif correspondant |
WO2020043170A1 (en) * | 2018-08-31 | 2020-03-05 | Changxin Memory Technologies, Inc. | Arrangement of bond pads on an integrated circuit chip |
US10925154B2 (en) * | 2019-01-31 | 2021-02-16 | Texas Instruments Incorporated | Tamper detection |
US11205625B2 (en) | 2019-04-12 | 2021-12-21 | Invensas Bonding Technologies, Inc. | Wafer-level bonding of obstructive elements |
US11610846B2 (en) * | 2019-04-12 | 2023-03-21 | Adeia Semiconductor Bonding Technologies Inc. | Protective elements for bonded structures including an obstructive element |
US11373963B2 (en) | 2019-04-12 | 2022-06-28 | Invensas Bonding Technologies, Inc. | Protective elements for bonded structures |
US11081455B2 (en) * | 2019-04-29 | 2021-08-03 | Infineon Technologies Austria Ag | Semiconductor device with bond pad extensions formed on molded appendage |
US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
CN110363271A (zh) * | 2019-07-19 | 2019-10-22 | 云南纳光科技有限公司 | 通过检测引脚通断实现防篡改检测的无源nfc防伪芯片 |
CN111696983B (zh) * | 2020-06-24 | 2024-03-15 | 悦虎晶芯电路(苏州)股份有限公司 | 多芯片水平封装的芯片模组、晶圆结构和加工方法 |
US11798876B2 (en) * | 2021-09-07 | 2023-10-24 | Novatek Microelectronics Corp. | Chip on film package and display device including the same |
US20230075399A1 (en) * | 2021-09-08 | 2023-03-09 | Nuvoton Technology Corporation | Integrated circuit (ic) and electronic apparatus |
CN116306459B (zh) * | 2023-02-28 | 2024-06-04 | 本源科仪(成都)科技有限公司 | 量子芯片版图的引脚布置方法、系统、介质及设备 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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US5389738A (en) * | 1992-05-04 | 1995-02-14 | Motorola, Inc. | Tamperproof arrangement for an integrated circuit device |
US5861662A (en) | 1997-02-24 | 1999-01-19 | General Instrument Corporation | Anti-tamper bond wire shield for an integrated circuit |
US7417293B2 (en) * | 2004-04-27 | 2008-08-26 | Industrial Technology Research Institute | Image sensor packaging structure |
US7442583B2 (en) | 2004-12-17 | 2008-10-28 | International Business Machines Corporation | Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable |
US7557597B2 (en) * | 2005-06-03 | 2009-07-07 | International Business Machines Corporation | Stacked chip security |
US8492906B2 (en) * | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
US7710286B1 (en) * | 2007-03-30 | 2010-05-04 | Maxim Integrated Products, Inc. | Intrusion detection using a conductive material |
US7923830B2 (en) | 2007-04-13 | 2011-04-12 | Maxim Integrated Products, Inc. | Package-on-package secure module having anti-tamper mesh in the substrate of the upper package |
JP2009076815A (ja) * | 2007-09-25 | 2009-04-09 | Nec Electronics Corp | 半導体装置 |
EP2220679A4 (en) | 2007-12-06 | 2014-02-26 | Broadcom Corp | EMBEDDED PACKING SAFETY MANIPULATION MACHINE |
FR2938953B1 (fr) | 2008-11-21 | 2011-03-11 | Innova Card | Dispositif de protection d'un boitier de circuit integre electronique contre les intrusions par voie physique ou chimique. |
US8455990B2 (en) | 2009-02-25 | 2013-06-04 | Conexant Systems, Inc. | Systems and methods of tamper proof packaging of a semiconductor device |
US8811526B2 (en) * | 2011-05-31 | 2014-08-19 | Keyssa, Inc. | Delta modulated low power EHF communication link |
US9437512B2 (en) * | 2011-10-07 | 2016-09-06 | Mediatek Inc. | Integrated circuit package structure |
US8896086B1 (en) | 2013-05-30 | 2014-11-25 | Freescale Semiconductor, Inc. | System for preventing tampering with integrated circuit |
US9274545B2 (en) * | 2013-10-24 | 2016-03-01 | Globalfoundries Inc. | Apparatus and method to recover a data signal |
US9342710B2 (en) | 2013-11-21 | 2016-05-17 | Nxp B.V. | Electronic tamper detection |
-
2016
- 2016-06-28 US US15/195,029 patent/US10651135B2/en active Active
-
2017
- 2017-04-12 TW TW106112180A patent/TWI660184B/zh active
- 2017-06-28 CN CN201710506432.3A patent/CN107546205B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TWI660184B (zh) | 2019-05-21 |
TW201809706A (zh) | 2018-03-16 |
US10651135B2 (en) | 2020-05-12 |
CN107546205A (zh) | 2018-01-05 |
US20170373024A1 (en) | 2017-12-28 |
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