CN101889344B - 嵌入式封装防篡改网栅 - Google Patents

嵌入式封装防篡改网栅 Download PDF

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CN101889344B
CN101889344B CN2008801209411A CN200880120941A CN101889344B CN 101889344 B CN101889344 B CN 101889344B CN 2008801209411 A CN2008801209411 A CN 2008801209411A CN 200880120941 A CN200880120941 A CN 200880120941A CN 101889344 B CN101889344 B CN 101889344B
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protection
die pads
wafer
group
pad
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CN101889344A (zh
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马克·布尔
马太·考夫曼
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Avago Technologies International Sales Pte Ltd
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Zyray Wireless Inc
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Abstract

本发明涉及一种嵌入式防护网的系统和方法。嵌入式防护网包括设置在用于传送敏感信号的焊线周围的多条保护焊线。保护焊线在竖直方面高于信号焊线。保护焊线连接于基底上的外连接点，而信号焊线连接于内连接点，从而在信号线周围构成一焊线笼。本发明还提供一种封装级保护。示例性的安全封装包括：带有多个连接件的基底，所述多个连接件围绕着设置在所述基底上表面的晶片。网栅晶片包括多个网栅晶片焊盘，其连接于晶片的上表面。焊线从网栅晶片焊盘连接至基底上的连接件，从而构成一围绕该晶片的焊线笼。

Description

嵌入式封装防篡改网栅
技术领域
本发明涉及集成电路器件的安全保护，更具体地说，涉及一种集成电路器件的物理保护。
背景技术
一些类型的器件通常易成为攻击的目标。例如，存储有密钥或其他安全数据的芯片或处理安全事务(例如信用卡事务)的芯片尤其受到攻击者的关注。有一种类型的物理攻击(称为围墙攻击)是刺穿器件的封装外壳，物理地进入器件。在这类物理攻击中，封装体被打开，塑封料被移除或蚀刻掉。之后，攻击者使用探针进入芯片或器件的内部。如此，攻击者就能够探测和/或控制芯片内部信号。
因此，需要一种封装级安全保护方案，结合逻辑保护、嵌入式物理安全保护测量，以及对重要数据和信号进行篡改检测。
附图说明
附图作为说明书的一部分，用于图示本发明的实施例，并结合文字描述来解释本发明的原理，以帮助进一步理解本发明。附图中：
图1是现有技术中典型的封装保护的示意图；
图2是依据本发明较佳实施例的带有焊线封装安全保护的封装的截面图；
图3是依据本发明较佳实施例的部分封装的俯视图；
图4是依据本发明较佳实施例的相邻交错排列焊盘的俯视图；
图5是依据本发明较佳实施例的封装的示意图，其中带有多个篡改检测电路；
图6是依据本发明较佳实施例的晶片的示意图，其中，在晶片一部分的上方设置有检测网栅；
图7是依据本发明较佳实施例的晶片的安全区域的截面图；
图8是依据本发明较佳实施例的保护网图案的示意图；
图9是依据本发明较佳实施例的另一种保护网图案的示意图；
图10是依据本发明较佳实施例的单层保护网的示意图；
图11和图12是仅带有机械安全保护的堆叠晶片(die)实施方案的示意图；
图13和图14是依据本发明较佳实施例的堆叠晶片保护实施方案的示意图；
图15和图16是依据本发明较佳实施例的封装堆叠(package-on package)实施方案的示意图。
以下将结合附图对本发明做进一步说明。附图中，相同的附图标记表示相同或功能相似的要素。
具体实施方式
1.0概述
芯片(chip)或器件的重要部件可能会遭受来自封装体的顶部、侧边或底部的攻击。传统技术通常是在一个或多个芯片的外部构建一保护盒，但这只能使苾片或器件不受物理攻击，而不能提供对重要信号的逻辑保护。图1所示为封装保护的示例性传统技术的示意图。如图1所示，封装100具有一个顶部电路板102、相对顶部电路板102呈90度安装的第一侧边电路板104、同样相对顶部电路板102呈90度安装的第二侧边电路板106、以及底部电路板108。网栅贯穿电路板围墙(enclosure)。该围墙包围了所有的被保护部件(称为“芯片包”)。这种方案使得产品制造困难并且成本高。
本发明的实施例提供了一种防护来自封装体的顶部、侧边或底部攻击的保护方案。第2节中描述的焊线保护实施例提供了一种防护和检测来自封装体侧边攻击的保护方案。顶部保护实施例(例如堆叠晶片和封装堆叠)提供了防护和检测对封装体顶部进行的攻击的保护方案，将在第4节中进行描述。第4节中描述的封装堆叠的实施例还提供了对侧边攻击的物理防护。对来自底部攻击的防护是通过设置在基底(晶片安装在其上)中的板级网(board level mesh)来实现的。板级网可以采用常规的制造技术来实现。
2.0焊线保护(Bond Wire Protection)
图2是依据本发明较佳实施例的带有焊线封装安全保护的封装200的截面图。焊线封装防护在传送敏感(sensitive)芯片信号的焊线周围有效地构建了保护焊线的线笼或网栅。这种保护焊线线笼增加了使用探针来探测未检测的受保护信号的难度。
封装200包括安装在基底204上的一个或多个集成电路(IC)晶片202。在一个实施例中，晶片202是集成安全处理器，具有芯片处理器上的嵌入式系统和多个外围装置。例如，晶片可包括敏感信号输入/输出装置，诸如磁条阅读器、智能卡输入/输出、信用卡阅读器、安全键盘和或触摸屏。在一个实施例中，封装的基底是多层板(例如4层)，用于将焊线信号传送至封装焊球206。
在一个实施例中，封装200在器件的I/O焊盘环中使用交错排列的焊盘(staggered pad)。用于敏感(或受保护)信号的焊盘(也称为“信号焊盘”)布置在外错(stagger-out)焊盘上(图中未示出)。外错焊盘位于晶片的最远边。保护焊线网布置在内错(stagger-in)焊盘上，内错焊盘与外错焊盘相邻。内错焊盘(图中未示出)位于外错焊盘和外错(或“信号”)焊线250之后(behind)。内错焊线(也称为“保护焊线”)240成形为在竖直方向高于外错焊线。因此，保护焊线为外错(敏感信号)焊盘和焊线250提供了垂直和水平两个方向上的保护。敏感信号在离开由保护焊线构成的保护笼之前被传送至基底中。如图2所示，该设计中，保护焊线构成的保护笼围绕并保护着敏感信号。
内错保护焊盘(图中未示出)由焊线焊盘(wire pad)构建成。焊线焊盘与基底或相邻焊盘的电源层不相连。保护焊盘只连接于晶片上的绝缘金属和绝缘通孔(vias)。在一个实施例中，保护焊线240连接成一个或多个保护电路。篡改信号(tamper signal)流经每一个保护电路到达检测电路。为获得更好的防护，保护电路的驱动焊盘可从晶片202的保护安全区域(如以下第3节中所描述)驱动。检测电路可以配置成能够检测到保护电路中出现的断路或短路。检测电路还可以配置成保护电路中的其他特性的改变，诸如电容或电阻的改变。
可使用加密或认证技术对离开芯片的信号(经由信号焊线250)进行逻辑保护。封装200还可以包括集成物理保护，包括频率监视、电压电视、温度传感和传感网，用于保护某些敏感区域中的芯片。
如本领域技术人员所知悉，焊球206排列有多行。在实施例中，安全敏感信号被安排在距离焊球阵列外边至少两行深处。较低敏感信号可安排在距离封装外边至少一行深处。
图3是依据本发明较佳实施例的部分封装300的俯视图。封装300包括晶片(例如图2中的晶片202)上的多个焊盘302a-p。在实施例中，焊盘302，以环形方式布置(注意图3中只示出了环的一部分)。焊盘302通常包括焊盘连接点(pad contact)304。一组焊盘302用于焊线保护(称为“保护焊盘”)。其余焊盘302(图3中阴影表示)可用于芯片功能。例如，焊盘302c、e、g、j、1和n是芯片功能(外错)焊盘，其余焊盘是保护(内错)焊盘。
虽然示为内错焊盘，网栅连接焊盘可以选择为内错或外错。焊盘的交错配置使得引脚密度可以更高，从而使得保护焊线可以布置得相互之间更加靠近，增强了对被包围的信号焊线的物理保护。另外，网栅连接焊盘可以是串联(in-line)焊盘。还有，如图3所示，可选地，焊盘可以重叠。
图3还示出了部分封装基底，用于为封装提供路由。在一个实施例中，由基底上的一块小印刷电路板(PCB)提供路由。如图3所示，封装基底包括一组外连接点(outer contact)316a-h和一组内连接点(inner contact)314a-h。晶片上的焊盘接点304可通过焊线连接至基底连接点。基底连接点一般连接于焊球206(如图2所示)。
保护焊线340a-n通常连接于该组外连接点316。传送物理保护信号(诸如信号380a)的焊线通常在每一边都有保护焊线。用于这些保护焊线的基底外连接点之间的有效垂直网栅间距318是由保护(内错)焊盘和信号(外错)焊盘之间的最小间距而决定的。在图3所示的例子中，第一物理保护信号380a从焊盘连接点304c经由信号焊线350a传送至基底内连接点314a。要想接入(或访问)基底内连接点314a，攻击者必须恰好地探入保护焊线340b的340c之间。因此，垂直网络间距越小，保护焊线靠得越近，从而使信号380a得到更强的物理保护。垂直网栅间距还可以通过增大基底外连接点316和基底内连接点314之间的水平间距319来减小。
图4是依据本发明较佳实施例的相邻交错焊盘的俯视图。交错焊盘402c是敏感信号(外错)焊盘，并接收保护信号(例如信号308a)。交错焊盘402b和402d是保护(内错)焊盘。在图4所示的实施例中，交错焊盘402b-d没有重叠。保护焊线440b和440c在垂直方向高于信号焊线450a。在一个实施例中，交错焊盘402为30μm宽，保护和信号焊线为0.9密耳(千分之一英寸)厚，在两条保护焊线之间生成37.14μm的有效焊线间距418。在本实施例中，水平间距仅为7.14μm。
如图3所示，保护(内错)焊线(例如焊线340b和340c)保护信号焊线(例如信号焊线350a)、信号焊盘接点(例如304c)和敏感信号(外错)焊盘的信号迹线(trace)。此外，晶片上保护(内错)焊盘之间的电路被连接起来以覆盖外错焊盘的信号迹线。在一个实施例中，连接可以形成一种图案(例如曲折形状)，如连接390a。使用图案迹线能够对晶片上的敏感信号迹线得到额外的物理保护。
在示例性的封装300中，一组信号380a-d被指定需要物理保护。另一组信号385被指定为不需要额外的物理保护。这些信号可以通过逻辑安全防护来保护和或被认为不需要额外的物理安全防护。如图3所示，在一个或多个物理保护信号380a-d周围构建有保护电路。从顶部朝下看，图3中的保护电路形成曲折图案。
在图3所示的保护电路中，驱动器(例如外部网栅驱动电路)连接于驱动焊盘302a。申请号为12/210013、名称为“网栅保护”的美国专利申请描述了一种示例性网栅驱动电路，本申请参考并结合其全部内容。驱动焊盘302a可以从位于晶片上的安全区域中的外部网栅驱动电路驱动。驱动焊盘302a可以一直处于激活状态，而不管受保护的信号是处于何种状态(带电或未带电)。
驱动焊盘302a可作为驱动焊盘302a和检测焊盘302p之间的唯一连接线。这条线使用焊线构成，以将驱动焊盘302a(经由焊盘接点304a)连接至基底连接点316a。基底连接点316a经由封装基底中的连接件连接于基底连接点316b。保护焊线连接于基底连接点316b，以保护晶片上的焊盘302b。在一个实施例中，焊盘302b是未固定在基片上的模拟焊盘(analog pad)。在保护电路中使用模拟焊盘使能使用两种不同的电压电平。采用这种配置，当芯片的其他部分断电时保护/篡改检测电路仍保持活跃状态。
焊盘接点304b利用晶片上的金属连接件(例如连接迹线)连接于焊盘接点304d。如上所述，这一金属连接件为传送受保护信号380a的信号迹线提供额外的物理安全防护。保护焊盘302b和d之间的信号焊盘302c物理地接收受保护信号380a。一条焊线将保护焊盘302d连接至基底连接点316c(其与基底连接点316d相连)。如此，保护电路有效地绕开不受保护的信号385。一条焊线将基底连接点316d连接至保护焊盘302i，保护焊盘302i利用金属连接件连接至保护焊盘302k，保护焊盘302k再通过焊线离开晶片焊至基底连接点316e。用于物理地传送受保护信号380b的信号焊线由保护焊线340d和340e包围。这一曲折图案延续直到最后一个基底外连接点316h被连接至检测焊盘302p，从而构建成篡改检测电路。来自检测焊盘304p的信号被路由至外部检测电路。申请号为12/210013的美国专利申请描述了一种示例性外部检测电路。本实施例中，曲折网栅图案延伸将整个晶片覆盖。
焊盘环(图3示出了其中的一部分)具有一个或多个间隔。该间隔可用来隔离一个或一组焊盘。例如，焊盘302a和焊盘302b之间由焊盘间隔隔离，彼此之间没有连通。在该实施例中，焊盘302a和焊盘302b处于不同的电源层。作为选择，可以提供具有连通性的焊盘间隔，例如在焊盘302h和焊盘302i之间的间隔中是连通的。
图3所示的是单个保护电路，用于为多个物理地受保护信号提供保护的。如本领域技术人员所知悉，在芯片上也可以使用多个保护电路。例如，用户可能希望在每一个敏感信号周围进行篡改监测。这种配置使得能够检测到攻击者企图接入(或访问)一个器件/功能(例如磁条阅读器)而不是另一个器件/功能(例如安全键盘)。注意在其他实施例中，芯片可以只用单个保护电路来对整个芯片进行保护。
图5是依据本发明较佳实施例的部分封装500的示意图，其中带有多个篡改(tamper)检测电路。图5特别地示出使用两种不同极性的驱动器的保护焊盘之间的连接。具有第一极性的连接用实线表示。具有第二极性的连接用虚线表示。
封装500包括两个驱动焊盘502a、b(一种极性一个驱动焊盘)和两个检测焊盘502x、y(一种极性一个检测焊盘)。检测电路用于为敏感信号580a-f提供焊线检测保护。
因为存在两个分离的篡改检测电路(全部的焊线)，在图5所示的受保护信号区域周围需要偶数个开/关(on/off)焊盘590。在一个实施例中，信号区域的最后一个焊盘可以路由回晶片，以保护从一个受保护焊盘区域到下一个区域的长信号迹线。
此外，两个篡改检测电路在封装上的路由可以交替从设置在内部到设置在外部，以连接下一条焊线。这种配置防止攻击者在封装基底层短路信号。晶片上的金属连接也可以类似的交替。相反的篡改检测电路极性进一步可以在晶片和封装的水平层对齐，使得很难绕开信号(或旁路信号)。
3.0晶片网栅保护(Die Mesh Protection)
晶片，如图2所示的晶片202，还可包括各种内部网栅保护。图6是依据本发明较佳实施例的晶片602的示意图，其中，在晶片一部分的上方设置有检测网栅。晶片602包括器件逻辑670、可选擦除电池备份RAM(BBRAM)672和位置晶片602角落上的网栅680。网栅680覆盖了晶片的安全区域。该网栅至少提供双层检测网栅。角落位置的设置使得攻击者很难在不损坏BBRAM供电焊线的情况下回蚀(etch back)封装。另外，如果晶片的安全区域包括有温度监视器，远离器件动态逻辑的位置设置提供了热隔离。如本领域技术人员所知悉，网栅680(及其关联的安全区域)可以位于晶片的任何位置。
在活跃的晶片区域上方，晶片602还可包括单层或双层金属网栅。增加的金属层可以由篡改检测信号驱动，该篡改检测信号来自位于晶片安全区域中的篡改逻辑。
图7是依据本发明较佳实施例的晶片的安全区域700的截面图。安全区域700包括RDL层740、M6层730、M5层720和基层710。安全区域700由金属层6(M6)730网栅保护，其中，到网栅的连接做在M5层720中。网栅连接总是处于保护网栅的下方。RDL层740提供了接地层，其在M6层730的活跃网栅的上方。接地层提供了物理屏障(physical blind)以及接地的短路径，其可由M6层网栅检测到。
图8是依据本发明较佳实施例的保护网栅图案800的示意图。保护网栅图案800在相反极性之间使用曲折线(或Z形线)。图9是依据本发明较佳实施例的另一种保护网栅图案900的示意图。这种图案利用额外的极性，增加了黑客成功绕开网栅的难度。在图9所示的网栅上增加额外的层，其中P2和P4设置在最小间隔开的P1和P3信号上，且图案重复但有偏移，进一步提高了攻击者攻击过程(jumper process)的难度。
图10是依据本发明较佳实施例的单层保护网1000的示意图。网栅1000由多个复杂图案组成，使得更加难以绕开。在一个实施例中，网栅1000设置在RDL中。在该实施例中，焊线的焊盘连接在M6层，以驱动和检测由网栅线构成的篡改电路。作为选择，单层网栅1000通过在M6驱动器和检测焊盘之间增加一经过层(a via layer)来规划，使用M7为连接层，RDL作为网栅。
此外，双层网栅可用来提供上层网栅保护下层网络连接。理想情况是，上层网栅连接由下层网栅来保护。
4.0封装级保护(Package Level Protection)
之前描述的焊线保护可以防止从侧面或角落(at angles)对封装的攻击。然而，攻击也可能从顶部发起(例如敲击晶片内侧)。因此需要一种能够增加这类攻击难度的技术，以及能够检测顶部攻击，采取保护措施诸如擦除敏感信息(例如加密密钥资料)。
图11-16示出了依据本发明实施例的封装级保护。封装级保护可与之前描述的焊线保护和或晶片网栅保护结合使用。作为选择，封装级保护也可单独使用。封装级保护可以采用堆叠晶片方案(如4.1节所描述)或采用封装堆叠(package-on-package)方案(如4.2节所描述)来实现。
通常，防护和检测对封装顶部的攻击是通过位于晶片上的网栅来实现的。这些内部晶片网栅技术的限制是无论客户是否需要，网栅保护都要在每一个晶片中制作。图13-16的实施例实现了与晶片分离的网栅保护。在这些实施例中，网栅保护是作为封装的一部分，是在晶片的外部
4.1堆叠晶片方案
图11和图12是仅带有机械安全保护的堆叠晶片(die)实施方案的示意图。图11中的封装1100包括伪晶片(dummy die)1140，其面积等于或大于晶片1102的面积。间隔晶片(spacer die)1150将伪晶片1140与晶片1102分隔。因此，要访问晶片1102，攻击者必须物理地移除全部或部分伪晶片1140和间隔晶片1140。图12所示的封装1200包括伪晶片1240，其面积等于或大于晶片1202的面积。伪晶片1240直接堆叠在晶片1202上面。即，封装1200不包括间隔晶片。图11和图12的实施例只提供物理保护。因此，这些封装的安全性没有检测可能会遭受破坏。这些实施例主要增加了从顶部攻击的难度。
图13和图14是依据本发明较佳实施例的堆叠晶片保护实施方案的示意图。封装1300和1400包括网栅晶片1360、1460，其面积等于或大于晶片1302、1402的面积。如此，网栅晶片1360、1460为整个低层晶片1302、1402提供了多层保护网栅。在图13所示的实施例中，间隔晶片1350将网栅晶片1360与晶片1302分隔。在图14所示的实施例中，网栅晶片1460直接堆叠在晶片1402上。在一个实施例中，网栅晶片1360、1460包括网栅。封装1300和1400中的焊线1320、1420分别包围着整个晶片，并在基底和网栅晶片之间提供连接。焊线1320、1420比焊球包围(如下面结合图15、16所进行的描述)所提供的保护更大，这是因为它们比焊球间隔的更紧密。
图13和图14实施例中的堆叠晶片使用顶部网栅晶片1360、1460作为网栅在整个晶片是提供保护。在这些实施例中，网栅可以使用外部网栅驱动电路从受保护的低层晶片1302、1402驱动。在实施例中，在顶部网栅晶片1360、1460中可以提供额外的功能(例如存储器)。
42.封装堆叠(package-on-package)方案
图15和图16是依据本发明较佳实施例的封装堆叠(package-on package)实施方案的示意图。在这些实施例中，使用带有网状栅格的网栅基底来保护晶片1502、1602。在封装1500中，晶片1502由连接于网栅基底1570的焊球阵列包围。另外，晶片1502被密封在塑封材料1506中。塑封材料1506中也由焊球阵列包围。如本领域技术人员所知悉，为对塑封材料进行模塑，需要定制塑封帽。焊球阵列中焊球的高度必须大于塑封材料的高度。网栅基底1570堆叠在焊球阵列上。网栅基底1570完全覆盖住晶片1502。
在封装1600中，无需定制的模塑塑封材料。作为替代，网栅基底1670的焊球阵列连接于下基底1604上塑封材料层中的间隔层。在该实施例中，焊球阵列的高度与晶片或塑封层的高度的关系不大。
图15和16的封装堆叠实施例使用顶部封装网栅基底在整个晶片上覆盖网栅。这样，在这些实施例中，不需要其他的晶片。在这些实施例中，多层网栅可使用位于晶片安全区域中的外部网栅驱动电路从受保护的下层晶片来驱动。与上层网栅基底的连接使用封装之间的焊球来实现。在一个实施例中，焊球布置在封装的四边，且具有最小的焊球间距和交替的极性。焊球的这种设置方式提供了对侧面攻击的额外防护。因此，图15和16的实施例可以不与前述焊线保护实施例一起使用。
5.0结束语
本发明是通过几个具体实施例进行说明的，本领域技术人员应当明白，在不脱离本发明范围的情况下，还可以对本发明进行各种变换及等同替代。另外，针对特定情形或具体情况，可以对本发明做各种修改，而不脱离本发明的范围。因此，本发明不局限于所公开的具体实施例，而应当包括落入本发明权利要求范围内的全部实施方式。

Claims (6)

1.一种集成电路封装，其特征在于，包括：
晶片，其包括：
设置在所述晶片的上表面的第一组晶片焊盘，所述第一组晶片焊盘中的每一个晶片焊盘用于接收晶片信号，及
设置在所述晶片的上表面的第二组晶片焊盘，所述第二组晶片焊盘与所述第一组晶片焊盘绝缘；及
基底，其具有设置在所述基底的上表面的一组外连接点和设置在所述基底的上表面的一组内连接点，
其中所述第一组晶片焊盘中的每一个晶片焊盘经由信号焊线连接于所述一组内连接点中的一内连接点，及
其中所述第二组晶片焊盘中的每一个晶片焊盘经由保护焊线连接于所述一组外连接点中的一外连接点，从而在所述信号焊线周围构建成焊线笼；
所述第一组晶片焊盘与所述第二组晶片焊盘交错排列；
所述保护焊线成形为在竖直方向高于信号焊线；
所述第二组晶片焊盘中的多个晶片焊盘和所述一组外连接点中的多个外连接点连接构成篡改保护电路；
所述多个信号焊线中的信号焊线传送受保护信号；
第一保护焊线与受保护信号焊线的第一侧相邻，第二保护焊线与受保护信号焊线的第二侧相邻；
与所述第一保护焊线关联的外连接点和与所述第二保护焊线关联的外连接点之间相隔最小垂直网格间距；
与所述受保护信号焊线关联的晶片焊盘包括受保护信号迹线；
与所述第一保护焊线关联的第一晶片焊盘和与所述第二保护焊线关联的第二晶片焊盘经由设置在受保护信号迹线上方的连接线而连接；
所述连接线形成的图案覆盖部分信号迹线。
2.根据权利要求1所述集成电路封装，其特征在于，在所述第二组晶片焊盘中的所述多个晶片焊盘包括驱动焊盘和检测焊盘。
3.根据权利要求2所述集成电路封装，其特征在于，所述驱动焊盘连接于外部网格驱动电路，所述检测焊盘连接于外部篡改检测电路。
4.根据权利要求3所述集成电路封装，其特征在于，所述晶片进一步包括：安全区域。
5.根据权利要求4所述集成电路封装，其特征在于，所述外部网格驱动电路和所述外部篡改检测电路包括在所述晶片安全区域中。
6.根据权利要求3所述集成电路封装，其特征在于，所述外部网格驱动电路和所述外部篡改检测电路包括在相同的逻辑电路中。
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EP2220679A4 (en) 2014-02-26
HK1149365A1 (en) 2011-12-16
US8502396B2 (en) 2013-08-06
US20150137340A1 (en) 2015-05-21
US8890298B2 (en) 2014-11-18
US20140035136A1 (en) 2014-02-06
US20090146270A1 (en) 2009-06-11
CN101889344A (zh) 2010-11-17
KR20100086083A (ko) 2010-07-29
KR101083445B1 (ko) 2011-11-14
WO2009073231A1 (en) 2009-06-11

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