TW201809706A - 晶片封裝件的篡改檢測 - Google Patents

晶片封裝件的篡改檢測 Download PDF

Info

Publication number
TW201809706A
TW201809706A TW106112180A TW106112180A TW201809706A TW 201809706 A TW201809706 A TW 201809706A TW 106112180 A TW106112180 A TW 106112180A TW 106112180 A TW106112180 A TW 106112180A TW 201809706 A TW201809706 A TW 201809706A
Authority
TW
Taiwan
Prior art keywords
wafer
lines
item
patent application
bonding pads
Prior art date
Application number
TW106112180A
Other languages
English (en)
Other versions
TWI660184B (zh
Inventor
理查Ｓ 格拉夫
伊拉 Ｄ Ｂ 賀爾
法瑞登 帕克巴茲
沙巴斯欽Ｔ 凡托尼
Original Assignee
格羅方德半導體公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 格羅方德半導體公司 filed Critical 格羅方德半導體公司
Publication of TW201809706A publication Critical patent/TW201809706A/zh
Application granted granted Critical
Publication of TWI660184B publication Critical patent/TWI660184B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/44—Testing lamps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H01L2224/85207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

本發明揭示具有改進防篡改的晶片封裝件以及使用此類晶片封裝件來提供改進防篡改的方法。導線架包括晶片附著座、外引腳，以及位於該外引腳與該晶片附著座之間的內引腳。晶片附著至該晶片附著座。該晶片包括表面，該表面具有外邊界以及鄰近該外邊界佈置的接合墊。第一多條線自該外引腳延伸至該晶片的該表面上的相應位置，該些位置相對該接合墊在該外邊界的內部。篡改檢測電路與該第一多條線耦接。第二多條線自該內引腳延伸至該晶片上的該接合墊。該第二多條線位於該導線架與該第一多條線之間。

Description

晶片封裝件的篡改檢測
本發明關於晶片封裝，尤其關於晶片的防篡改封裝件以及使用此類封裝件提供防篡改的方法。
晶片封裝在產品保護及晶片安全方面起作用。例如，晶片封裝件可保護被封閉的晶片免受損傷。至於晶片安全，可應用防篡改技術來防止攻擊者偷偷存取晶片並阻止逆向工程。
需要以改進防篡改為特徵的晶片封裝件以及使用此類晶片封裝件的方法。
依據本發明的一個實施例，一種結構包括導線架，其具有晶片附著座、多個外引腳，以及位於該外引腳與該晶片附著座之間的多個內引腳。晶片附著至該晶片附著座。該晶片包括表面，該表面具有外邊界以及鄰近該外邊界佈置的多個接合墊。第一多條線自該外引腳延伸至該晶片的該表面上的相應位置，該些位置相對該接合墊在該外邊界的內部。篡改檢測電路與該第一多條線耦接。第二多條線自該內引腳延伸至該晶片上的該接合墊。該第 二多條線位於該導線架與該第一多條線之間。
依據本發明的另一個實施例，提供一種方法以檢測附著至導線架上的晶片附著座的晶片的篡改的方法。該方法包括：向第一多條線發送第一信號，該第一多條線自該導線架上的多個外引腳延伸至該晶片的表面上方的相應位置；向第二多條線發送第二信號，該第二多條線自該導線架上的多個內引腳延伸至晶片的該表面上的多個接合墊；以及通過篡改保護電路監控該第一信號。
10‧‧‧晶片封裝件
12‧‧‧晶片
14‧‧‧導線架
16‧‧‧外殼
17‧‧‧外表面
18‧‧‧晶片附著墊、晶片附著座
20‧‧‧內引腳、引腳
20a‧‧‧表面
22‧‧‧外引腳、引腳
22a‧‧‧表面
24‧‧‧層
26‧‧‧側邊
30‧‧‧線
31‧‧‧端部、端
32‧‧‧線、導線
33‧‧‧端部、端
34‧‧‧接合墊
35‧‧‧導電路徑
36‧‧‧接合墊
38‧‧‧表面
40‧‧‧基板
42‧‧‧導電路徑
44‧‧‧接地平面
46‧‧‧功率平面
50‧‧‧篡改保護電路
52‧‧‧發送器電路
54‧‧‧接收器電路
56‧‧‧時鐘電路
包含於並構成本說明書的一部分的附圖說明本發明的各種實施例，並與上面所作的本發明的概括說明以及下面所作的實施例的詳細說明一起用以解釋本發明的實施例。
第1圖顯示依據本發明的一個實施例的晶片封裝件的剖視圖。
第2圖顯示第1圖的晶片封裝件的頂視圖，其中，出於說明目的移除了外殼。
第3圖顯示依據本發明的一個實施例利用連接晶片與封裝件的線的篡改檢測系統的示意圖。
請參照第1、2圖並依據本發明的一個實施例，晶片封裝件10包括晶片12、導線架14，以及具有外表面17的外殼16。晶片12包括一個或多個積體電路，其具有通過使用前端工藝(front-end-of-line；FEOL)製程形成 的裝置結構。該FEOL製程可包括例如互補金屬氧化物半導體(complementary-metal-oxide-semiconductor；CMOS)製程，該製程用以構建經耦接以實施邏輯門及其它類型數位電路的p型與n型場效應電晶體的組合。晶片12包括建立外邊界或周邊的側邊26，以及被側邊26圍繞或限制的表面38。
導線架14包括晶片附著墊或座18，其相對內引腳20及外引腳22居中設置。導線架14可由金屬(例如銅或銅合金)的薄層組成。晶片12通過例如導熱和/或導電黏附劑的層24附著至晶片附著座18。晶片附著座18的不同側邊分別與晶片12的側邊26對齊。可將晶片封裝件10表面貼裝至基板40，例如印刷電路板或層疊基板。晶片附著座18為從晶片12(當開啟時)至基板40的熱傳遞提供低熱阻路徑。
可將內引腳20及外引腳22佈置成列，該些列與晶片12的側邊26的其中一條或多條相鄰設置並向外間隔開。在晶片12及晶片附著座18呈矩形的該代表性實施例中，引腳20、22的列與晶片12的所有側邊26相鄰設置且不同的列可與晶片12的相應不同側邊26平行排列。在一個替代實施例中，引腳20、22可與晶片12的部分側邊26相鄰設置。例如，引腳20、22可僅與晶片12的側邊26的其中相對一對相鄰設置。在晶片12的各側邊26上，內引腳20被橫向設置成它們的相應列，其位於包括外引腳22的相鄰列與晶片附著座18之間，以使內引腳20比外引 腳22更靠近晶片12及晶片附著座18。引腳20、22可具有不同的尺寸及不同的間距。引腳20、22的相應表面20a、22a與晶片12的表面38面向同一方向取向，以促進打線接合(wirebonding)製程。
在一個實施例中，晶片封裝件10可為多列四方扁平無引線(Qaud Flat No-leads；QFN)晶片封裝件或另一種類型的多列扁平無引線封裝件。在一個特定實施例中，晶片封裝件10可為雙列QFN晶片封裝件或另一種類型的雙列扁平無引線封裝件。在具有不止兩列引腳的晶片封裝件中，將額外列的引腳設置於內引腳20與外引腳22之間，以將外引腳22設置為與晶片12及晶片附著座18具有最大間距的周邊最外列。
在通過FEOL製程形成積體電路以後，晶片12經歷中間工藝(middle-of-line；MOL)製程及後端工藝(back-end-of-line；BEOL)製程，以形成堆疊佈置的多個金屬化層級並包括位於最上金屬化層級中的接合墊34、36。接合墊34、36可由銅、鋁，或這些金屬的合金組成，且可通過例如金屬沉積層的減成蝕刻(subtractive etching)形成。接合墊34、36位於晶片12的頂部表面38的BEOL互連結構的最上金屬化層級中，且可供打線接合製程使用。接合墊34可用以向晶片12的積體電路提供信號、時鐘、功率等的導電路徑。在一個實施例中，接合墊36不與晶片12的積體電路連接，而是接合墊36的相鄰對通過BEOL互連結構中的導電路徑35(示意顯示於第2圖中)連接。導 電路徑35可位於例如與最上金屬化層級相鄰的金屬化層級中的晶片12的頂部表面38下方。在一個替代實施例中，接合墊36的其中一個或多個可與作為晶片12上的積體電路通過FEOL製程所形成的一個或多個篡改保護電路耦接，如下所述。
線30、32沒有連接至位於例如晶片堆疊中的多層上的位置。相反，晶片12的表面38提供共平面，在該共平面中將所有線30的端部附著至晶片12並設置所有線32的端部33。
接合墊34、36位於由側邊26建立的晶片12的外邊界的內部的表面38上，而接合墊36位於接合墊34的內部。接合墊34在由側邊26建立的外周邊或邊界附近的晶片12的邊緣設置，且可被佈置成與不同的側邊26相鄰的列。內引腳20及接合墊34分別比外引腳22及接合墊36更靠近該外邊界。接合墊36位於接合墊36的內部，且內引腳20也橫向位於外引腳22的內部。可將接合墊36佈置成列，該些列成一角度朝向晶片12的頂部表面38的中心並相對包含接合墊34的列。接合墊36的排列促進提供篡改保護的能力。
線30自附著至導線架14上的內列中的內引腳20的一端延伸至附著於晶片12上的接合墊34的相對端。線30用以在晶片12與基板40之間提供互連，該互連在該晶片的外部環境與晶片12上的積體電路之間提供電性路徑。線30的數目及引腳20的數目可依據晶片封裝件 10及晶片12的設計而變化。
線32自附著至導線架14上的外列中的外引腳22的一端31延伸至附著於晶片12上的接合墊36的相對端33。線32的數目及密度以及引腳22及接合墊36的數目及密度可依據提供篡改保護的覆蓋範圍的需要而變化。
線30、32可由具有細直徑的金屬例如金或銅組成且可通過打線接合製程施加。例如，該打線接合製程可依賴于打線接合工具，該工具行進至接合墊36的其中之一的位置並通過使用熱和/或超音波能量將位於線32的端部33的球形球附著至接合墊36。隨著端部33被附著至接合墊36，該打線接合工具向外引腳22的其中之一以弧形運動方式運動，同時在運動期間分配線32的長度。形成針腳式接合，以將線32的相對端31與外引腳22的其中之一接合。在一個替代操作次序中，可先形成至外引腳22的該針腳式接合並可最後形成至接合墊36的接合。
位於引腳22的端部31與接合墊36的端部33之間的線32的長度獲得與呈弧形運動的該打線接合工具的運動相關的接合後形狀。除其它因素以外，該弧形運動確定線32沿其在端部31、33之間的長度的標高或高度。該打線接合工具的該運動經編程以使線32與線30相比，相對晶片12的表面38具有較高的標高。尤其，線32自外引腳22在線30上方走線，以使線32的弧在線30的弧上方形成罩或傘。在該打線接合製程期間，線32都可以同一 弧形運動形成，以使線32相對所有線30所共有的較低標高具有同一較高標高，並使線32的弧的長度比線30的弧的長度長。
由於線32圍繞側邊26的佈置，線32形成位於線30上方的獨立導體格柵或網格。線30、32垂直位於與導線架14耦接的基板40與外殼16的外表面17之間。穿過外殼16以從外殼16的外表面17存取線30的任意企圖將需要探針經過線32的相鄰一對之間，以接觸線32的其中一條或多條，或者鄰近線32的其中一條或多條。相對晶片12，線30在由側邊26建立的晶片12的外邊界的內部位置水平且垂直位於線32與晶片12的表面38之間。在一個實施例中，線32可向晶片12的表面38的幾何中心延伸，以覆蓋表面38的大部分或位於其上方。最佳如第2圖中所示，線32可覆蓋晶片12的表面38的各象限的大部分且線30可與位於各該象限中的接合墊34運接。相對導線架14，線30垂直且水平位於線32與晶片封裝件10的外殼16的外表面17之間。
晶片12、導線架14以及線30、32被封裝於外殼16內部。外殼16可通過晶片封裝製程形成，在通過打線接合製程形成線30、32以後，該晶片封裝製程除其它操作以外施加並固化環氧模壓複合材料。外殼16用以防止對線30和/或晶片12造成物理損傷或腐蝕，且還可限制存取晶片12及線30。
基板40可包括金屬化，其定義用以將外引 腳22的相鄰對耦接在一起的導電路徑42。線32可通過基板40的導電路徑42及晶片12的導電路徑35菊鏈或串聯耦接。由晶片12的BEOL互連結構中的導電路徑35提供的互連以及由基板40中的導電路徑42提供的互連允許同時篡改監控優化數目的線32。基板40可包括額外的金屬化(例如接地平面44以及功率平面46)，其獨立于用以連接接合墊36的相鄰對的導電路徑42。
線32提供檢測物理攻擊的篡改的能力。例如，線32可允許檢測移除晶片封裝件10的物理篡改企圖。又例如，線32可允許檢測當線32被探針或穿入外殼16中的另一個外來物體的物理接觸以試圖感測線30所載的I/O信號時的篡改。該物理篡改企圖可引起線32的屬性變化，例如如果一條或多條線32被接觸的電阻變化或者因導電外來物體靠近一條或多條導線32而引起的電容變化。
請參照第3圖，其中，類似的元件符號表示第1至2圖中的類似特徵且依據本發明的一個實施例，線32可與篡改保護電路50耦接並可結合篡改保護電路50充當感測裝置，用以檢測入侵篡改。入侵篡改可包括但不限於破壞外殼16或自基板40移除晶片12，且可通過使用微探測台的探針進行嘗試。篡改保護電路50可位於晶片12上或晶片12外，例如位於基板40上。篡改保護電路50可經配置以響應自晶片12上的積體電路接收的指令或編程設置以及/或者自晶片外源(例如與晶片12在同一基板40上的源)接收的其它指令或輸入向線向線32傳輸電性信 號。
篡改保護電路50可包括發送器電路52，該發送器電路經配置以將靜態信號或瞬態信號作為脈衝發送，該脈衝經過線32到達接收器電路54，該接收器電路經配置以接收經過線32的該信號。由於線32菊鏈串聯，因此該信號可經過所有線32。該信號可被配置為偽信號，該偽信號經脈衝化以模仿傳輸於線30上的實際信號的頻率及不規則性。偽信號的使用可使攻擊者難以檢測到線32及其上的信號正被用於篡改保護目的。偽信號尤其可有效打擊對線30所載信號的竊聽。
由發送器電路52提供的信號可基於在開環狀態中操作的運算放大器由電壓檢測電路產生。可將變化輸入電壓作為模擬電壓電平輸入該運算放大器的一個端口，並將參考電壓輸入該運算放大器的另一個端口。自該運算放大器向線32輸出的信號是基於不同模擬電壓電平之間的比較，且可為一系列脈衝，其振幅在正供應軌線電壓及負供應軌線電壓範圍內變化。
篡改保護電路50可經配置以確定信號經過線32的傳輸時間延遲。為此，電路52、54可與時鐘電路56耦接，該時鐘電路提供定時信息，且可於晶片12啟動時操作。接收器電路54測量從信號被發送器電路52發送至線32上的瞬間至其接收的信號延遲。可將由發送器電路52發送並在接收器電路54接收的任意給定信號的延遲與延遲儲存值或延遲值儲存窗口進行比較，該延遲儲存值或 延遲值儲存窗口可自初始測試確定。例如，由於已破壞外殼16並位於線32的其中一條或多條的探針或其它物體的靠近而引起的電容變化可導致該延遲在該儲存值或值範圍之外變化。
一旦檢測到物理篡改企圖，篡改保護電路50即可通過採取或觸發一個或多個對策來響應，例如生成使能信號以啟動防篡改操作。例如，如果線32檢測到外殼16穿透或檢測到線32的電阻或電容變化中的超限環境參數，則篡改保護電路50可經設計以觸發敏感數據歸零。歸零可能需要清除記憶體晶片的記憶體單元中的敏感儲存內容或重寫記憶體晶片的記憶體單元的其中一些或全部。或者，可停止晶片12上的處理器，可發出警報以使系統或使用者意識到該篡改事件，或者一個或多個電路塊或嵌入式軟體可防止晶片12完全操作或完全作用。
上述方法用於積體電路晶片的製造中。製造者可以原始晶圓形式(例如作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。可將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置集成，作為中間產品或最終產品的部分。該最終產品可為包括積體電路晶片的任意產品，例如具有中央處理器的電腦產品或智慧型手機。
本文中引用術語例如“垂直”、“水平”等作為示例來建立參考框架，並非限制。本文中所使用的術語“水平”被定義為與半導體基板的傳統平面平行的平 面，而不論其實際的三維空間取向。術語“垂直”及“正交”是指垂直於如剛剛所定義的水平面的方向。術語“橫向”是指在該水平平面內的方向。術語例如“上方”及“下方”用以表示元件或結構相對彼此的定位，而不是相對標高。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接，或者可存在一個或多個中間元件。如果不存在中間元件，則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件，則特徵可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭示的實施例。許多修改及變更對於所屬技術領域中具有通常知識者將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使所屬技術領域中具有通常知識者能夠理解本文中所揭示的實施例。
10‧‧‧晶片封裝件
12‧‧‧晶片
14‧‧‧導線架
16‧‧‧外殼
17‧‧‧外表面
18‧‧‧晶片附著墊、晶片附著座
20‧‧‧內引腳、引腳
20a、22a‧‧‧表面
22‧‧‧外引腳、引腳
24‧‧‧層
26‧‧‧側邊
30‧‧‧線
31、33‧‧‧端部、端
32‧‧‧線、導線
34、36‧‧‧接合墊
38‧‧‧表面
40‧‧‧基板
42‧‧‧導電路徑
44‧‧‧接地平面
46‧‧‧功率平面

Claims (20)

  1. 一種結構，包括：導線架，具有晶片附著座、多個外引腳，以及位於該外引腳與該晶片附著座之間的多個內引腳；晶片，附著至該晶片附著座，該晶片包括表面，該表面具有外邊界以及鄰近該外邊界佈置的第一多個接合墊；第一多條線，自該外引腳延伸至該晶片的該表面上的相應位置，所述位置相對該第一多個接合墊在該外邊界的內部；篡改檢測電路，與該第一多條線耦接；以及第二多條線，自該內引腳延伸至該晶片上的該第一多個接合墊，該第二多條線位於該導線架與該第一多條線之間。
  2. 如申請專利範圍第1項所述之結構，還包括：基板，該導線架附著至該基板，該基板包括經佈置以耦接該外引腳的相鄰對的多條導電路徑。
  3. 如申請專利範圍第1項所述之結構，其中，該晶片包括第二多個接合墊，各該第一多條線具有耦接至該外引腳的其中之一的第一端，該第一多個接合墊位於該晶片的該第二多個接合墊與該外邊界之間，且各該第一多條線具有耦接至該第二多個接合墊的其中之一的第二端。
  4. 如申請專利範圍第3項所述之結構，還包括： 基板，該導線架附著至該基板，該基板包括經佈置以耦接該外引腳的相鄰對的多條導電路徑。
  5. 如申請專利範圍第3項所述之結構，其中，該晶片具有互連結構，該互連結構具有多條導電路徑，且該第二多個接合墊的相鄰對通過該互連結構的該導電路徑的其中之一連接。
  6. 如申請專利範圍第5項所述之結構，還包括：基板，該導線架附著至該基板，該基板包括經佈置以耦接該外引腳的相鄰對的多條導電路徑。
  7. 如申請專利範圍第1項所述之結構，其中，該第一多條線自該外引腳向該晶片的該表面上的該相應位置以相應第一弧延伸，該第二多條線自該內引腳向該第一多個接合墊以相應第二弧延伸，且該第二弧短於該第一弧。
  8. 如申請專利範圍第1項所述之結構，還包括：基板，該導線架附著至該基板；以及外殼，具有外表面，其中，該導線架、該晶片、該第一多條線，以及該第二多條線被封裝於該外殼內部，且該導線架、該晶片、該第一多條線，以及該第二多條線位於該基板與該外殼的該外表面之間。
  9. 如申請專利範圍第1項所述之結構，其中，該內引腳橫向位於該外引腳與該晶片的該外邊界之間，該晶片的該外邊界包括多條側邊，且該內引腳與該外引腳沿 該晶片的該側邊的其中一條或多條被設置成一個或多個列。
  10. 如申請專利範圍第9項所述之結構，其中，該外引腳所設置成的該一個或多個列沿該晶片的所有該側邊佈置。
  11. 如申請專利範圍第9項所述之結構，其中，該外引腳所設置成的該一個或多個列沿彼此相對的該晶片的該側邊的其中至少兩條佈置。
  12. 如申請專利範圍第1項所述之結構，其中，該篡改檢測電路包括：接收器電路，與該第一多條線耦接；以及發送器電路，與該第一多條線耦接，該發送器電路經配置以向該第一多條線提供信號，該信號經過該第一多條線到達該接收器電路。
  13. 如申請專利範圍第1項所述之結構，其中，該篡改檢測電路包括：接收器電路，與該第一多條線耦接；以及發送器電路，與該第一多條線耦接，該發送器電路經配置以向該第一多條線提供偽信號，該偽信號經過該第一多條線到達該接收器電路。
  14. 如申請專利範圍第1項所述之結構，其中，該篡改檢測電路位於該晶片上，該晶片包括第二多個接合墊，且該第二多個接合墊將該第一多條線與該篡改檢測電路耦接。
  15. 如申請專利範圍第1項所述之結構，其中，該篡改檢測電路位於該晶片外，該晶片包括第二多個接合墊，且該外引腳將該第一多條線與該篡改檢測電路耦接。
  16. 一種用以檢測附著至導線架的晶片的篡改之方法，該方法包括：向第一多條線發送第一信號，該第一多條線自該導線架上的多個外引腳延伸至該晶片的表面上方的相應位置；向第二多條線發送第二信號，該第二多條線自該導線架上的多個內引腳延伸至該晶片的該表面上的多個接合墊；以及通過篡改保護電路監控該第一信號。
  17. 如申請專利範圍第16項所述之方法，其中，通過該篡改保護電路監控該第一信號包括：檢測由篡改企圖引發的該第一多條線的電容變化。
  18. 如申請專利範圍第16項所述之方法，其中，通過該篡改保護電路監控該第一信號包括：檢測由篡改企圖引發的該第一多條線的電阻變化。
  19. 如申請專利範圍第16項所述之方法，其中，該第一多條線串聯連接。
  20. 如申請專利範圍第16項所述之方法，其中，該第一信號是模仿該第二信號的偽信號。
TW106112180A 2016-06-28 2017-04-12 晶片封裝件的篡改檢測 TWI660184B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/195,029 2016-06-28
US15/195,029 US10651135B2 (en) 2016-06-28 2016-06-28 Tamper detection for a chip package

Publications (2)

Publication Number Publication Date
TW201809706A true TW201809706A (zh) 2018-03-16
TWI660184B TWI660184B (zh) 2019-05-21

Family

ID=60677063

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106112180A TWI660184B (zh) 2016-06-28 2017-04-12 晶片封裝件的篡改檢測

Country Status (3)

Country Link
US (1) US10651135B2 (zh)
CN (1) CN107546205B (zh)
TW (1) TWI660184B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI829332B (zh) * 2021-09-08 2024-01-11 新唐科技股份有限公司 積體電路和電子設備

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3077678B1 (fr) * 2018-02-07 2022-10-21 St Microelectronics Rousset Procede de detection d'une atteinte a l'integrite d'un substrat semi-conducteur d'un circuit integre depuis sa face arriere, et dispositif correspondant
WO2020043170A1 (en) * 2018-08-31 2020-03-05 Changxin Memory Technologies, Inc. Arrangement of bond pads on an integrated circuit chip
US10925154B2 (en) * 2019-01-31 2021-02-16 Texas Instruments Incorporated Tamper detection
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) * 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11081455B2 (en) * 2019-04-29 2021-08-03 Infineon Technologies Austria Ag Semiconductor device with bond pad extensions formed on molded appendage
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
CN110363271A (zh) * 2019-07-19 2019-10-22 云南纳光科技有限公司 通过检测引脚通断实现防篡改检测的无源nfc防伪芯片
CN111696983B (zh) * 2020-06-24 2024-03-15 悦虎晶芯电路(苏州)股份有限公司 多芯片水平封装的芯片模组、晶圆结构和加工方法
TWI817566B (zh) * 2021-09-07 2023-10-01 聯詠科技股份有限公司 薄膜覆晶封裝及包括該薄膜覆晶封裝的顯示裝置
CN116306459B (zh) * 2023-02-28 2024-06-04 本源科仪(成都)科技有限公司 量子芯片版图的引脚布置方法、系统、介质及设备

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5389738A (en) * 1992-05-04 1995-02-14 Motorola, Inc. Tamperproof arrangement for an integrated circuit device
US5861662A (en) 1997-02-24 1999-01-19 General Instrument Corporation Anti-tamper bond wire shield for an integrated circuit
US7417293B2 (en) * 2004-04-27 2008-08-26 Industrial Technology Research Institute Image sensor packaging structure
US7442583B2 (en) 2004-12-17 2008-10-28 International Business Machines Corporation Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable
US7557597B2 (en) * 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US7710286B1 (en) * 2007-03-30 2010-05-04 Maxim Integrated Products, Inc. Intrusion detection using a conductive material
US7923830B2 (en) 2007-04-13 2011-04-12 Maxim Integrated Products, Inc. Package-on-package secure module having anti-tamper mesh in the substrate of the upper package
JP2009076815A (ja) * 2007-09-25 2009-04-09 Nec Electronics Corp 半導体装置
EP2220679A4 (en) 2007-12-06 2014-02-26 Broadcom Corp EMBEDDED PACKING SAFETY MANIPULATION MACHINE
FR2938953B1 (fr) 2008-11-21 2011-03-11 Innova Card Dispositif de protection d'un boitier de circuit integre electronique contre les intrusions par voie physique ou chimique.
US8455990B2 (en) 2009-02-25 2013-06-04 Conexant Systems, Inc. Systems and methods of tamper proof packaging of a semiconductor device
US8811526B2 (en) * 2011-05-31 2014-08-19 Keyssa, Inc. Delta modulated low power EHF communication link
US9437512B2 (en) * 2011-10-07 2016-09-06 Mediatek Inc. Integrated circuit package structure
US8896086B1 (en) 2013-05-30 2014-11-25 Freescale Semiconductor, Inc. System for preventing tampering with integrated circuit
US9274545B2 (en) * 2013-10-24 2016-03-01 Globalfoundries Inc. Apparatus and method to recover a data signal
US9342710B2 (en) 2013-11-21 2016-05-17 Nxp B.V. Electronic tamper detection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI829332B (zh) * 2021-09-08 2024-01-11 新唐科技股份有限公司 積體電路和電子設備

Also Published As

Publication number Publication date
US10651135B2 (en) 2020-05-12
TWI660184B (zh) 2019-05-21
US20170373024A1 (en) 2017-12-28
CN107546205A (zh) 2018-01-05
CN107546205B (zh) 2021-01-26

Similar Documents

Publication Publication Date Title
TWI660184B (zh) 晶片封裝件的篡改檢測
KR101394177B1 (ko) Ｂｇａ 메시 캡을 갖는 패키지-온-패키지 보안 모듈
US7402442B2 (en) Physically highly secure multi-chip assembly
TWI443349B (zh) 具有偵知晶片斷裂結構之半導體裝置
TWI710070B (zh) 用於半導體封裝體之致能矽橋線內測試的防護環設計
US11502047B2 (en) Packaging techniques for backside mesh connectivity
JP2010206007A (ja) 半導体装置及びその製造方法
JP2003282791A (ja) 接触型センサ内蔵半導体装置及びその製造方法
CN101889344A (zh) 嵌入式封装防篡改网栅
US10147657B2 (en) Semiconductor devices and a method of detecting a crack
US9947609B2 (en) Integrated circuit stack
CN105474390B (zh) 电子硬件组件
EP3373511A1 (en) Method and apparatus for binding stacked die using a physically unclonable function
US9620462B2 (en) Integrated circuit package having surface-mount blocking elements
US11411163B2 (en) Packaging for ultrasonic transducers
US8717059B2 (en) Die having wire bond alignment sensing structures
CN101762762B (zh) 封装结构的检测方法、检测板及封装检测组件
JP2006086360A (ja) 半導体装置及びその製造方法
US20060071306A1 (en) Active device bases, leadframes utilizing the same, and leadframe fabrication methods