CN107546205A - 芯片封装件的篡改检测 - Google Patents

芯片封装件的篡改检测 Download PDF

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Publication number
CN107546205A
CN107546205A CN201710506432.3A CN201710506432A CN107546205A CN 107546205 A CN107546205 A CN 107546205A CN 201710506432 A CN201710506432 A CN 201710506432A CN 107546205 A CN107546205 A CN 107546205A
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China
Prior art keywords
chip
line
lead frame
substrate
joint sheet
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Granted
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CN201710506432.3A
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CN107546205B (zh
Inventor
理查·S·格拉夫
E·D·B·霍尔
F·帕克巴兹
沙巴斯钦·T·凡托尼
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Kawam International Inc
Marvell International Ltd
Marvell Asia Pte Ltd
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GlobalFoundries Inc
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Abstract

本发明揭示芯片封装件的篡改检测，其具有改进防篡改的芯片封装件以及使用此类芯片封装件来提供改进防篡改的方法。导线架包括芯片附着座、外引脚，以及位于该外引脚与该芯片附着座之间的内引脚。芯片附着至该芯片附着座。该芯片包括表面，该表面具有外边界以及邻近该外边界布置的接合垫。第一多条线自该外引脚延伸至该芯片的该表面上的相应位置，该些位置相对该接合垫在该外边界的内部。篡改检测电路与该第一多条线耦接。第二多条线自该内引脚延伸至该芯片上的该接合垫。该第二多条线位于该导线架与该第一多条线之间。

Description

芯片封装件的篡改检测
技术领域
本发明涉及芯片封装，尤其涉及芯片的防篡改封装件以及使用此类封装件提供防篡改的方法。
背景技术
芯片封装在产品保护及芯片安全方面起作用。例如，芯片封装件可保护被封闭的芯片免受损伤。至于芯片安全，可应用防篡改技术来防止攻击者偷偷访问芯片并阻止逆向工程。
需要以改进防篡改为特征的芯片封装件以及使用此类芯片封装件的方法。
发明内容
依据本发明的一个实施例，一种结构包括导线架，其具有芯片附着座、多个外引脚，以及位于该外引脚与该芯片附着座之间的多个内引脚。芯片附着至该芯片附着座。该芯片包括表面，该表面具有外边界以及邻近该外边界布置的多个接合垫。第一多条线自该外引脚延伸至该芯片的该表面上的相应位置，该些位置相对该接合垫在该外边界的内部。篡改检测电路与该第一多条线耦接。第二多条线自该内引脚延伸至该芯片上的该接合垫。该第二多条线位于该导线架与该第一多条线之间。
依据本发明的另一个实施例，提供一种方法以检测附着至导线架上的芯片附着座的芯片的篡改的方法。该方法包括：向第一多条线发送第一信号，该第一多条线自该导线架上的多个外引脚延伸至该芯片的表面上方的相应位置；向第二多条线发送第二信号，该第二多条线自该导线架上的多个内引脚延伸至芯片的该表面上的多个接合垫；以及通过篡改保护电路监控该第一信号。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例，并与上面所作的本发明的概括说明以及下面所作的实施例的详细说明一起用以解释本发明的实施例。
图1显示依据本发明的一个实施例的芯片封装件的剖视图。
图2显示图1的芯片封装件的顶视图，其中，出于说明目的移除了外壳。
图3显示依据本发明的一个实施例利用连接芯片与封装件的线的篡改检测系统的示意图。
具体实施方式
请参照图1、2并依据本发明的一个实施例，芯片封装件10包括芯片12、导线架14，以及具有外表面17的外壳16。芯片12包括一个或多个集成电路，其具有通过使用前端工艺(front-end-of-line；FEOL)制程形成的装置结构。该FEOL制程可包括例如互补金属氧化物半导体(complementary-metal-oxide-semiconductor；CMOS)制程，该制程用以构建经耦接以实施逻辑门及其它类型数字电路的p型与n型场效应晶体管的组合。芯片12包括建立外边界或周边的侧边26，以及被侧边26围绕或限制的表面38。
导线架14包括芯片附着垫或座18，其相对内引脚20及外引脚22居中设置。导线架14可由金属(例如铜或铜合金)的薄层组成。芯片12通过例如导热和/或导电黏附剂的层24附着至芯片附着座18。芯片附着座18的不同侧边分别与芯片12的侧边26对齐。可将芯片封装件10表面贴装至衬底40，例如印刷电路板或层叠衬底。芯片附着座18为从芯片12(当开启时)至衬底40的热传递提供低热阻路径。
可将内引脚20及外引脚22布置成行，该些行与芯片12的侧边26的其中一条或多条相邻设置并向外间隔开。在芯片12及芯片附着座18呈矩形的该代表性实施例中，引脚20、22的行与芯片12的所有侧边26相邻设置且不同的行可与芯片12的相应不同侧边26平行排列。在一个替代实施例中，引脚20、22可与芯片12的部分侧边26相邻设置。例如，引脚20、22可仅与芯片12的侧边26的其中相对一对相邻设置。在芯片12的各侧边26上，内引脚20被横向设置成它们的相应行，其位于包括外引脚22的相邻行与芯片附着座18之间，以使内引脚20比外引脚22更靠近芯片12及芯片附着座18。引脚20、22可具有不同的尺寸及不同的间距。引脚20、22的相应表面20a、22a与芯片12的表面38面向同一方向取向，以促进打线接合(wirebonding)制程。
在一个实施例中，芯片封装件10可为多行四方扁平无引线(QaudFlat No-leads；QFN)芯片封装件或另一种类型的多行扁平无引线封装件。在一个特定实施例中，芯片封装件10可为双行QFN芯片封装件或另一种类型的双行扁平无引线封装件。在具有不止两行引脚的芯片封装件中，将额外行的引脚设置于内引脚20与外引脚22之间，以将外引脚22设置为与芯片12及芯片附着座18具有最大间距的周边最外行。
在通过FEOL制程形成集成电路以后，芯片12经历中间工艺(middle-of-line；MOL)制程及后端工艺(back-end-of-line；BEOL)制程，以形成堆叠布置的多个金属化层级并包括位于最上金属化层级中的接合垫34、36。接合垫34、36可由铜、铝，或这些金属的合金组成，且可通过例如金属沉积层的减成蚀刻(subtractive etching)形成。接合垫34、36位于芯片12的顶部表面38的BEOL互连结构的最上金属化层级中，且可供打线接合制程使用。接合垫34可用以向芯片12的集成电路提供信号、时钟、功率等的导电路径。在一个实施例中，接合垫36不与芯片12的集成电路连接，而是接合垫36的相邻对通过BEOL互连结构中的导电路径35(示意显示于图2中)连接。导电路径35可位于例如与最上金属化层级相邻的金属化层级中的芯片12的顶部表面38下方。在一个替代实施例中，接合垫36的其中一个或多个可与作为芯片12上的集成电路通过FEOL制程所形成的一个或多个篡改保护电路耦接，如下所述。
线30、32没有连接至位于例如芯片堆叠中的多层上的位置。相反，芯片12的表面38提供共平面，在该共平面中将所有线30的端部附着至芯片12并设置所有线32的端部33。
接合垫34、36位于由侧边26建立的芯片12的外边界的内部的表面38上，而接合垫36位于接合垫34的内部。接合垫34在由侧边26建立的外周边或边界附近的芯片12的边缘设置，且可被布置成与不同的侧边26相邻的行。内引脚20及接合垫34分别比外引脚22及接合垫36更靠近该外边界。接合垫36位于接合垫36的内部，且内引脚20也横向位于外引脚22的内部。可将接合垫36布置成行，该些行成一角度朝向芯片12的顶部表面38的中心并相对包含接合垫34的行。接合垫36的排列促进提供篡改保护的能力。
线30自附着至导线架14上的内行中的内引脚20的一端延伸至附着于芯片12上的接合垫34的相对端。线30用以在芯片12与衬底40之间提供互连，该互连在该芯片的外部环境与芯片12上的集成电路之间提供电性路径。线30的数目及引脚20的数目可依据芯片封装件10及芯片12的设计而变化。
线32自附着至导线架14上的外行中的外引脚22的一端31延伸至附着于芯片12上的接合垫36的相对端33。线32的数目及密度以及引脚22及接合垫36的数目及密度可依据提供篡改保护的覆盖范围的需要而变化。
线30、32可由具有细直径的金属例如金或铜组成且可通过打线接合制程施加。例如，该打线接合制程可依赖于打线接合工具，该工具行进至接合垫36的其中之一的位置并通过使用热和/或超声能量将位于线32的端部33的球形球附着至接合垫36。随着端部33被附着至接合垫36，该打线接合工具向外引脚22的其中之一以弧形运动方式运动，同时在运动期间分配线32的长度。形成针脚式接合，以将线32的相对端31与外引脚22的其中之一接合。在一个替代操作次序中，可先形成至外引脚22的该针脚式接合并可最后形成至接合垫36的接合。
位于引脚22的端部31与接合垫36的端部33之间的线32的长度获得与呈弧形运动的该打线接合工具的运动相关的接合后形状。除其它因素以外，该弧形运动确定线32沿其在端部31、33之间的长度的标高或高度。该打线接合工具的该运动经编程以使线32与线30相比，相对芯片12的表面38具有较高的标高。尤其，线32自外引脚22在线30上方走线，以使线32的弧在线30的弧上方形成罩或伞。在该打线接合制程期间，线32都可以同一弧形运动形成，以使线32相对所有线30所共有的较低标高具有同一较高标高，并使线32的弧的长度比线30的弧的长度长。
由于线32围绕侧边26的布置，线32形成位于线30上方的独立导体格栅或网格。线30、32垂直位于与导线架14耦接的衬底40与外壳16的外表面17之间。穿过外壳16以从外壳16的外表面17访问线30的任意企图将需要探针经过线32的相邻一对之间，以接触线32的其中一条或多条，或者邻近线32的其中一条或多条。相对芯片12，线30在由侧边26建立的芯片12的外边界的内部位置水平且垂直位于线32与芯片12的表面38之间。在一个实施例中，线32可向芯片12的表面38的几何中心延伸，以覆盖表面38的大部分或位于其上方。最佳如2中所示，线32可覆盖芯片12的表面38的各象限的大部分且线30可与位于各该象限中的接合垫34连接。相对导线架14，线30垂直且水平位于线32与芯片封装件10的外壳16的外表面17之间。
芯片12、导线架14以及线30、32被封装于外壳16内部。外壳16可通过芯片封装制程形成，在通过打线接合制程形成线30、32以后，该芯片封装制程除其它操作以外施加并固化环氧模压复合材料。外壳16用以防止对线30和/或芯片12造成物理损伤或腐蚀，且还可限制访问芯片12及线30。
衬底40可包括金属化，其定义用以将外引脚22的相邻对耦接在一起的导电路径42。线32可通过衬底40的导电路径42及芯片12的导电路径35菊链或串联耦接。由芯片12的BEOL互连结构中的导电路径35提供的互连以及由衬底40中的导电路径42提供的互连允许同时篡改监控优化数目的线32。衬底40可包括额外的金属化(例如接地平面44以及功率平面46)，其独立于用以连接接合垫36的相邻对的导电路径42。
线32提供检测物理攻击的篡改的能力。例如，线32可允许检测移除芯片封装件10的物理篡改企图。又例如，线32可允许检测当线32被探针或穿入外壳16中的另一个外来物体的物理接触以试图感测线30所载的I/O信号时的篡改。该物理篡改企图可引起线32的属性变化，例如如果一条或多条线32被接触的电阻变化或者因导电外来物体靠近一条或多条导线32而引起的电容变化。
请参照图3，其中，类似的附图标记表示图1至2中的类似特征且依据本发明的一个实施例，线32可与篡改保护电路50耦接并可结合篡改保护电路50充当感测装置，用以检测入侵篡改。入侵篡改可包括但不限于破坏外壳16或自衬底40移除芯片12，且可通过使用微探测台的探针进行尝试。篡改保护电路50可位于芯片12上或芯片12外，例如位于衬底40上。篡改保护电路50可经配置以响应自芯片12上的集成电路接收的指令或编程设置以及/或者自芯片外源(例如与芯片12在同一衬底40上的源)接收的其它指令或输入向线向线32传输电性信号。
篡改保护电路50可包括发送器电路52，该发送器电路经配置以将静态信号或瞬态信号作为脉冲发送，该脉冲经过线32到达接收器电路54，该接收器电路经配置以接收经过线32的该信号。由于线32菊链串联，因此该信号可经过所有线32。该信号可被配置为伪信号，该伪信号经脉冲化以模仿传输于线30上的实际信号的频率及不规则性。伪信号的使用可使攻击者难以检测到线32及其上的信号正被用于篡改保护目的。伪信号尤其可有效打击对线30所载信号的窃听。
由发送器电路52提供的信号可基于在开环状态中操作的运算放大器由电压检测电路产生。可将变化输入电压作为模拟电压电平输入该运算放大器的一个端口，并将参考电压输入该运算放大器的另一个端口。自该运算放大器向线32输出的信号是基于不同模拟电压电平之间的比较，且可为一系列脉冲，其振幅在正供应轨线电压及负供应轨线电压范围内变化。
篡改保护电路50可经配置以确定信号经过线32的传输时间延迟。为此，电路52、54可与时钟电路56耦接，该时钟电路提供定时信息，且可于芯片12启动时操作。接收器电路54测量从信号被发送器电路52发送至线32上的瞬间至其接收的信号延迟。可将由发送器电路52发送并在接收器电路54接收的任意给定信号的延迟与延迟储存值或延迟值储存窗口进行比较，该延迟储存值或延迟值储存窗口可自初始测试确定。例如，由于已破坏外壳16并位于线32的其中一条或多条的探针或其它物体的靠近而引起的电容变化可导致该延迟在该储存值或值范围之外变化。
一旦检测到物理篡改企图，篡改保护电路50即可通过采取或触发一个或多个对策来响应，例如生成使能信号以启动防篡改操作。例如，如果线32检测到外壳16穿透或检测到线32的电阻或电容变化中的超限环境参数，则篡改保护电路50可经设计以触发敏感数据归零。归零可能需要清除存储器芯片的存储器单元中的敏感储存内容或重写存储器芯片的存储器单元的其中一些或全部。或者，可停止芯片12上的处理器，可发出警报以使系统或使用者意识到该篡改事件，或者一个或多个电路块或嵌入式软件可防止芯片12完全操作或完全作用。
上述方法用于集成电路芯片的制造中。制造者可以原始晶圆形式(例如作为具有多个未封装芯片的单个晶圆)、作为裸芯片，或者以封装形式分配所得的集成电路芯片。可将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成，作为中间产品或最终产品的部分。该最终产品可为包括集成电路芯片的任意产品，例如具有中央处理器的电脑产品或智能手机。
本文中引用术语例如“垂直”、“水平”等作为示例来建立参考框架，并非限制。本文中所使用的术语“水平”被定义为与半导体衬底的传统平面平行的平面，而不论其实际的三维空间取向。术语“垂直”及“正交”是指垂直于如刚刚所定义的水平面的方向。术语“横向”是指在该水平平面内的方向。术语例如“上方”及“下方”用以表示元件或结构相对彼此的定位，而不是相对标高。
与另一个元件“连接”或“耦接”的特征可与该另一个元件直接连接或耦接，或者可存在一个或多个中间元件。如果不存在中间元件，则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件，则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的，而非意图详尽无遗或限于所揭示的实施例。许多修改及变更对于本领域的普通技术人员将显而易见，而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进，或者使本领域的普通技术人员能够理解本文中所揭示的实施例。

Claims (20)

1.一种结构，包括：
导线架，具有芯片附着座、多个外引脚，以及位于该外引脚与该芯片附着座之间的多个内引脚；
芯片，附着至该芯片附着座，该芯片包括表面，该表面具有外边界以及邻近该外边界布置的第一多个接合垫；
第一多条线，自该外引脚延伸至该芯片的该表面上的相应位置，所述位置相对该第一多个接合垫在该外边界的内部；
篡改检测电路，与该第一多条线耦接；以及
第二多条线，自该内引脚延伸至该芯片上的该第一多个接合垫，该第二多条线位于该导线架与该第一多条线之间。
2.如权利要求1所述的结构，还包括：
衬底，该导线架附着至该衬底，该衬底包括经布置以耦接该外引脚的相邻对的多条导电路径。
3.如权利要求1所述的结构，其中，该芯片包括第二多个接合垫，各该第一多条线具有耦接至该外引脚的其中之一的第一端，该第一多个接合垫位于该芯片的该第二多个接合垫与该外边界之间，且各该第一多条线具有耦接至该第二多个接合垫的其中之一的第二端。
4.如权利要求3所述的结构，还包括：
衬底，该导线架附着至该衬底，该衬底包括经布置以耦接该外引脚的相邻对的多条导电路径。
5.如权利要求3所述的结构，其中，该芯片具有互连结构，该互连结构具有多条导电路径，且该第二多个接合垫的相邻对通过该互连结构的该导电路径的其中之一连接。
6.如权利要求5所述的结构，还包括：
衬底，该导线架附着至该衬底，该衬底包括经布置以耦接该外引脚的相邻对的多条导电路径。
7.如权利要求1所述的结构，其中，该第一多条线自该外引脚向该芯片的该表面上的该相应位置以相应第一弧延伸，该第二多条线自该内引脚向该第一多个接合垫以相应第二弧延伸，且该第二弧短于该第一弧。
8.如权利要求1所述的结构，还包括：
衬底，该导线架附着至该衬底；以及
外壳，具有外表面，
其中，该导线架、该芯片、该第一多条线，以及该第二多条线被封装于该外壳内部，且该导线架、该芯片、该第一多条线，以及该第二多条线位于该衬底与该外壳的该外表面之间。
9.如权利要求1所述的结构，其中，该内引脚横向位于该外引脚与该芯片的该外边界之间，该芯片的该外边界包括多条侧边，且该内引脚与该外引脚沿该芯片的该侧边的其中一条或多条被设置成一个或多个行。
10.如权利要求9所述的结构，其中，该外引脚所设置成的该一个或多个行沿该芯片的所有该侧边布置。
11.如权利要求9所述的结构，其中，该外引脚所设置成的该一个或多个行沿彼此相对的该芯片的该侧边的其中至少两条布置。
12.如权利要求1所述的结构，其中，该篡改检测电路包括：
接收器电路，与该第一多条线耦接；以及
发送器电路，与该第一多条线耦接，该发送器电路经配置以向该第一多条线提供信号，该信号经过该第一多条线到达该接收器电路。
13.如权利要求1所述的结构，其中，该篡改检测电路包括：
接收器电路，与该第一多条线耦接；以及
发送器电路，与该第一多条线耦接，该发送器电路经配置以向该第一多条线提供伪信号，该伪信号经过该第一多条线到达该接收器电路。
14.如权利要求1所述的结构，其中，该篡改检测电路位于该芯片上，该芯片包括第二多个接合垫，且该第二多个接合垫将该第一多条线与该篡改检测电路耦接。
15.如权利要求1所述的结构，其中，该篡改检测电路位于该芯片外，该芯片包括第二多个接合垫，且该外引脚将该第一多条线与该篡改检测电路耦接。
16.一种用以检测附着至导线架的芯片的篡改的方法，该方法包括：
向第一多条线发送第一信号，该第一多条线自该导线架上的多个外引脚延伸至该芯片的表面上方的相应位置；
向第二多条线发送第二信号，该第二多条线自该导线架上的多个内引脚延伸至该芯片的该表面上的多个接合垫；以及
通过篡改保护电路监控该第一信号。
17.如权利要求16所述的方法，其中，通过该篡改保护电路监控该第一信号包括：
检测由篡改企图引发的该第一多条线的电容变化。
18.如权利要求16所述的方法，其中，通过该篡改保护电路监控该第一信号包括：
检测由篡改企图引发的该第一多条线的电阻变化。
19.如权利要求16所述的方法，其中，该第一多条线串联连接。
20.如权利要求16所述的方法，其中，该第一信号是模仿该第二信号的伪信号。
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