CN107527815B - 外延层的制作方法 - Google Patents

外延层的制作方法 Download PDF

Info

Publication number
CN107527815B
CN107527815B CN201610452293.6A CN201610452293A CN107527815B CN 107527815 B CN107527815 B CN 107527815B CN 201610452293 A CN201610452293 A CN 201610452293A CN 107527815 B CN107527815 B CN 107527815B
Authority
CN
China
Prior art keywords
epitaxial layer
layer
epitaxial
dielectric layer
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610452293.6A
Other languages
English (en)
Other versions
CN107527815A (zh
Inventor
李一凡
冯立伟
许力介
陈俊仁
胡益诚
吴典逸
林钰书
杨能辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Blue gun Semiconductor Co.,Ltd.
Original Assignee
Blue Gun Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Blue Gun Semiconductor Co ltd filed Critical Blue Gun Semiconductor Co ltd
Priority to CN201610452293.6A priority Critical patent/CN107527815B/zh
Priority to US15/214,467 priority patent/US9748147B1/en
Publication of CN107527815A publication Critical patent/CN107527815A/zh
Application granted granted Critical
Publication of CN107527815B publication Critical patent/CN107527815B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明公开一种外延层的制作方法，包含提供一硅基底，一介电层覆盖硅基底，接着形成一凹槽于硅基底和介电层内，之后进行一选择性外延成长步骤以及一非选择性外延成长步骤，分别形成一第一外延层和第二外延层于凹槽内，第一外延层不覆盖介电层的上表面，其中凹槽由第一外延层和第二外延层共同填满，最后平坦化第一外延层和第二外延层。

Description

外延层的制作方法
技术领域
本发明涉及一种外延层的制作方法，尤其是涉及一种结合选择性外延步骤和非选择性外延步骤的外延层的制作方法。
背景技术
近年来，随着各种消费性电子产品不断的朝小型化发展，半导体元件设计的尺寸也不断缩小，以符合高集成度、高效能和低耗电的潮流以及产品需求。
然而，随着电子产品的小型化发展，现有的平面晶体管已经无法满足产品的需求。因此，目前发展出一种非平面晶体管的鳍状晶体管技术。与平面晶体管不同，在鳍状晶体管具有立体的栅极通道结构，以缩小晶体管的物理尺寸，此外，鳍状晶体管还具有减少基底的漏电、降低短通道效应，并具有较高的驱动电流的特色。
但由于鳍状晶体管是属于立体的结构，较传统结构复杂，制造难度也偏高，而且依现今对电子产品要求体积小和速度快的情况下，还需要一种新颖的鳍状晶体管装置的制作方法，以达成业界的需求。
发明内容
根据本发明的较佳实施例，一种外延层的制作方法，包含提供一硅基底，一介电层覆盖硅基底，接着形成一凹槽于硅基底和介电层内，进行一选择性外延成长步骤以形成一第一外延层于凹槽内，其中第一外延层不覆盖介电层的一上表面，之后进行一非选择性外延成长步骤以形成一第二外延层于凹槽内，并且第二外延层覆盖介电层的该上表面，其中凹槽由第一外延层和第二外延层共同填满，最后平坦化第一外延层和第二外延层，使得第二外延层和介电层切齐。
附图说明
图1至图10所绘示的为根据本发明较佳实施例的形成一种外延层的制作方法。
主要元件符号说明
10 硅基底 12 介电层
14 上表面 16 上表面
18 图案化掩模层 20 N型掺杂区
22 图案化掩模层 24 P型掺杂区
26 图案化掩模层 28 凹槽
30 第一外延层 32 第二外延层
34 上表面 36 上表面
38 掩模层 40 外延层
42 掩模层 44 间隙壁
46 鳍状结构
具体实施方式
请参考图1至图10，图1至图10所绘示的为根据本发明较佳实施例的形成一种外延层的制作方法。如图1所示，首先提供一硅基底10。接着，在硅基底10上形成一介电层12，其可包含有单一材料层或多层堆叠薄膜，介电层12可以包含氮化硅、氧化硅或氮氧化硅等。介电层12接触硅基底10的一上表面14，介电层12的上表面16和硅基底10的上表面14平行。接着，根据不同制作工艺上的需求，硅基底10上可至少定义有第一区A和第二区B，第一区A可以为周边电路区或是平坦式晶体管区，第二区B可以为核心电路区或是鳍状晶体管区，第二区B又可分为二个掺杂区，例如一N型掺杂区以及一P型掺杂区。介电层12可以是用于形成第一区中的浅渠沟隔离时所留下的垫氧化层。
N型掺杂区和P型掺杂区的形成方式如图2和图3所示，但N型掺杂区和P型掺杂区的形成顺序可视状况不同而对调。如图2所示，举例而言，先形成一图案化掩模层18，例如光致抗蚀剂，覆盖部分硅基底10和介电层12，暴露出部分基底10和介电层12，然后进行一离子掺杂步骤，将N型掺质注入硅基底10，形成一N型掺杂区20，之后移除图案化掩模层18。如图3所示，先形成另一图案化掩模层22，例如光致抗蚀剂覆盖部分硅基底10和介电层12，暴露出不具有N型掺杂区20的硅基底10，然后进行一离子掺杂步骤，将P型掺质注入硅基底10，形成一P型掺杂区24，之后移除图案化掩模层22，然后进行一快速升温处理制作工艺，以驱入(drive in)掺质。
如图4所示，形成一图案化掩模层26覆盖硅基底10，并且在N型掺杂区20上的介电层12由图案化掩模层26暴露出来，然而以图案化掩模层26为掩模蚀刻介电层12和硅基底10以形成一凹槽28，详细来说，先蚀刻位于N型掺杂区20正上方的介电层12，使其完全被移除之后，接续蚀刻部分的N型掺杂区20，以形成凹槽28，也就是说凹槽28是由介电层12和硅基底10定义而成。接续移除图案化掩模26。后续将形成外延层于凹槽28中，为形成品质较佳的外延层于凹槽28中，在进行后续的外延层步骤前，可另先进行一预清洗(pre-clean)步骤，例如利用稀释氢氟酸水溶液、或含有硫酸、过氧化氢、与去离子水的SPM混合溶液等清洗液以去除凹槽28表面的不纯物质例如原生氧化物(native oxide)层。此外，可再进行一预烤步骤(pre-bake)，例如在通入氢气的腔室中加热硅基底10，以清除凹槽28表面的原生氧化物层或残留的清洗液。
请参考图5和图7，此两个步骤是本发明的关键部分，图5和图7的步骤，两者可以结合应用在任何需要外延层的步骤，不必非得搭配图1至图4的步骤。
在图5中，先进行一选择性外延成长步骤以形成一第一外延层30于凹槽28内，接续再如图7所示，进行非选择性外延成长步骤以形成一第二外延层32于凹槽28内。第一外延层30可以为硅化锗、硅化磷或碳化硅，第二外延层32可以为硅化锗、硅化磷或碳化硅。但第一外延层30和第二外延层32较佳为相同材料，更佳的是第一外延层30和第二外延层32是本质上完全相同的材料。
详细来说，如图5所示，进行一选择性外延成长步骤，于凹槽28内形成第一外延层30。值得注意的是：第一外延层30不覆盖介电层12的上表面16，并且至少部分的第一外延层30的一上表面34低于介电层12的上表面16，在图5第一外延层30的上表面34轮廓为凹面的情况下，当第一外延层30的上表面34的任何部分会高于介电层12的上表面16之前，选择性外延成长步骤就必须停止，在图5中的第一外延层30的上表面34轮廓为凹面，但根据本发明另一较佳实施例，如图6所示，通过调整制作工艺参数，第一外延层30的上表面34轮廓可以为凸面，在第一外延层30的上表面34轮廓为凸面的情况下，第一外延层30的上表面34有可能会高于介电层12的上表面，但第一外延层30依然不会覆盖介电层12的上表面16。
一般而言，选择性外延成长步骤允许外延层生长在硅材料上，例如硅基底上，而不生长在非硅材料，例如介电层表面上。选择性外延成长步骤可以于半导体元件中使用，例如：鳍状结构、高起的源极/漏极、源极/漏极延伸部、接触插塞或双极性元件的基底层沉积。在选择性外延成长步骤中，四氯硅烷(SiCl4)被经常用作为硅原子的来源，而在反应气体中添加氯化氢可以增加成长过程中的选择性(Selectivity)沉积的能力。而于外延过程中可通过调控一些参数来控制外延层的沉积状况，可影响外延状况的参数包括了硅基板的表面情况、凹槽的大小、氯化氢的浓度、硅气体源种类或成长压力和温度等。
以下说明本发明的较佳实施例的选择性外延成长步骤的操作参数，当然依据不同产品要求，参数可作不同的调整，本实施例只为举例之用。在进行图5中选择性外延成长步骤时，在操作压力介于10至50托耳(torr)之间以及温度在摄氏500至800度的腔室中通入气体，气体包括二氯硅烷(Dichlorosilane,DCS)、锗烷(GeH4)以及氯化氢等，以形成第一外延层30于凹槽28内，在此条件下所形成的第一外延层30为硅化锗，前述的二氯硅烷可用四氯硅烷取代。二氯硅烷供应至腔室的速率为40至150标准毫升/分(standard cubiccentimeter per minute)，锗烷供应至腔室的速率为250至900标准毫升/分，氯化氢供应至腔室的速率为70至200标准毫升/分，其中，二氯硅烷为硅源材料气体，锗烷为锗源材料气体，而二氯硅烷的浓度比例与锗烷的浓度比例可决定第一外延层所包含锗浓度，较佳者，二氯硅烷的浓度比例实质上小于锗烷的浓度比例。此外，氯化氢用来协助第一外延层30的选择性形成，以使第一外延层30只形成于凹槽28内的硅基底10上，而不形成于氧化物或氮化硅等材料构成的介电层12上。较佳者，氯化氢的浓度比例实质上介于二氯硅烷的浓度比例与锗烷的浓度比例之间。
图7为接续图5中的步骤，接着如图7所示进行非选择性外延成长步骤，以形成一第二外延层32于凹槽28内，第二外延层32覆盖第一外延层30并且也覆盖介电层12的上表面16，由于有至少部分的第一外延层30低于介电层12的上表面16，因此在选择性外延成长步骤完成时，第一外延层30并未填满由介电层12和硅基底10定义出的凹槽28，直到第二外延层32形成后，凹槽28才由第一外延层30和第二外延层32共同填满。
非选择性外延成长步骤和选择性外延成长步骤的不同之处在于非选择性外延成长步骤所形成的外延层会形成在所有的材料上，不限定只形成在硅材料上，也就是说第二外延层32会形成并接触硅基底10和介电层12，此外第二外延层32会在介电层12上形成一定厚度。
在进行图7中非选择性外延成长步骤时，在操作压力介于20至100托耳之间以及温度在摄氏500至800度的腔室中，通入气体，气体包括二氯硅烷(Dichlorosilane,DCS)、锗烷(GeH4)以及氯化氢等，在此条件下所形成的第二外延层32为硅化锗，前述的二氯硅烷可用四氯硅烷取代，较佳地，第一外延层30和第二外延层32二者的成分本质上相同。二氯硅烷供应至腔室的速率为50至200标准毫升/分(sccm)，锗烷供应至腔室的速率为200至700标准毫升/分，氯化氢供应至腔室的速率为10至50标准毫升/分。
如图8所示，平坦化第二外延层32，使得第二外延层32的上表面36和介电层12的上表面16切齐，在一些情况下，需平坦化第一外延层30和第二外延层32，使得第一外延层30的上表面34、第二外延层32的上表面36和介电层12的上表面16同时切齐。至此，本发明的外延层40业已完成。此外，前述外延层40的制作方式也可以视产品需求，形成在P型掺杂区24中。本发明的第一外延层30和第二外延层32可应用在鳍状结构中，例如在第一外延层30和第二外延层32完成之后，图案化硅基底10、第一外延层30和第二外延层32，以形成多个鳍状结构。详细来说，如图9所示，全面移除介电层12，在硅基底10和第二外延层32上形成一掩模层38，掩模层38可以为氧化硅-氮化硅-氧化硅的复合结构，或是其它介电材料。本发明利用间隙壁自对准双图案法(spacer self-aligned double-patterning,SADP)的方式来图案化掩模层38，首先形成多个掩模层42在掩模层38上，接着在各个掩模层42两侧形成间隙壁44，使得部分的掩模层38由掩模层42和间隙壁44暴露出来，然后以掩模层42和间隙壁44为掩模，移除部分掩模层38，之后移除掩模层42和间隙壁44。
如图10所示，以掩模层38为掩模，蚀刻硅基底10、第一外延层30和第二外延层32，以形成多个鳍状结构46。有些鳍状结构46，由具有N型掺杂区20的硅基底10、第一外延层30和第二外延层32共同构成，而另外有些鳍状结构46由具有P型掺杂区24的硅基底10构成。
在完成图10的步骤后，接续可以移除掩模层38，之后先在鳍状结构之间形成浅沟槽隔离，再形成栅极介电层、栅极电极和源极/漏极在鳍状结构上。
本发明的外延层的形成方式包含一选择性外延成长步骤和一非选择性外延成长步骤，并且选择性外延成长步骤在非选择性外延成长步骤之前。先用选择性外延成长步骤形成的第一外延层30填入部分的凹槽28，再用非选择性外延成长步骤所形成的第二外延层32填入剩余的凹槽28，此外第二外延层32全面在介电层12上形成一高低差较小厚度，所以后续在平坦化第二外延层32时不会在介电层12或其下的硅基底10上形成凹陷。若是只用选择性外延成长步骤形成外延层填满凹槽，外延层的上表面会高于介电层的上表面很多，也就是外延层的上表面和介电层的上表面会有很大的高低差，后续在平坦化外延层后，会造成介电层甚至介电层下方的硅基底产生凹陷。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种外延层的制作方法，包含：
提供一硅基底，一介电层覆盖该硅基底；
形成一凹槽于该硅基底和该介电层内；
进行一选择性外延成长步骤以形成一第一外延层于该凹槽内，其中该第一外延层不覆盖该介电层的一上表面，并且该第一外延层不与该介电层接触；
进行一非选择性外延成长步骤以形成一第二外延层于该凹槽内，并且该第二外延层覆盖该介电层的该上表面，其中该凹槽仅由该第一外延层和该第二外延层共同填满；以及
平坦化该第二外延层，使得该第二外延层和该介电层的上表面切齐。
2.如权利要求1所述的外延层的制作方法，其中至少部分的该第一外延层的一上表面低于该介电层的该上表面。
3.如权利要求1所述的外延层的制作方法，另包含形成该凹槽之前，形成一掺杂区于该硅基底中。
4.如权利要求3所述的外延层的制作方法，其中形成该凹槽的步骤包含移除部分的该掺杂区。
5.如权利要求1所述的外延层的制作方法，另包含在平坦化该第一外延层和该第二外延层之后，图案化该第一外延层、该第二外延层和该硅基底以形成至少一鳍状结构。
6.如权利要求1所述的外延层的制作方法，其中该第一外延层包含硅化锗、硅化磷或碳化硅。
7.如权利要求1所述的外延层的制作方法，其中该第二外延层包含硅化锗、硅化磷或碳化硅。
8.如权利要求1所述的外延层的制作方法，其中该介电层包含氮化硅、氧化硅或氮氧化硅。
9.如权利要求1所述的外延层的制作方法，其中该选择性外延成长步骤限定只成长该第一外延层在该硅基底上，该第一外延层，不会成长在该介电层上。
10.如权利要求1所述的外延层的制作方法，其中该介电层接触该硅基底的一上表面，该介电层的该上表面和该硅基底的该上表面平行。
CN201610452293.6A 2016-06-21 2016-06-21 外延层的制作方法 Active CN107527815B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201610452293.6A CN107527815B (zh) 2016-06-21 2016-06-21 外延层的制作方法
US15/214,467 US9748147B1 (en) 2016-06-21 2016-07-20 Method of fabricating epitaxial layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610452293.6A CN107527815B (zh) 2016-06-21 2016-06-21 外延层的制作方法

Publications (2)

Publication Number Publication Date
CN107527815A CN107527815A (zh) 2017-12-29
CN107527815B true CN107527815B (zh) 2022-03-22

Family

ID=59654122

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610452293.6A Active CN107527815B (zh) 2016-06-21 2016-06-21 外延层的制作方法

Country Status (2)

Country Link
US (1) US9748147B1 (zh)
CN (1) CN107527815B (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020047510A (ko) * 2000-12-13 2002-06-22 박종섭 반도체 소자의 트랜지스터 제조 방법
CN1367526A (zh) * 2001-01-23 2002-09-04 联华电子股份有限公司 一种于一硅覆绝缘层上形成掺杂区的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385234B2 (en) * 2013-02-27 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9330959B2 (en) * 2014-04-13 2016-05-03 Texas Instruments Incorporated Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
KR102195230B1 (ko) * 2014-06-03 2020-12-24 삼성전자주식회사 정전기 보호 소자

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020047510A (ko) * 2000-12-13 2002-06-22 박종섭 반도체 소자의 트랜지스터 제조 방법
CN1367526A (zh) * 2001-01-23 2002-09-04 联华电子股份有限公司 一种于一硅覆绝缘层上形成掺杂区的方法

Also Published As

Publication number Publication date
US9748147B1 (en) 2017-08-29
CN107527815A (zh) 2017-12-29

Similar Documents

Publication Publication Date Title
US11133387B2 (en) FinFETs having dielectric punch-through stoppers
US8076735B2 (en) Semiconductor device with trench of various widths
KR100844933B1 (ko) 반도체 소자의 트랜지스터 및 그 제조 방법
US8969163B2 (en) Forming facet-less epitaxy with self-aligned isolation
TWI656564B (zh) 半導體結構的製造方法
CN103247537A (zh) 制造鳍片器件的方法和鳍片器件
KR20150050338A (ko) Ｆⅰｎｆｅｔ 디바이스를 형성하기 위한 메커니즘들
KR100683401B1 (ko) 에피층을 이용한 반도체 장치 및 그 제조방법
TW201735131A (zh) 一種形成半導體鰭狀結構的方法
US7091072B2 (en) Semiconductor device and method for manufacturing the same
CN110504169B (zh) 非共形氧化物衬垫及其制造方法
US12009406B2 (en) FinFET device and method
US20090085075A1 (en) Method of fabricating mos transistor and mos transistor fabricated thereby
US20230207396A1 (en) Source/Drain Structures and Method of Forming
TWI527088B (zh) 半導體裝置及製作磊晶層的方法
CN107527815B (zh) 外延层的制作方法
TW202137292A (zh) 半導體裝置的形成方法
KR20210056154A (ko) 액티브 패턴 구조물 및 이를 포함하는 반도체 장치
KR100507377B1 (ko) 반도체 소자의 제조 방법
TWI807706B (zh) 半導體裝置及其製造方法
TWI787817B (zh) 半導體元件的製造方法
TWI847249B (zh) 半導體裝置與其形成方法
TW201834239A (zh) 半導體裝置及其製造方法
TW202201505A (zh) 半導體元件及半導體方法
TW202416360A (zh) 半導體裝置及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20211021

Address after: Ai Erlandubailin

Applicant after: Blue gun Semiconductor Co.,Ltd.

Address before: Hsinchu Science Industrial Park, Hsinchu City, Taiwan, China

Applicant before: UNITED MICROELECTRONICS Corp.

GR01 Patent grant
GR01 Patent grant