CN107492548A - 标准胞元布局及设置多个标准胞元的方法 - Google Patents
标准胞元布局及设置多个标准胞元的方法 Download PDFInfo
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Abstract
本发明涉及标准胞元布局及设置多个标准胞元的方法,提供一种集成电路产品,其包括多个标准胞元,该多个标准胞元的各标准胞元与该多个标准胞元的至少一个其它标准胞元毗连;跨该多个标准胞元连续延展的连续主动区;通过中间扩散间断来分开的至少两个主动区,其中,各标准胞元包含至少一个PMOS装置及至少一个NMOS装置,该至少一个PMOS装置设于该连续主动区中及上面,并且该至少一个NMOS装置设于该至少两个主动区中及上面。
Description
技术领域
本发明关于标准胞元(cell)布局,以及关于设置多个标准胞元的方法,并且更尤指设计具有跨多个标准胞元连续延展的连续主动区、及通过中间扩散间断(intermediatediffusion break)分开的至少两个主动区的标准胞元布局。
背景技术
半导体集成电路(IC)中现有的标准胞元库主要含有以金属氧化物半导体(MOS)环境为基础的逻辑胞元布局,尤其是以互补式金属氧化物半导体(CMOS)环境为基础。大体上,标准胞元库代表标准胞元的集合,其中标准胞元是典型藉助计算机辅助设计(CAD)应用程序来设计的晶体管、或非特定逻辑栅集合的预先设计的布局。标准胞元通常是通过置放与绕线工具按照特定方式来互连或配线,以在特定应用IC(application specific IC;ASIC)中进行特定类型的逻辑操作。
现有的ASIC布局典型为通过配置成数条相邻列(row)的逻辑胞元的阵列(array)来界定。诸如PMOS与NMOS晶体管装置等逻辑胞元的组件通过贯孔与金属层来配线,以便形成进行诸如INVERTER、AND、OR、NAND、NOR、XOR、XNOR、及类似者等布尔(Boolean)与逻辑功能的单纯逻辑(NMOS与PMOS)栅。在互连布局的设计中,必须观察集成电路设计规则,举例如晶体管宽度的最小宽度、金属迹线的最小宽度、及类似者。
在用于设计集成电路的设计程序中,标准胞元库的标准胞元撷取自标准胞元库,并且置放到所欲位置内,后面跟着绕线步骤,用以将所置放的标准胞元彼此连接,并且与半导体芯片上的其它电路连接。将标准胞元置放到半导体芯片上的所欲位置内时,要遵循预定义的设计规则,亦即,界定主动区与胞元边界相隔间距的规则,使得标准胞元一经置放成毗连配置,邻接胞元的主动区便受适当置放,不会招致面积损失。本文中,介于诸邻接标准胞元的诸主动区之间的保留空间、及介于该等主动区与胞元边界之间的保留空间导致标准胞元的面积显著增加。倘若主动区与胞元边界隔开,该等主动区将不会在彼此毗连置放标准胞元时结合,导致具有不同结晶结构或热膨胀系数的不同材料的接口(interface)附近的材料中出现应力相关问题。举例而言,在胞元内,与连至周围绝缘材料的接口接近的主动区的材料(诸如浅沟槽隔离(shallow trench isolation;STI)区)中出现的应力,应变可能在该胞元内生成,该应变影响标准胞元内的NMOS与PMOS装置的效能,对其输出效能造成不理想的变异。现有的标准胞元可包括非主动区,例如STI区,其围绕标准胞元内的主动区。若标准胞元具有超过两阶段,则非主动区通常作用为将诸主动区彼此隔离,并且在区块层级于诸标准胞元之间形成胞元边界。主动区大体上代表上待形成半导体装置的半导体衬底材料的离散岛,这些离散岛是在半导体衬底中通过STI区所界定。
希望提供一种标准胞元布局、及一种设置多个标准胞元的方法,使得晶体管效能在接近扩散边缘处(即介于主动区与非主动区之间的接口)的衰减得以降低(若不得避免的话)。
发明内容
以下介绍本发明的简化概要,以便对本发明的一些态样有基本的了解。本概要并非本发明的详尽概述。用意不在于指认本发明的重要或关键要素,或叙述本发明的范畴。目的仅在于以简化形式介绍一些概念,作为下文更详细说明的引言。
在本发明的第一态样中,提供一种标准胞元布局。根据本文中的一些说明性具体实施例,该标准胞元布局包括多个标准胞元,该多个标准胞元的各标准胞元与该多个标准胞元的至少一个其它标准胞元毗连;跨该多个标准胞元连续延展的连续主动区;通过中间扩散间断来分开的至少两个主动区,其中各标准胞元包含至少一个PMOS装置及至少一个NMOS装置,该至少一个PMOS装置设于该连续主动区中及上面,并且该至少一个NMOS装置设于该至少两个主动区中及上面。
在本发明的第二态样中,提供一种设置多个标准胞元的方法。根据本文中的一些说明性具体实施例,该设置多个标准胞元的方法包括在毗连配置中置放至少两个标准胞元,该至少两个标准胞元各具有至少两个主动区,其中该至少两个标准胞元的各标准胞元具有至少一个PMOS装置及至少一个NMOS装置,其中,该至少两个标准胞元一经置放成毗连配置,便形成跨该至少两个标准胞元连续延展的连续主动区,其中该至少两个毗连标准胞元包含通过中间扩散间断来分开的至少两个主动区,以及其中该至少一个PMOS装置设于该连续主动区中及上面,并且该至少一个NMOS装置设于该至少两个主动区中及上面。
附图说明
本发明可搭配附图参照以下说明来了解,其中相似的参考组件符号表示相似的组件,并且其中:
图1根据本发明的一些说明性具体实施例,在示意性俯视图中示意性绘示标准胞元布局;
图2在示意性俯视图中示意性绘示图1的标准胞元布局更进阶的情况;
图3在示意性俯视图中示意性绘示图1及图2的标准胞元布局再更进阶的情况;以及
图4在示意性俯视图中示意性绘示图1至图3的标准胞元布局再更进阶的情况。
尽管本文所揭示的专利目标易受各种修改和替代形式所影响,其特定具体实施例仍已通过图式中的实施例予以表示并且在本文中予以详述。然而,应了解的是,本文中特定具体实施例的说明用意不在于将本发明限制于所揭示的特定形式,相反地,如随附权利要求书所界定,用意在于涵盖落于本发明的精神及范畴内的所有修改、均等例、及替代方案。
主要组件符号说明
100 标准胞元布局
110、120~126、130~136、140~147 主动区
110a~110e、120a~120e、130a~130e、140a~140e 标准胞元
122b、122c1、122c2 扩散区
150、150a、150b 栅极线
152 间隔或接触
172、173 接触
153、154 间隔
160 切口
174、183 接触结构
176 浮动栅极
178 栅极线
181 浮动栅极。
具体实施方式
下面说明本发明的各项说明性具体实施例。为了澄清,本说明书中并未说明实际实作态样的所有特征。当然,将会领会旳是,在开发任何此实际具体实施例时,必须做出许多实作态样特定决策才能达到开发者的特定目的,例如符合系统有关及业务有关的限制条件,这些限制条件会随实作态样不同而变。此外,将了解的是,此一开发努力可能复杂且耗时,虽然如此,仍会是受益于本发明的所属领域技术人员的例行工作。
本发明现将参照附图作说明。各种结构、系统及装置在图式中只是为了阐释而绘示,为的是不要因所属领域技术人员众所周知的细节而混淆本发明。虽然如此,仍将附图包括进来以说明并阐释本发明的说明性实施例。本文中使用的字组及词组应了解并诠释为与所属领域技术人员了解的字组及词组具有一致的意义。与所属领域技术人员了解的通常或惯用意义不同的词汇或词组(即定义)的特殊定义,用意不在于通过本文词汇或词组的一致性用法提供暗示。就一词汇或词组用意在于具有特殊意义的方面来说,即有别于所属领域技术人员了解的意义,此一特殊定义应会按照为此词汇或词组直接且不含糊地提供此特殊定义的定义方式,在本说明书中明确提出。
在各项态样中,本发明关于一种形成电容器结构的方法,并且关于一种电容器结构,其中该等电容器结构整合于芯片上或中。根据本发明的一些说明性具体实施例,电容器结构可实质代表金属-绝缘体-金属(metal-insulator-metal;MIM)结构。提及MIM结构时,所属领域技术人员将了解的是,虽然使用“MIM结构”这个措辞,用意并非限制于含金属电极材料。
本发明的诸如PMOS与NMOS装置等半导体装置可涉及通过使用先进技术所制作的结构,亦即半导体装置可通过应用于小于100nm技术节点的技术来制作,例如,小于50nm或小于35nm的技术节点,例如:22nm或更小的技术节点。所属领域技术人员将了解的是,根据本发明,可施用小于或等于45nm(例如:22nm或更小的技术节点)的基本规范。所属领域技术人员将了解的是,本发明提出的电容器结构的最小长度尺寸及/或宽度尺寸小于100nm,例如,小于50nm或小于35nm或小于22nm。举例而言,本发明可提供通过使用45nm或更小(例如,22nm或甚至更小)的技术来制作的结构。然而,本文中关于可能技术节点的叙述不应视为构成现揭专利目标的限制。
根据一些说明性具体实施例,半导体装置可在诸如主体衬底(例如:所属技术领域已知的半导体主体材料)或FDSOI衬底的衬底中及上面实施。大体上,FDSOI衬底可具有布置于埋置型绝缘材料层上的薄(主动)半导体层,其进而可形成于衬底材料上。根据本文中的一些说明性具体实施例,半导体层可包含硅、硅锗及类似者其中一者。埋置型绝缘材料层可包含绝缘材料,例如:氧化硅或氮化硅。半导体衬底材料可以是如所属技术领域当作衬底使用的底座材料,例如:硅、硅锗及类似者。所属领域技术人员将了解的是,根据FDSOI衬底,半导体层可具有约20nm或更小的厚度,而埋置型绝缘材料层可具有约145nm的厚度,或根据先进技术,埋置型绝缘材料层可具有范围自10nm至30nm的厚度。举例而言,在本发明的一些说明性具体实施例中,半导体层可具有6nm至10nm的厚度。
虽然半导体装置可通过MOS装置来提供,“MOS”这个措辞仍未暗喻对本文中所揭示专利目标的任何限制,亦即MOS装置未受限于金属氧化物半导体组态,而是亦可包含半导体-氧化物-半导体组态及类似者。
图1示意性绘示包含多个标准胞元110a、110b、110c、110d、110e、120a、120b、120c、120d、120e、130a、130b、130c、130d、130e、140a、140b、140c、140d及140e的标准胞元布局100。可将这多个标准胞元的标准胞元设置成毗连配置,其中多个标准胞元的各标准胞元可毗连多个标准胞元的至少一个其它标准胞元。举例而言,多个标准胞元的标准胞元可设置成毗连的列,各列内的标准胞元与该列的标准胞元中的至少一个其它标准胞元毗连。
请参阅图1,标准胞元110a、110b、110c、110d及110e可设置成使得标准胞元110a可毗连标准胞元110b,其进而可毗连标准胞元110c,其进而可毗连标准胞元110d,其进而可毗连标准胞元110e。
类似的是,标准胞元120a、120b、120c、120d及120e可设置成一列的标准胞元,其中标准胞元120a可毗连标准胞元120b,其进而可毗连标准胞元120c,其进而可毗连标准胞元120d,其进而可毗连标准胞元120e。
类似的是,标准胞元130a、130b、130c、130d及130e可设置成一列,其中标准胞元130a可毗连标准胞元130b,其进而可毗连标准胞元130c,其进而可毗连标准胞元130d,其进而可毗连标准胞元130e。
类似的是,标准胞元140a、140b、140c、140d及140e可设于一列的标准胞元中,其中标准胞元140a可毗连标准胞元140b,其进而可毗连标准胞元140c,其进而可毗连标准胞元140d,其进而可毗连标准胞元140e。
请参阅图1,各个列至少有一些标准胞元可经过设置以形成一行的标准胞元,举例如设置成一行的标准胞元110a、120a及130a。
根据本发明的一些特殊说明性具体实施例,一列内的各标准胞元可具有相等的宽度尺寸,亦即,就各列内的所有标准胞元,沿着图1中的垂直方向所测量的尺寸可相同。相比的下,图1中的水平方向可表示与沿着各列设置的多标准胞元的方向垂直的方向。
根据本发明的一些说明性具体实施例,各个标准胞元110a至140e可代表选自于预定义标准胞元库的合适的标准胞元。虽然可在图1中按照非常示意性的方式来绘示这些标准胞元,尤其是为求清楚而将标准胞元布局的细节省略的方式,所属领域技术人员将了解的是,目的只是为了说明。所属领域技术人员在完整阅读本发明的后将了解的是,标准胞元110a至140e可使用任何现有的集成电路布局来实施,其经组配以诸如AND、OR、XOR、XNOR或NOT等用以提供一些实施例的布尔逻辑功能,或诸如正反器或闩锁器等用以提供一些实施例的储存功能。
根据本发明的一些说明性具体实施例,如图1所示,各标准胞元110a至140e可包含形成于一或多个扩散层内的至于两个主动扩散区。根据本发明的一些特殊说明性具体实施例,主动扩散区可代表设于半导体衬底内的主动扩散区,诸如在FDSOI应用的情况下可设于FDSOI衬底内,或在主体应用的情况下可设于主体衬底内,一经设置,便可形成主动扩散区、一或多个半导体装置,例如:PMOS及/或NMOS装置。根据本发明的一些说明性具体实施例,各标准胞元内所形成的多个主动扩散区其中至少一个主动扩散区可掺有受体(acceptor)类型的杂质原子,诸如硼或铝,用以形成P型金属氧化物半导体(PMOS)装置。替代地或另外,至少一个主动扩散区可掺有施体(donor)类型的杂质原子,诸如磷、砷或锑,用以形成N型金属氧化物半导体(NMOS)装置的主动区。
根据本发明的一些说明性具体实施例,标准胞元可具有至少两个主动扩散区。对于各类型的半导体装置,可提供至少一个主动扩散区。可组配各标准胞元以容纳至少一个PMOS装置及至少一个NMOS装置。
请参照图1,其是参照标准胞元120b所示意性绘示,标准胞元120b包含两个主动扩散区122b及122。可在标准胞元120b内形成主动扩散区122b,致使符合设计规则,诸如连至标准胞元120b的上水平边界或轮廓的间隔152所示。然而,关于标准胞元120b的垂直边界,主动扩散区122b可自一条垂直边界起实质延展至标准胞元120b的对立垂直边界,亦即,主动扩散区122b顺着水平方向跨标准胞元120b完全延展。
关于如图1所示的标准胞元120b的主动扩散区122,根据界定连至标准胞元120b的下边界的间隔152、及界定连至标准胞元120b的垂直边界的间隔153的设计规则,在标准胞元120b内布置主动扩散区122。亦即,可将主动扩散区122完全置放于标准胞元120b内,尤其是,主动扩散区122可不与标准胞元120b的任何边界接触。在下文中,诸如标准胞元120b的主动扩散区122等与标准胞元的边界没有接触的主动扩散区将在下文中称为“主动区”。相比的下,诸如主动扩散区122b等与标准胞元的对置边界有接触的主动扩散区将在下文中称为“连续主动区”。二或更多毗连标准胞元的连续主动区从而形成跨该二或更多毗连标准胞元延展的连续主动区。
请参照图1,标准胞元120c具有根据诸如间隔154等设计规则彼此隔开的两个主动区123及124。再者,标准胞元120c具有通过自一条垂直边界至标准胞元120c的对置垂直边界跨标准胞元120c完全延展的两个毗连主动扩散区122c1及122c2所形成的连续主动区。根据本发明的一些说明性具体实施例,诸如标准胞元120b内的扩散区122b及122等标准胞元的扩散区、或扩散区122c1、122c2、123及124各可具有相等或不同的宽度尺寸(即沿着图1中的垂直方向所测量的尺寸)。图1示意性绘示标准胞元内的主动扩散区可具有不同宽度尺寸的例示性具体实施例。
根据图1的说明,标准胞元布局100可包含毗连配置的多个标准胞元,尤其是,各列标准胞元内的标准胞元呈毗连配置,诸如标准胞元110a、110b、110c、110d及110e,或标准胞元120a、120b、120c、120d及120e,或标准胞元130a、130b、130c、130d及130e,或140a、140b、140c、140d及140e。本文中,标准胞元120a与120b可彼此毗连,使得各标准胞元120a与120b内的连续主动区毗连,提供跨两毗连主动区120a与120b延展的连续主动区。毗连标准胞元120a与120b可更包含如图1中参考组件符号154所示通过中间扩散间断来分开的两个主动区121与122。类似的是,标准胞元120b可与标准胞元120c毗连,使得扩散区122b、122c1及122c2可毗连而形成跨标准胞元120b与120c延展的连续主动区。类似的是,主动区122、123及124通过中间扩散间断(诸如间隔154)来分开。
请参阅图1,标准胞元110a、110b、110c、110d及110e可包含连续主动区110。类似的是,标准胞元120a、120b、120c、120d及120e可包含连续主动区120。类似的是,标准胞元130a、130b、130c、130d及130e可包含主动区130。类似的是,标准胞元140a、140b、140c、140d及140e可包含主动区140。鉴于将一列内的各标准胞元视为提供毗连配置的多个标准胞元,毗连配置的各多个标准胞元可包含连续主动区,例如:连续主动区110、120、130及140,以及在标准胞元120a、120b、120c、120d及120e的情况下可包含至少一个主动区,例如:主动区121、122、123、124、125及126,或在标准胞元130a、130b、130c、130d及130e的情况下可包含主动区131、132、133、134、135及136,或在标准胞元140a、140b、140c、140d及140e的情况下可包含主动区141、142、143、144、145、146及147。
根据包含标准胞元110a至110e的一些说明性具体实施例,连续主动区110可跨标准胞元110a至110e连续延展。在标准胞元120a至120e的情况下,连续主动区120可跨标准胞元120a至120e连续延展。在标准胞元130a至130e的情况下,连续主动区130可跨标准胞元130a至130e连续延展。在标准胞元140a至140e的情况下,连续主动区140可跨标准胞元140a至140e连续延展。
根据本发明的一些说明性具体实施例,连续主动区110至140的至少一者可掺有受体类型的杂质原子,诸如硼或铝。
根据本发明的一些说明性具体实施例,主动区121至147的至少一者可掺有施体类型的杂质原子,诸如磷、砷或锑。
请参阅图2,其根据本发明的一些说明性具体实施例,示意性绘示标准胞元布局。如图2示意性绘示的标准胞元布局100可实质对应于如参照图1所述的标准胞元配置,但复杂度更高。举例而言,图2与图1相异处在于图2的标准胞元布局100较不具有示意性,并且展示多条栅极线150。多条栅极线150中的各栅极线基本上可跨各连续主动区110、120、130及140延展。根据本发明的一些说明性具体实施例,多条栅极线150可包含等间隔相隔或等距相隔的栅极线。然而,这并不对本发明造成任何限制,而且所属领域技术人员将了解的是,栅极线可不均等相隔。
根据本发明的一些说明性具体实施例,多条栅极线150中有一些栅极线可实质布置于至少一些标准胞元的边界上方,如图2中在一些栅极线内以破折线所示。然而,这并不对本发明造成任何限制,而且所属领域技术人员将了解的是,替代地,没有栅极线可布置于标准胞元的边界上方。
根据本发明的一些说明性具体实施例,多条栅极线150的各栅极线可通过一或多个多晶硅及/或栅极金属层所形成。多条栅极线150的各栅极线可更包含用于使多晶硅层及/或栅极金属层与下层主动区及/或连续主动区电绝缘的栅极氧化物。所属领域技术人员将了解的是,图中省略如以上所述栅极线的细节。
请参阅图3,示意性绘示的是图2的标准胞元布局100在通过一或多个切口(cut)将多条栅极线150的栅极线切分的后的情况,如图3中以参考组件符号160所示。因此,跨数列的标准胞元延展的栅极线从而可通过切口160来中断,使得多条栅极线150的各栅极线完全落于一列的标准胞元内。供选择地,落于一列的标准胞元内的栅极线可进一步通过切口160来中断,诸如布置于两个邻接标准胞元120c与120d之间的接口上方的栅极线150a与150b。
请参阅图4,示意性绘示的是图3的标准胞元布局100在更高复杂度的情况,亦即,接触连续主动区110至140的接触(contact)172、连至主动区121至147的接触173、及连至多条栅极线150其中该等栅极线的接触152的层级。
根据本发明的一些说明性具体实施例,如图4所示的标准胞元布局100可包含至少一个浮动栅极,诸如设于连续主动区120上方的浮动栅极176。浮动栅极176可设于两个相邻PMOS装置之间的连续主动区120上方。举例而言,浮动栅极176可布置于标准胞元120c及标准胞元120d的垂直边界上方。根据一些特殊说明性实施例,浮动栅极176可通过接触结构174来电耦合至连续主动区120。接触结构174可包含耦合至贯孔接触的金属线部分,该垂直线部分实质平行于连续主动区120的上表面延展,而该贯孔接触垂直于连续主动区120的上表面。因此,浮动栅极176可电连接至相邻PMOS装置的源极接触与漏极接触其中一者。
根据本发明的一些说明性具体实施例,可不接触实质跨中间扩散间断延展的栅极线,诸如跨介于主动区124与125之间的中间扩散间断延展的栅极线178。
根据本发明的一些说明性具体实施例,浮动栅极181可设于主动区126上方,其中浮动栅极181可沿着介于主动区216与中间扩散间断之间的接口延展,该中间扩散间断介于主动区126与主动区125之间。浮动栅极181可通过接触结构183电连接至主动区126,接触结构183实质类似于接触结构174,例如:包含金属线及贯孔接触。
根据本发明的一些说明性具体实施例,标准胞元110a至140e的至少一者可实施反相器(inverter)。另外或替代地,标准胞元可实施用以提供一些实施例的AND、OR、XOR、XNOR及NOT其中至少一者,或诸如正反器或闩锁器等用以提供一些实施例的储存功能。
根据本发明的一些说明性具体实施例,中间扩散间断可通过绝缘结构所形成,诸如浅沟槽隔离(STI)结构。所属领域技术人员将了解的是,主动区可通过周围STI来界定及/或划定。
根据本发明的一些说明性具体实施例,连续主动区110至140的至少一者可包含硅锗。
根据本发明的一些说明性具体实施例,连续主动区110至140的至少一者可通过至少一个STI与主动区121至147分开。根据本发明的一些说明性具体实施例,两个相邻连续主动区可通过至少一个STI来分开。
根据本发明的一些特殊说明性且非限制性实施例,连续主动区110至140可具有顺着图中垂直方向延展的长度尺寸,其大于约50nm,例如:大于约100nm。
请参照图2至图4,根据本发明的一些说明性具体实施例,在示意性俯视图中提供标准胞元布局。所属领域技术人员将了解的是,示意性俯视图未通过任何栅极结构指出任何主动区的形状的任何切口。
所属领域技术人员将了解的是,倘若邻接晶体管的主动源极及/或漏极区处于不同电位,则处于不同电位的主动源极/漏极区之间需要充分隔离。根据一些说明性实施例,邻接晶体管的此类主动源极/漏极区之间的隔离可通过隔离结构来提供,例如:浅沟槽隔离(STI)结构,或通过另一隔离结构来提供,例如:将处于不同电位的邻接主动源极/漏极区隔离的氧化物结构。
根据本发明的一些说明性具体实施例,可提出连续主动区设计,其中连续主动区设计包含可通过连结栅极(tie gate)来完成的隔离,亦即,连接至处于不同电位的两个邻接区域之间的源极电位(VDD或VSS)的栅极,该等邻接区域形成主动切割屏蔽(mask),或对于不必要地图案化小主动空间有需求。根据一些特殊实施例,紧密栅极可代表连接至邻接源极/漏极区的源极电位与漏极电位其中一者的浮动栅极。
根据本发明的一些说明性具体实施例,因PMOS装置邻近标准胞元设计中的扩散边缘而损失晶体管效能可通过就毗连标准胞元配置中的PMOS装置提供连续主动区来阻止,其中连续主动区跨至少两个毗连标准胞元延展。举例而言,至少可降低因紧密靠近中间扩散间断所造成的PMOS装置的效能衰减。再者,紧密的栅极隔离与漏极/漏极邻域(neighborhood)情况,使得定界特殊构造的良率使用状况降低。再者,紧密的栅极隔离与漏极/漏极邻域情况所造成的漏电可降低,并且可降低漏极/漏极情况中诸胞元边界之间置放填充物的必要性。再者,附加的胞元间绕线资源可通过使用较不紧密的栅极构造来提供。由于PMOS装置在标准胞元布局中有连续主动区,标准胞元边界的PMOS子边缘仅需要胞元间置放限制条件。
以上所揭示的特定具体实施例仅属描述性,正如本发明可用所属领域技术人员所明显知道的不同但均等方式予以修改并且实践而具有本文教示的效益。举例而言,以上所提出的程序步骤可按照不同顺序来进行。再者,如所附的权利要求书中所述除外,未意图限制于本文所示构造或设计的细节。因此,证实可改变或修改以上揭示的特定具体实施例,而且所有此类变体全都视为在本发明的范畴及精神内。要注意的是,本说明书及所附的权利要求书中如“第一”、“第二”、“第三”或“第四”的类用以说明各个程序或结构的术语,仅当作此些步骤/结构节略参考,并且不必然暗喻此些步骤/结构的进行/形成序列。当然,取决于精准声称的措辞,可或可不需要此些程序的排列顺序。因此,本文寻求的保护如所附的权利要求书中所提。
Claims (20)
1.一种集成电路产品,其包含:
多个标准胞元,该多个标准胞元的各标准胞元与该多个标准胞元的至少一个其它标准胞元毗连;
跨该多个标准胞元连续延展的连续主动区;以及
通过中间扩散间断来分开的至少两个主动区,其中,各标准胞元包含至少一个PMOS装置及至少一个NMOS装置,该至少一个PMOS装置设于该连续主动区中及上面,并且该至少一个NMOS装置设于该至少两个主动区中及上面。
2.如权利要求1所述的产品,其中,该连续主动区包含硅锗。
3.如权利要求1所述的产品,其中,该中间扩散间断是沟槽隔离。
4.如权利要求1所述的产品,其中,该连续主动区通过沟槽隔离与该至少两个主动区分开。
5.如权利要求1所述的产品,其中,该多个标准胞元的至少一个标准胞元实施反相器。
6.如权利要求1所述的产品,其中,该连续主动区具有至少约50nm的长度。
7.如权利要求1所述的产品,其更包含设于相邻PMOS装置之间的该连续主动区上方的浮动栅极。
8.如权利要求7所述的产品,其中,该浮动栅极沿着介于两个邻接标准胞元之间的接口延展。
9.如权利要求7所述的产品,其中,该浮动栅极电连接至相邻PMOS装置的源极接触与漏极接触其中一者。
10.如权利要求1所述的产品,其更包含设于该两个主动区其中一者上方的浮动栅极,该浮动栅极沿着介于该两个主动区其中一者与该扩散间断之间的接口延展。
11.一种制作集成电路产品的方法,其包含:
在毗连配置中置放至少两个标准胞元,该至少两个标准胞元各具有至少两个主动区,其中,该至少两个标准胞元的各标准胞元具有至少一个PMOS装置及至少一个NMOS装置;
形成跨该至少两个标准胞元连续延展的连续主动区;以及
在该至少两个毗连标准胞元中形成通过中间扩散间断来分开的至少两个主动区,其中,该至少一个PMOS装置设于该连续主动区中及上面,并且该至少一个NMOS装置设于该至少两个主动区中及上面。
12.如权利要求11所述的方法,其中,该连续主动区包含硅锗。
13.如权利要求11所述的方法,其中,该中间扩散间断包含浅沟槽隔离。
14.如权利要求11所述的方法,其更包含形成将该连续主动区与该至少两个主动区分开的浅沟槽隔离。
15.如权利要求11所述的方法,其中,该至少两个标准胞元的至少一个标准胞元实施反相器。
16.如权利要求11所述的方法,其更包含在相邻PMOS装置之间的该连续主动区上方形成浮动栅极。
17.如权利要求16所述的方法,其中,该浮动栅极沿着介于两个邻接标准胞元之间的接口延展。
18.如权利要求16所述的方法,其中,形成该浮动栅极包含形成跨该连续主动区、及该至少两个主动区其中一者延展的多晶栅极线,以浮动栅极材料堆栈取代该多晶栅极线的一部分,该部分跨该连续主动区延展,以及使该部分与形成该浮动栅极的该剩余的多晶栅极线分开,其中,形成跨该至少两个主动区其中一者延展的多晶栅极。
19.如权利要求11所述的方法,其更包含在该两个主动区其中一者上方形成浮动栅极,该浮动栅极沿着介于该两个主动区其中一者与该扩散间断之间的接口延展。
20.如权利要求19所述的方法,其中,形成该浮动栅极包含形成跨该连续主动区、并沿着介于该两个主动区其中一者与该扩散间断之间的接口延展的多晶栅极线,通过浮动栅极材料堆栈取代该至少两个主动区其中一者上方该多晶栅极线的一部分,以及经由形成该浮动栅极的切口使该部分与该剩余的多晶栅极线分开,其中,形成跨该连续主动区延展的多晶栅极。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110993599A (zh) * | 2018-09-28 | 2020-04-10 | 台湾积体电路制造股份有限公司 | 集成电路及其形成方法和用于设计集成电路的系统 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10297588B2 (en) * | 2016-12-14 | 2019-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and fabrication method of the same |
US9978682B1 (en) * | 2017-04-13 | 2018-05-22 | Qualcomm Incorporated | Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods |
US10572615B2 (en) * | 2017-04-28 | 2020-02-25 | Synopsys, Inc. | Placement and routing of cells using cell-level layout-dependent stress effects |
US10700204B2 (en) * | 2018-08-17 | 2020-06-30 | Qualcomm Incorporated | Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods |
US10892322B2 (en) | 2018-09-21 | 2021-01-12 | Qualcomm Incorporated | Circuits employing a double diffusion break (DDB) and single diffusion break (SDB) in different type diffusion region(s), and related fabrication methods |
US10622479B1 (en) | 2018-09-21 | 2020-04-14 | Qualcomm Incorporated | Circuits employing a double diffusion break (DDB) and single diffusion break (SDB) in different type diffusion region(s), and related fabrication methods |
US11080453B2 (en) | 2018-10-31 | 2021-08-03 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated circuit fin layout method, system, and structure |
US11030381B2 (en) | 2019-01-16 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage analysis on semiconductor device |
KR20210009503A (ko) | 2019-07-17 | 2021-01-27 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US11538757B2 (en) * | 2019-10-29 | 2022-12-27 | Qualcomm Incorporated | Integrated circuit with circuit cells having lower intercell routing metal layers |
US11450659B2 (en) | 2020-03-12 | 2022-09-20 | International Business Machines Corporation | On-chip decoupling capacitor |
DE102021100870B4 (de) | 2020-05-12 | 2024-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Hybridschicht-layout, -verfahren, -system und -struktur |
US11893333B2 (en) | 2020-05-12 | 2024-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid sheet layout, method, system, and structure |
FR3118282B1 (fr) * | 2020-12-17 | 2022-12-30 | St Microelectronics Crolles 2 Sas | Ensemble de cellules precaracterisees integrees |
US11803683B2 (en) * | 2021-01-28 | 2023-10-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of and system for manufacturing semiconductor device |
US12001772B2 (en) * | 2021-09-24 | 2024-06-04 | International Business Machines Corporation | Ultra-short-height standard cell architecture |
KR20240055475A (ko) * | 2022-10-20 | 2024-04-29 | 삼성전자주식회사 | 반도체 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100127333A1 (en) * | 2008-11-21 | 2010-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | novel layout architecture for performance enhancement |
US20140001563A1 (en) * | 2012-07-02 | 2014-01-02 | Globalfoundries Inc. | Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same |
US20150356225A1 (en) * | 2012-12-31 | 2015-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks formed based on integrated circuit layout design having cell that includes extended active region |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8183639B2 (en) * | 2010-10-07 | 2012-05-22 | Freescale Semiconductor, Inc. | Dual port static random access memory cell layout |
US9190405B2 (en) * | 2014-01-31 | 2015-11-17 | Qualcomm Incorporated | Digital circuit design with semi-continuous diffusion standard cell |
-
2016
- 2016-06-09 US US15/177,417 patent/US20170358565A1/en not_active Abandoned
-
2017
- 2017-06-02 TW TW106118260A patent/TW201804347A/zh unknown
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100127333A1 (en) * | 2008-11-21 | 2010-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | novel layout architecture for performance enhancement |
US20140001563A1 (en) * | 2012-07-02 | 2014-01-02 | Globalfoundries Inc. | Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same |
US20150356225A1 (en) * | 2012-12-31 | 2015-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks formed based on integrated circuit layout design having cell that includes extended active region |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110993599A (zh) * | 2018-09-28 | 2020-04-10 | 台湾积体电路制造股份有限公司 | 集成电路及其形成方法和用于设计集成电路的系统 |
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