CN107424937B - A kind of multi-chip integrates packaging method - Google Patents
A kind of multi-chip integrates packaging method Download PDFInfo
- Publication number
- CN107424937B CN107424937B CN201710168631.8A CN201710168631A CN107424937B CN 107424937 B CN107424937 B CN 107424937B CN 201710168631 A CN201710168631 A CN 201710168631A CN 107424937 B CN107424937 B CN 107424937B
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- chip
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- bonding wire
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000007747 plating Methods 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 239000011265 semifinished product Substances 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 15
- 239000000047 product Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 238000000643 oven drying Methods 0.000 claims description 5
- 239000005022 packaging material Substances 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 5
- 238000013461 design Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000007711 solidification Methods 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 239000004744 fabric Substances 0.000 description 4
- 238000011161 development Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention discloses a kind of multi-chips to integrate packaging method, this method comprises: the solidification of chip layout, load, wiring, plastic packaging, plating, Trim Molding, total 7 processing steps of packaging, different function chip can be combined and be packaged in single chip by this method, short time maximum efficiency meets different market user's demands, reduce design link, single chip integration capability is increased, and shortens the production cycle, reduces design cost expense.
Description
Technical field
The present invention relates to a kind of chip package fields more particularly to a kind of multi-chip to integrate packaging method.
Background technique
Currently, market is higher and higher to encapsulating products functional diversities and single chip functional requirement, it is desirable to realize client
Such requirement needs Chevron Research Company (CRC) to redesign former piece, so that single chip has multiple functions, is designed not only to this
It is higher, it is too long from test-manufactr ing time is designed into, and also need to continue to optimize, it is not able to satisfy the duration demand of high speed development variation.Mirror
In disadvantages described above, it is really necessary to design a kind of multi-chip to integrate packaging method.
Summary of the invention
The purpose of the present invention is to provide a kind of multi-chips to integrate packaging method, more functional chips can be carried out integration envelope
Dress, and it is with short production cycle, it is at low cost.
In order to solve the above technical problems, the technical scheme is that a kind of multi-chip integrates packaging method, this method packet
Include following steps:
1) chip layout: function and size are pressed according to muti-piece functional chip, determine chip layout mode, the chip cloth
Setting mode is that horizontal direction is horizontally disposed, vertical direction one of is stacked or multiple combinations；
2) load solidifies: each functional chip is successively carried out load by the chip layout mode selected according to step 1), until
All functional chips are sent into an oven carry out baking-curing after installing, the baking oven drying temperature is 173 DEG C -175 DEG C, when drying
Between be 2.5h；
3) be routed: the functional chip after step 2) load is solidified is placed in bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, uses chopper to carry out reversed cut after planting ball, a reversed section is made into the spot welding top dome face planted and is put down
The reversed section platform is successively interconnected using bonding wire, each functional chip is connected by platform, when two reversed section platforms of connection
Bonding wire length is greater than 2000 microns when less than 3000 microns, and more break structures are arranged at the center of bonding wire；Work as connection
The bonding wire length of two reversed section platforms be greater than 3000 microns and when less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, the bonding wire material is fine copper, and diameter is 20-25 microns；
4) plastic packaging: the functional chip that step 3) completes wiring is placed in mold, is carried out plastic packaging using plastic packaging material and is made
Semi-finished product, and 90s is kept under the conditions of 180 DEG C -182 DEG C, to eliminate semi-finished product internal stress；
5) it is electroplated: semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding: finished product will be cut by predetermined size through the semi-finished product after step 5) plating using cutter；
7) pack: the automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
It can.
The present invention further improves as follows:
Further, bonding heating platform heating temperature is 230 DEG C -235 DEG C in the step 3).
Different function chip can be combined and be packaged in single chip the invention has the advantages that: this method, in short-term
Between maximum efficiency meet different market user's demands, reduce design link, increase single chip integration capability, and shorten
Production cycle reduces design cost expense.
Detailed description of the invention
Fig. 1 shows flow chart of the present invention
Specific embodiment
Embodiment 1
As shown in Figure 1, a kind of multi-chip integrates packaging method, method includes the following steps:
1) chip layout: function and size are pressed according to muti-piece functional chip, determine chip layout mode, the chip cloth
Setting mode is that horizontal direction is horizontally disposed, vertical direction one of is stacked or multiple combinations；
2) load solidifies: each functional chip is successively carried out load by the chip layout mode selected according to step 1), until
All functional chips are sent into an oven carry out baking-curing after installing, the baking oven drying temperature is 175 DEG C, and drying time is
2.5h；
3) be routed: the functional chip after step 2) load is solidified is placed in bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, uses chopper to carry out reversed cut after planting ball, a reversed section is made into the spot welding top dome face planted and is put down
The reversed section platform is successively interconnected using bonding wire, each functional chip is connected by platform, when two reversed section platforms of connection
Bonding wire length is greater than 2000 microns when less than 3000 microns, and more break structures are arranged at the center of bonding wire；Work as connection
The bonding wire length of two reversed section platforms be greater than 3000 microns and when less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, the bonding wire material is fine copper, and diameter is 25 microns；
4) plastic packaging: the functional chip that step 3) completes wiring is placed in mold, is carried out plastic packaging using plastic packaging material and is made
Semi-finished product, and 90s is kept under the conditions of 182 DEG C, to eliminate semi-finished product internal stress；
5) it is electroplated: semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding: finished product will be cut by predetermined size through the semi-finished product after step 5) plating using cutter；
7) pack: the automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
It can.
Bonding heating platform heating temperature is 235 DEG C in step 3) of the present invention.
Embodiment 2
As shown in Figure 1, a kind of multi-chip integrates packaging method, method includes the following steps:
1) chip layout: function and size are pressed according to muti-piece functional chip, determine chip layout mode, the chip cloth
Setting mode is that horizontal direction is horizontally disposed, vertical direction one of is stacked or multiple combinations；
2) load solidifies: each functional chip is successively carried out load by the chip layout mode selected according to step 1), until
All functional chips are sent into an oven carry out baking-curing after installing, the baking oven drying temperature is 173 DEG C, and drying time is
2.5h；
3) be routed: the functional chip after step 2) load is solidified is placed in bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, uses chopper to carry out reversed cut after planting ball, a reversed section is made into the spot welding top dome face planted and is put down
The reversed section platform is successively interconnected using bonding wire, each functional chip is connected by platform, when two reversed section platforms of connection
Bonding wire length is greater than 2000 microns when less than 3000 microns, and more break structures are arranged at the center of bonding wire；Work as connection
The bonding wire length of two reversed section platforms be greater than 3000 microns and when less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, the bonding wire material is fine copper, and diameter is 20 microns；
4) plastic packaging: the functional chip that step 3) completes wiring is placed in mold, is carried out plastic packaging using plastic packaging material and is made
Semi-finished product, and 90s is kept under the conditions of 180 DEG C, to eliminate semi-finished product internal stress；
5) it is electroplated: semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding: finished product will be cut by predetermined size through the semi-finished product after step 5) plating using cutter；
7) pack: the automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
It can.
Bonding heating platform heating temperature is 230 DEG C in step 3) of the present invention.
Embodiment 3
As shown in Figure 1, a kind of multi-chip integrates packaging method, method includes the following steps:
1) chip layout: function and size are pressed according to muti-piece functional chip, determine chip layout mode, the chip cloth
Setting mode is that horizontal direction is horizontally disposed, vertical direction one of is stacked or multiple combinations；
2) load solidifies: each functional chip is successively carried out load by the chip layout mode selected according to step 1), until
All functional chips are sent into an oven carry out baking-curing after installing, the baking oven drying temperature is 174 DEG C, and drying time is
2.5h；
3) be routed: the functional chip after step 2) load is solidified is placed in bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, uses chopper to carry out reversed cut after planting ball, a reversed section is made into the spot welding top dome face planted and is put down
The reversed section platform is successively interconnected using bonding wire, each functional chip is connected by platform, when two reversed section platforms of connection
Bonding wire length is greater than 2000 microns when less than 3000 microns, and more break structures are arranged at the center of bonding wire；Work as connection
The bonding wire length of two reversed section platforms be greater than 3000 microns and when less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, the bonding wire material is fine copper, and diameter is 23 microns；
4) plastic packaging: the functional chip that step 3) completes wiring is placed in mold, is carried out plastic packaging using plastic packaging material and is made
Semi-finished product, and 90s is kept under the conditions of 181 DEG C, to eliminate semi-finished product internal stress；
5) it is electroplated: semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding: finished product will be cut by predetermined size through the semi-finished product after step 5) plating using cutter；
7) pack: the automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
It can.
Bonding heating platform heating temperature is 233 DEG C in step 3) of the present invention.
The present invention is not limited to above-mentioned specific embodiment, those skilled in the art from the above idea,
Without creative labor, the various transformation made are within the scope of the present invention.
Claims (2)
1. a kind of multi-chip integrates packaging method, it is characterised in that method includes the following steps:
1) chip layout: function and size are pressed according to muti-piece functional chip, determine chip layout mode, the chip layout side
Formula is that horizontal direction is horizontally disposed, vertical direction one of is stacked or multiple combinations；
2) load solidifies: each functional chip is successively carried out load by the chip layout mode selected according to step 1), until all
Functional chip is sent into an oven carry out baking-curing after installing, the baking oven drying temperature is 173 DEG C -175 DEG C, and drying time is
2.5h；
3) be routed: the functional chip after step 2) load is solidified is placed in bonding heating platform upper end, carries out to functional chip
Automatic ball-embedding uses chopper to carry out reversed cut, a reversed section platform is made in the spot welding top dome face planted, is made after planting ball
The reversed section platform is successively interconnected with bonding wire, each functional chip is connected, when the bonding for connecting two reversed section platforms
Filament length degree is greater than 2000 microns when less than 3000 microns, and more break structures are arranged at the center of bonding wire；When connection two is anti-
It is greater than 3000 microns when less than 6000 microns to the bonding wire length of section platform, is arranged at the 1/3 of bonding wire, at 2/3
More break structures, for avoiding the line that drifts about and collapse, the bonding wire material is fine copper, and diameter is 20-25 microns；
4) plastic packaging: the functional chip that step 3) completes wiring is placed in mold, using plastic packaging material carry out plastic packaging be made half at
Product, and 90s is kept under the conditions of 180 DEG C -182 DEG C, to eliminate semi-finished product internal stress；
5) it is electroplated: semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding: finished product will be cut by predetermined size through the semi-finished product after step 5) plating using cutter；
7) it packs: being packed automatically after carrying out electrical detection to finished product made from step 6) using automatic test machine.
2. multi-chip as described in claim 1 integrates packaging method, it is characterised in that be bonded heating platform in the step 3)
Heating temperature is 230 DEG C -235 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710168631.8A CN107424937B (en) | 2017-03-21 | 2017-03-21 | A kind of multi-chip integrates packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710168631.8A CN107424937B (en) | 2017-03-21 | 2017-03-21 | A kind of multi-chip integrates packaging method |
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| Publication Number | Publication Date |
|---|---|
| CN107424937A CN107424937A (en) | 2017-12-01 |
| CN107424937B true CN107424937B (en) | 2019-09-24 |
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| CN201710168631.8A Active CN107424937B (en) | 2017-03-21 | 2017-03-21 | A kind of multi-chip integrates packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109087876A (en) * | 2018-09-10 | 2018-12-25 | 无锡豪帮高科股份有限公司 | A kind of SIP integrated antenna package production line merging SMT process |
| CN111816575B (en) * | 2020-06-19 | 2022-01-28 | 浙江亚芯微电子股份有限公司 | Three-chip packaging process |
| CN112362015B (en) * | 2020-06-29 | 2022-06-21 | 泰安晶品新材料科技有限公司 | Method for detecting BGA solder balls for packaging integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074541A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof |
| CN104934405A (en) * | 2015-05-04 | 2015-09-23 | 天水华天科技股份有限公司 | Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010278318A (en) * | 2009-05-29 | 2010-12-09 | Renesas Electronics Corp | Semiconductor device |
| JP6326647B2 (en) * | 2015-02-20 | 2018-05-23 | 大口マテリアル株式会社 | Lead frame for mounting a semiconductor element and manufacturing method thereof |
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2017
- 2017-03-21 CN CN201710168631.8A patent/CN107424937B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074541A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof |
| CN104934405A (en) * | 2015-05-04 | 2015-09-23 | 天水华天科技股份有限公司 | Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part |
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| CN107424937A (en) | 2017-12-01 |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180403 Address after: 247099 Electronic Information Industry Park, Chizhou economic and Technological Development Zone, Chizhou, Anhui Province Applicant after: CHIZHOU HISEMI ELECTRONIC TECHNOLOGY CO.,LTD. Address before: 247100 Anhui city of Chizhou Province Economic and Technological Development Zone Jinan Industrial Park Electronic Information Industrial Park No. 8 standard workshop Applicant before: NATIONT SEMICONDUCTOR Co.,Ltd. |
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| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 247099 Electronic Information Industrial Park 10, Chizhou economic and Technological Development Zone, Anhui Patentee after: Chizhou Huayu Electronic Technology Co.,Ltd. Address before: 247099 Electronic Information Industrial Park 10, Chizhou economic and Technological Development Zone, Anhui Patentee before: CHIZHOU HISEMI ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A kind of multi-chip integrated packaging method Effective date of registration: 20220916 Granted publication date: 20190924 Pledgee: China Co. truction Bank Corp Chizhou branch Pledgor: Chizhou Huayu Electronic Technology Co.,Ltd. Registration number: Y2022980015312 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |