CN107424937A - A kind of multi-chip integrates method for packing - Google Patents
A kind of multi-chip integrates method for packing Download PDFInfo
- Publication number
- CN107424937A CN107424937A CN201710168631.8A CN201710168631A CN107424937A CN 107424937 A CN107424937 A CN 107424937A CN 201710168631 A CN201710168631 A CN 201710168631A CN 107424937 A CN107424937 A CN 107424937A
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- chip
- finished product
- microns
- bonding wire
- functional chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Abstract
The invention discloses a kind of multi-chip to integrate method for packing, and this method includes：Chip layout, load solidification, wiring, plastic packaging, plating, Trim Molding, packaging amount to 7 processing steps, difference in functionality chip can be combined and be packaged in single chip by this method, short time maximum efficiency meets different market user's demands, reduce design link, add single chip integration capability, and shorten the production cycle, reduce design cost expense.
Description
Technical field
The present invention relates to a kind of chip package field, more particularly to a kind of multi-chip to integrate method for packing.
Background technology
At present, market is to encapsulating products functional diversities and single chip functional requirement more and more higher, it is desirable to realizes client
Such requirement is, it is necessary to which Chevron Research Company (CRC) redesigns to former piece so that single chip possesses multiple functions, is designed not only to this
It is higher, it is oversize from test-manufactr ing time is designed into, and also need to continue to optimize, it is impossible to meet the duration demand of high speed development change.Mirror
In disadvantages described above, it is necessary that designing a kind of multi-chip integrates method for packing in fact.
The content of the invention
It is an object of the invention to provide a kind of multi-chip to integrate method for packing, more functional chips can be carried out into integration envelope
Dress, and it is with short production cycle, cost is low.
In order to solve the above technical problems, the technical scheme is that：A kind of multi-chip integrates method for packing, this method bag
Include following steps：
1) chip layout：Function and size are pressed according to polylith functional chip, determine chip layout mode, described chip cloth
Mode is put as horizontal direction is horizontally disposed, one or more combinations in vertical direction stacked arrangement；
2) load solidifies：The chip layout mode selected according to step 1), load is carried out by each functional chip successively, until
All functional chips are sent into baking oven after installing and carry out baking-curing, and the oven for drying temperature is 173 DEG C -175 DEG C, during drying
Between be 2.5H；
3) connect up：Functional chip after step 2) load is solidified is positioned over bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, using chopper reverse cut is carried out after planting ball, a reverse section is made into the spot welding top dome face planted and put down
Platform, the reverse section platform is interconnected successively using bonding wire, each functional chip is turned on, when two reverse section platforms of connection
When bonding wire length is more than 2000 microns and is less than 3000 microns, more break structures are set at the center of bonding wire；Work as connection
When the bonding wire length of two reverse section platforms is more than 3000 microns and is less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, described bonding wire material is fine copper, a diameter of 20-25 microns；
4) plastic packaging：The functional chip that step 3) is completed to wiring is positioned in mould, and carrying out plastic packaging using plastic packaging material is made
Semi-finished product, and 90S is kept under the conditions of 180 DEG C -182 DEG C, to eliminate semi-finished product internal stress；
5) electroplate：Semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding：Finished product will be cut using cutter by given size through the semi-finished product after step 5) plating；
7) pack：The automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
Can.
Further improvement of the invention is as follows：
Further, bonding heating platform heating-up temperature is 230 DEG C -235 DEG C in the step 3).
Beneficial effect of the present invention：Difference in functionality chip can be combined and be packaged in single chip by this method, in short-term
Between maximum efficiency meet different market user's demands, reduce design link, add single chip integration capability, and shorten
Production cycle, reduce design cost expense.
Brief description of the drawings
Fig. 1 shows front view of the present invention
Embodiment
Embodiment 1
As shown in figure 1, a kind of multi-chip integrates method for packing, this method comprises the following steps：
1) chip layout：Function and size are pressed according to polylith functional chip, determine chip layout mode, described chip cloth
Mode is put as horizontal direction is horizontally disposed, one or more combinations in vertical direction stacked arrangement；
2) load solidifies：The chip layout mode selected according to step 1), load is carried out by each functional chip successively, until
All functional chips are sent into baking oven after installing and carry out baking-curing, and the oven for drying temperature is 175 DEG C, and drying time is
2.5H；
3) connect up：Functional chip after step 2) load is solidified is positioned over bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, using chopper reverse cut is carried out after planting ball, a reverse section is made into the spot welding top dome face planted and put down
Platform, the reverse section platform is interconnected successively using bonding wire, each functional chip is turned on, when two reverse section platforms of connection
When bonding wire length is more than 2000 microns and is less than 3000 microns, more break structures are set at the center of bonding wire；Work as connection
When the bonding wire length of two reverse section platforms is more than 3000 microns and is less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, described bonding wire material is fine copper, a diameter of 25 microns；
4) plastic packaging：The functional chip that step 3) is completed to wiring is positioned in mould, and carrying out plastic packaging using plastic packaging material is made
Semi-finished product, and 90S is kept under the conditions of 182 DEG C, to eliminate semi-finished product internal stress；
5) electroplate：Semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding：Finished product will be cut using cutter by given size through the semi-finished product after step 5) plating；
7) pack：The automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
Can.
Bonding heating platform heating-up temperature is 235 DEG C in step 3) of the present invention.
Embodiment 2
As shown in figure 1, a kind of multi-chip integrates method for packing, this method comprises the following steps：
1) chip layout：Function and size are pressed according to polylith functional chip, determine chip layout mode, described chip cloth
Mode is put as horizontal direction is horizontally disposed, one or more combinations in vertical direction stacked arrangement；
2) load solidifies：The chip layout mode selected according to step 1), load is carried out by each functional chip successively, until
All functional chips are sent into baking oven after installing and carry out baking-curing, and the oven for drying temperature is 173 DEG C, and drying time is
2.5H；
3) connect up：Functional chip after step 2) load is solidified is positioned over bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, using chopper reverse cut is carried out after planting ball, a reverse section is made into the spot welding top dome face planted and put down
Platform, the reverse section platform is interconnected successively using bonding wire, each functional chip is turned on, when two reverse section platforms of connection
When bonding wire length is more than 2000 microns and is less than 3000 microns, more break structures are set at the center of bonding wire；Work as connection
When the bonding wire length of two reverse section platforms is more than 3000 microns and is less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, described bonding wire material is fine copper, a diameter of 20 microns；
4) plastic packaging：The functional chip that step 3) is completed to wiring is positioned in mould, and carrying out plastic packaging using plastic packaging material is made
Semi-finished product, and 90S is kept under the conditions of 180 DEG C, to eliminate semi-finished product internal stress；
5) electroplate：Semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding：Finished product will be cut using cutter by given size through the semi-finished product after step 5) plating；
7) pack：The automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
Can.
Bonding heating platform heating-up temperature is 230 DEG C in step 3) of the present invention.
Embodiment 3
As shown in figure 1, a kind of multi-chip integrates method for packing, this method comprises the following steps：
1) chip layout：Function and size are pressed according to polylith functional chip, determine chip layout mode, described chip cloth
Mode is put as horizontal direction is horizontally disposed, one or more combinations in vertical direction stacked arrangement；
2) load solidifies：The chip layout mode selected according to step 1), load is carried out by each functional chip successively, until
All functional chips are sent into baking oven after installing and carry out baking-curing, and the oven for drying temperature is 174 DEG C, and drying time is
2.5H；
3) connect up：Functional chip after step 2) load is solidified is positioned over bonding heating platform upper end, to functional chip
Automatic ball-embedding is carried out, using chopper reverse cut is carried out after planting ball, a reverse section is made into the spot welding top dome face planted and put down
Platform, the reverse section platform is interconnected successively using bonding wire, each functional chip is turned on, when two reverse section platforms of connection
When bonding wire length is more than 2000 microns and is less than 3000 microns, more break structures are set at the center of bonding wire；Work as connection
When the bonding wire length of two reverse section platforms is more than 3000 microns and is less than 6000 microns, at the 1/3 of bonding wire, at 2/3
More break structures are set, and for avoiding the line that drifts about and collapse, described bonding wire material is fine copper, a diameter of 23 microns；
4) plastic packaging：The functional chip that step 3) is completed to wiring is positioned in mould, and carrying out plastic packaging using plastic packaging material is made
Semi-finished product, and 90S is kept under the conditions of 181 DEG C, to eliminate semi-finished product internal stress；
5) electroplate：Semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding：Finished product will be cut using cutter by given size through the semi-finished product after step 5) plating；
7) pack：The automatic packaging of progress is after carrying out electrical detection to finished product made from step 6) using automatic test machine
Can.
Bonding heating platform heating-up temperature is 233 DEG C in step 3) of the present invention.
The present invention is not limited to above-mentioned specific embodiment, one of ordinary skill in the art from above-mentioned design,
Without performing creative labour, a variety of conversion made, it is within the scope of the present invention.
Claims (2)
1. a kind of multi-chip integrates method for packing, it is characterised in that this method comprises the following steps：
1) chip layout：Function and size are pressed according to polylith functional chip, determine chip layout mode, described chip layout side
Formula is that horizontal direction is horizontally disposed, one or more combinations in vertical direction stacked arrangement；
2) load solidifies：The chip layout mode selected according to step 1), load is carried out by each functional chip successively, until all
Functional chip is sent into baking oven after installing and carries out baking-curing, and the oven for drying temperature is 173 DEG C -175 DEG C, and drying time is
2.5H；
3) connect up：Functional chip after step 2) load is solidified is positioned over bonding heating platform upper end, and functional chip is carried out
Automatic ball-embedding, using chopper reverse cut is carried out after planting ball, a reverse section platform is made into the spot welding top dome face planted, made
The reverse section platform is interconnected successively with bonding wire, each functional chip is turned on, when the bonding for connecting two reverse section platforms
When filament length degree is more than 2000 microns and is less than 3000 microns, more break structures are set at the center of bonding wire；When connection two is anti-
When being more than 3000 microns to the bonding wire length of section platform and being less than 6000 microns, set at the 1/3 of bonding wire, at 2/3
More break structures, for avoiding the line that drifts about and collapse, described bonding wire material is fine copper, a diameter of 20-25 microns；
4) plastic packaging：The functional chip that step 3) is completed to wiring is positioned in mould, using plastic packaging material carry out plastic packaging be made half into
Product, and 90S is kept under the conditions of 180 DEG C -182 DEG C, to eliminate semi-finished product internal stress；
5) electroplate：Semi-finished product pin made from step 4) is subjected to Tin plating；
6) Trim Molding：Finished product will be cut using cutter by given size through the semi-finished product after step 5) plating；
7) pack：Packed automatically after carrying out electrical detection to finished product made from step 6) using automatic test machine.
2. multi-chip as claimed in claim 1 integrates method for packing, it is characterised in that bonding heating platform in the step 3)
Heating-up temperature is 230 DEG C -235 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710168631.8A CN107424937B (en) | 2017-03-21 | 2017-03-21 | A kind of multi-chip integrates packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710168631.8A CN107424937B (en) | 2017-03-21 | 2017-03-21 | A kind of multi-chip integrates packaging method |
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| CN107424937A true CN107424937A (en) | 2017-12-01 |
| CN107424937B CN107424937B (en) | 2019-09-24 |
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| CN201710168631.8A Active CN107424937B (en) | 2017-03-21 | 2017-03-21 | A kind of multi-chip integrates packaging method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087876A (en) * | 2018-09-10 | 2018-12-25 | 无锡豪帮高科股份有限公司 | A kind of SIP integrated antenna package production line merging SMT process |
| CN111816575A (en) * | 2020-06-19 | 2020-10-23 | 浙江亚芯微电子股份有限公司 | Three-chip packaging process |
| CN112362015A (en) * | 2020-06-29 | 2021-02-12 | 泰安晶品新材料科技有限公司 | Method for detecting BGA solder balls for packaging integrated circuit |
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| CN102074541A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof |
| US20140193954A1 (en) * | 2009-05-29 | 2014-07-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
| CN104934405A (en) * | 2015-05-04 | 2015-09-23 | 天水华天科技股份有限公司 | Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part |
| JP2016154161A (en) * | 2015-02-20 | 2016-08-25 | Ｓｈマテリアル株式会社 | Lead frame for mounting semiconductor device and manufacturing method thereof |
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2017
- 2017-03-21 CN CN201710168631.8A patent/CN107424937B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140193954A1 (en) * | 2009-05-29 | 2014-07-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
| CN102074541A (en) * | 2010-11-26 | 2011-05-25 | 天水华天科技股份有限公司 | Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof |
| JP2016154161A (en) * | 2015-02-20 | 2016-08-25 | Ｓｈマテリアル株式会社 | Lead frame for mounting semiconductor device and manufacturing method thereof |
| CN104934405A (en) * | 2015-05-04 | 2015-09-23 | 天水华天科技股份有限公司 | Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087876A (en) * | 2018-09-10 | 2018-12-25 | 无锡豪帮高科股份有限公司 | A kind of SIP integrated antenna package production line merging SMT process |
| CN111816575A (en) * | 2020-06-19 | 2020-10-23 | 浙江亚芯微电子股份有限公司 | Three-chip packaging process |
| CN112362015A (en) * | 2020-06-29 | 2021-02-12 | 泰安晶品新材料科技有限公司 | Method for detecting BGA solder balls for packaging integrated circuit |
| CN112362015B (en) * | 2020-06-29 | 2022-06-21 | 泰安晶品新材料科技有限公司 | Method for detecting BGA solder balls for packaging integrated circuit |
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| CN107424937B (en) | 2019-09-24 |
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| PB01 | Publication | ||
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| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180403 Address after: 247099 Electronic Information Industry Park, Chizhou economic and Technological Development Zone, Chizhou, Anhui Province Applicant after: CHIZHOU HISEMI ELECTRONIC TECHNOLOGY CO.,LTD. Address before: 247100 Anhui city of Chizhou Province Economic and Technological Development Zone Jinan Industrial Park Electronic Information Industrial Park No. 8 standard workshop Applicant before: NATIONT SEMICONDUCTOR Co.,Ltd. |
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| GR01 | Patent grant | ||
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| CP01 | Change in the name or title of a patent holder | ||
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Address after: 247099 Electronic Information Industrial Park 10, Chizhou economic and Technological Development Zone, Anhui Patentee after: Chizhou Huayu Electronic Technology Co.,Ltd. Address before: 247099 Electronic Information Industrial Park 10, Chizhou economic and Technological Development Zone, Anhui Patentee before: CHIZHOU HISEMI ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A kind of multi-chip integrated packaging method Effective date of registration: 20220916 Granted publication date: 20190924 Pledgee: China Co. truction Bank Corp Chizhou branch Pledgor: Chizhou Huayu Electronic Technology Co.,Ltd. Registration number: Y2022980015312 |