CN104934405A - Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part - Google Patents

Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part Download PDF

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Publication number
CN104934405A
CN104934405A CN201510220625.3A CN201510220625A CN104934405A CN 104934405 A CN104934405 A CN 104934405A CN 201510220625 A CN201510220625 A CN 201510220625A CN 104934405 A CN104934405 A CN 104934405A
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chip
frame unit
dao
framework
bonding
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CN201510220625.3A
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CN104934405B (en
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牛社强
孙亚丽
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Tianshui Huatian Technology Co Ltd
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Tianshui Huatian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Provided is a lead wire framework based on DIP multiple substrates and a method of using the lead wire framework to manufacture a packaging part. The lead wire framework comprises a framework body with a plurality of rows of first framework unit sets and a plurality of rows of second framework unit sets, and the two kinds of framework unit sets are arranged at intervals. A framework unit is provided with three substrates, wherein two substrates are in connection with four inner pins of the framework unit through a dam bar, and are located between a third substrate and the dam bar; the third substrate is in connection with the frame of the framework body through a tie bar; the inner pin in the framework unit towards an adjacent framework unit and the inner pin of the adjacent framework unit towards the framework unit are interlaced. A wafer is thinned and sawed, and a chip is adhered to the lead wire framework according to requirements to obtain a packing part through processes including pressure welding, post curing, plastic package, etc. The lead wire framework is conductive to increasing product function integration, and improving product packaging yield, quality and reliability; in addition, the lead wire framework can be extended to multi-row matrix type packaging, and is not limited to a DIP packaging form.

Description

Based on the lead frame on DIP Duo Ji island and the method with its manufacturing and encapsulation part
Technical field
The invention belongs to technical field of manufacturing semiconductors, relate to a kind of lead frame, particularly a kind of lead frame based on DIP Duo Ji island; The invention still further relates to a kind of method with this lead frame manufacturing and encapsulation part.
Background technology
For a long time, the encapsulation of DIP series of products manufactures the two row lead frame patterns being mostly single carrier or complex carries, but by the impact of lead frame rolled copper foil manufacturing technology, diel and stamping technology, the restriction of the conditions such as encapsulation aspect is selected coating technology by plastic package die, plating, cut muscle shaping dies technology, the accuracy of identification of upper core/pressure welding device and operation window scope, framework mode is arranged on tradition list/double-basis island two, and not only production efficiency is low, causes larger waste to factory's production capacity, manpower etc.And product design dimensional uniformity is poor, encapsulation rate of finished products is low, causes that production cost is high, efficiency is low.
Through for many years grope development, according to the turn of the market of low cost, high encapsulation count packages demand.The products such as BGA, the MCM higher relative to packaging cost, the multi-chip integration packaging of combination function has become a main trend of encapsulation, thereby produces DIP plane multichip carrier, multi-chip package, and development trend is very rapid.
Current integrated antenna package, in the Ji Dao design of carries chips, the design on the single or Liang Geji island of most employing, this design realizes the number of chips less (1 or 2) of encapsulation, and concerning product cost higher (1 chip or 2 the longer bonding wires of chip demand, more encapsulating resins), simultaneously practical function single (simulation or mixed signal) encapsulation factory.Due to high integration and the miniaturization of integrated circuit development trend, for the encapsulating products of low side DIP series, the multi-chip assembled package not increasing cost just becomes the consumer electronics package requirements of combination function.
Summary of the invention
The object of this invention is to provide a kind of lead frame based on DIP Duo Ji island, the quantity of encapsulate chip in a unit can be increased.
Another object of the present invention is to provide a kind of method manufacturing low cost, multi-chip, multi-functional packaging part with above-mentioned lead frame.
For achieving the above object, the technical solution adopted in the present invention is: a kind of lead frame based on DIP Duo Ji island, comprise frame body, frame body is provided with multiple row first frame unit group and multiple row second frame unit group, first frame unit group and the second frame unit group interval are arranged, and in all first frame unit groups, the quantity of the first frame unit is identical; In all second frame unit groups, the quantity of the second frame unit is identical, the first Ji Dao and the 3rd Ji Dao is provided with on first frame unit, along the orientation of pin, first Ji Dao is connected with four interior pins of the first frame unit by grizzly bar with the 3rd Ji Dao, first frame unit is also provided with the second Ji Dao, first Ji Dao and the 3rd Ji Dao is between grizzly bar and the second base island, and other four interior pins of the first frame unit are disposed adjacent with the second Ji Dao; The 4th Ji Dao and the 6th Ji Dao is arranged with on second frame unit, along the orientation of pin, 4th Ji Dao is connected with four interior pins of the second frame unit by another article of grizzly bar with the 6th Ji Dao, second frame unit is provided with the 5th Ji Dao, 4th Ji Dao and the 6th Ji Dao is between another article of grizzly bar and the 5th base island, and other four interior pins of the second frame unit are disposed adjacent with the 5th Ji Dao; 5th Ji Dao is all connected with the frame of frame body by intercell connector with the second Ji Dao; Be crisscross arranged towards pin in adjacent frame unit and this adjacent frame unit towards pin in this frame unit in a frame unit.
Another technical scheme of the present invention is: a kind of method with above-mentioned lead frame manufacturing and encapsulation part, specifically carries out according to the following steps:
Step 1: thinned wafer, obtains the chip of surface roughness Ra 0.10mm; Chip used thickness 380 μm in thinning rear multi-chip plane packaging part, chip used thickness 200 μm in thinning rear Multichip stacking encapsulation part;
Step 2: adopt DIP to encapsulate general scribing process and scribing is carried out to the chip that thickness is 380 μm;
Adopt DIP to encapsulate general scribing process and scribing is carried out to the chip that the thickness be directly pasted on carrier is 200 μm, during scribing, adopt cooling fin technique; When carrying out scribing to the chip be not directly pasted on carrier, first sticking film film after heating being pasted onto the back side of this chip, then adopting DIP to encapsulate general scribing process and carrying out scribing, during scribing, adopting cooling fin technique;
Step 3: upper core:
For multi-chip plane packaging part:
A first bonding IC chip on the first Ji Dao of first frame unit, then a bonding IC chip on the 4th Ji Dao of second frame unit adjacent with this first frame unit, carry out the bonding of an IC chip on each frame unit of whole piece framework successively, after whole piece framework the one IC chip glues and gets, carry out the bonding of Article 2 framework the one IC chip, until by the gross on framework an IC die bonding complete; Bonding 2nd IC chip on the second Ji Dao, then bonding 2nd IC chip on the 5th Ji Dao again; In each frame unit of whole piece framework, paste the 2nd IC chip successively, after whole piece framework the 2nd IC die bonding, carry out the bonding of Article 2 framework the 2nd IC chip, until the 2nd IC die bonding is complete on whole framework; The bonding 3rd IC chip on the 3rd base island, then the 3rd IC chip is pasted on the 6th Ji Dao of the second frame unit; On each frame unit of whole piece framework, paste the 3rd IC chip successively, whole piece framework carries out the stickup of the 3rd IC chip on Article 2 framework, until the 3rd IC die bonding is complete on whole framework after pasting the 3rd IC chip; Toast after upper core;
For Multichip stacking encapsulation part:
Directly be pasted on the IC chip on Ji Dao, taping process and the IC chip in multi-chip plane packaging part of the 2nd IC chip and the 3rd IC chip, the 2nd IC chip are identical with the taping process of the 3rd IC chip;
Heat an IC chip, it is pasted the 4th IC chip be not directly pasted on carrier, carry out the stickup of the 4th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 4th IC chip attach completes, carry out the stickup of the 4th IC chip on Article 2 framework, until the 4th IC chip attach is complete on whole framework; Then the 2nd IC chip is heated, paste the 5th IC chip thereon, carry out the stickup of the 5th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 5th IC chip attach completes, carry out the stickup of Article 2 framework the 5th IC chip, until the 5th IC chip attach is complete on whole framework; Then, heat the 3rd IC chip, paste the 6th IC chip thereon, carry out the stickup of the 6th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 6th IC chip attach completes, carry out the stickup of Article 2 framework the 6th IC chip, until the 6th IC chip attach is complete on whole framework;
Step 4: pressure welding:
For multi-chip plane packaging part: first make a call to the first bond ball on the pad of an IC chip towards the 2nd IC chip, the pad of 2nd IC chip towards an IC chip makes a call to the second bond ball, then, stacking welding in the first bond ball, welding wire evens up arc in the second bond ball; In like manner weld the bonding line between the 3rd IC chip and an IC chip, the bonding line between welding the 2nd IC chip and the 3rd IC chip; Last from an IC chip, the 2nd IC chip and the inside pin bonding wire of the 3rd IC chip, complete the bonding wire welding of the first frame unit, then carry out the bonding wire welding of the second frame unit, carry out all element solder of whole piece framework successively, until all frame weldings are complete;
For Multichip stacking encapsulation part:
First adopt height arc-welding wire bonding from the 4th IC chip to an IC chip, Hi-Lo lines arc-welding wire bonding is adopted again from the 5th IC chip to the 2nd IC chip, , then square bank sealing wire is used from the 4th IC chip to the 5th IC chip, finally common bonding wire is adopted to weld camber line from the inside pin of an IC chip, common bonding wire is adopted to weld camber line from the inside pin of the 2nd IC chip, a square bank welding is adopted from an IC chip to the 2nd IC chip, connect with the bonding wire that identical order and method are carried out on the first Ji Dao on IC chip and the 3rd Ji Dao between IC chip, connect with the bonding wire that identical order and method are carried out on the second Ji Dao on IC chip and the 3rd Ji Dao between IC chip, complete the bonding wire welding on the first frame unit, then the bonding wire welding on the second frame unit is carried out, carry out the welding of IC chip in all frame units of whole piece framework successively, until all frame weldings are complete,
Step 5: plastic packaging, Post RDBMS, printing;
Step 6: send High-speed Electric plate wire to electroplate, material loading in automatic charging groove, the body periphery scrap rubber material that removes photoresist completes in a system with plating baking, bath temperature 35 ~ 45 DEG C, electroplating current 95 ± 5A/groove, thickness of coating 7.0 ~ 20.32 μm;
Step 7: Trim Molding, automatic feed, enters pipe automatically;
Step 8: check, rejects defective item;
Step 9: adopt the method for testing of same DIP product to test qualified product, choose defective products, non-defective unit is obtained packaging part.
Novel unique, the advantages of simple of lead frame structure of the present invention, has the advantages such as cost is low, energy-saving and emission-reduction, contributes to increasing the integrated of product function, the encapsulation rate of finished products of improving product, quality and reliability.And may extend into the encapsulation of more row's matrix forms, be not limited to DIP packing forms.Be widely used in LED lamp tube, computer interface type, supply power module, network transformer, DIP switch, pressure sensor, conveniently realize the piercing welding of pcb board, range of application comprises the field such as standard logic IC, memory LSI.Manufacture method of the present invention can effective improve production efficiency and product quality, reduces the fail safe that error rate improves processing.And the consumption of single product plastic packaging material reduces greatly, packaging part DIP8L 5 as the inventive method manufacture arranges, every product plastic packaging material consumption 0.433g, and existing packaging part DIP8L 2 arranges every product plastic packaging material consumption 0.75g, adopt lead frame manufacturing and encapsulation part of the present invention to save on packaging cost and be about 42.26%, and under the prerequisite using lead frame of the present invention, select the bonding die glue of domestic brand common material and environment-friendly materials, select the plastic packaging material of domestic common material and environment-friendly materials, bonding line is based on copper cash, gold thread is auxiliary low-cost production scheme and technology.When adopting lead frame of the present invention to produce packaging part, the output of a secondary mould is 2.25 times that existing DIP8L2 arranges packaging part output.
Accompanying drawing explanation
Fig. 1 is the structural representation of the present invention's many base island lead frames frame.
Fig. 2 is the schematic diagram of adjacent first frame unit and the second frame unit in lead frame shown in Fig. 1.
Fig. 3 is the bonding die schematic diagram of multi-chip plane packaging part in packaging part of the present invention.
Fig. 4 is the bonding die schematic diagram of Multichip stacking encapsulation part in packaging part of the present invention.
Fig. 5 is the generalized section of multi-chip plane packaging part in packaging part of the present invention.
Fig. 6 is the generalized section of Multichip stacking encapsulation part in packaging part of the present invention.
In figure: 1. frame body, 2. the first frame unit, 3. the second frame unit, 4. the first Ji Dao, 5. the second Ji Dao, 6. the 3rd Ji Dao, 7. the 4th Ji Dao, 8. the 5th Ji Dao, 9. the 6th Ji Dao, 10. intercell connector, 11. grizzly bars, 12. the one IC chips, 13. the 2nd IC chips, 14. the 3rd IC chips, 15. the 4th IC chips, 16. the 5th IC chips, 17. the 6th IC chips, pin in 18., 19. first bonding lines, 20. plastic-sealed bodies, 21. first bond ball, 22. second bonding lines, 23. second bond ball, 24. outer pins, 25. the 3rd bonding lines, 26. the 4th bonding lines, 27. the 5th bonding lines, A1. the first frame unit 1 pin, A2. the first frame unit 2 pin, A3. the first frame unit 3 pin, A4. the first frame unit 4 pin, A5. the first frame unit 5 pin, A6. the first frame unit 6 pin, A7. the first frame unit 7 pin, A8. the first frame unit 8 pin, B1. the second frame unit 1 pin, B2. the second frame unit 3 pin, B3. the second frame unit 3 pin, B4. the second frame unit 4 pin, B5. the second frame unit 5 pin, B6. the second frame unit 6 pin, B7. the second frame unit 7 pin, B8. the second frame unit 8 pin.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 1, lead frame of the present invention, comprises frame body 1, and frame body 1 is provided with multiple first frame unit 2 and multiple frame unit 3, the first all frame units 2 forms multiple row first frame unit group, and in all first frame unit groups, the quantity of the first frame unit 2 is identical; All second frame units 3 form multiple row second frame unit group, and in all second frame unit groups, the quantity of the second frame unit 3 is identical; Multiple first frame unit group and multiple second frame unit group are arranged at intervals on frame body 1, and all frame units are matrix arrangement.The first frame unit 2 in first frame unit group be arranged in parallel with the second frame unit 3 in the second adjacent frame unit group, and the distance between the second frame unit 3 and frame body 1 frame is less than the distance between the first frame unit 2 and frame body 1 frame, the pin that this first frame unit 2 and this second frame unit 3 are oppositely arranged is crisscross arranged, namely the first frame unit 4 pin A4 is between the second frame unit 5 pin B5 and the second frame unit 6 pin B6, first frame unit 3 pin A3 is between the second frame unit 6 pin B6 and the second frame unit 7 pin B7, first frame unit 2 pin A2 is between the second frame unit 7 pin B7 and the second frame unit 8 pin B8, second frame unit 8 pin B8 is between the first frame unit 2 pin A2 and the first frame unit 1 pin A1, first frame unit 5 pin A5 is between the second frame unit 4 pin B4 and the second frame unit 3 pin B3, first frame unit 6 pin A6 is between the second frame unit 3 pin B3 and the second frame unit 3 pin B2, first frame unit 7 pin A7 is between the second frame unit 3 pin B2 and the second frame unit 1 pin B1, second frame unit 1 pin B1 is between the first frame unit 7 pin A7 and the first frame unit 8 pin A8, as shown in Figure 2, first frame unit 2 is arranged with the first base island 4 and the 3rd base island 6 along the orientation of pin, first base island 4 is all connected with grizzly bar 11 with the 3rd base island 6, one end of grizzly bar 11 and the first frame unit 5 pin A5, one end of first frame unit 6 pin A6, one end of first frame unit 7 pin A7 is connected with one end of the first frame unit 8 pin A8, first frame unit 2 is provided with the second base island 5, first base island 4 and the 3rd base island 6 are positioned at grizzly bar (Dam Bar, also middle muscle is) 11 and second between base island 5, second base island 5 is connected with the frame of frame body 1 by intercell connector (Tie Bar) 10, first frame unit 1 pin A1, first frame unit 2 pin A2, first frame unit 3 pin A3 and the first frame unit 4 pin A4 is all positioned at the side that the second base island 5 deviates from grizzly bar 11.
Second frame unit 3 is arranged with the 4th base island 7 and the 6th base island 9 along the orientation of pin, 4th base island 7 is all connected with another article of grizzly bar 11 with the 6th base island 9, one end of this grizzly bar 11 and the second frame unit 5 pin B5, one end of second frame unit 6 pin B6, one end of second frame unit 7 pin B7 is connected with one end of the second frame unit 8 pin B8, second frame unit 3 is provided with the 5th base island 8, 4th base island 7 and the 6th base island 9 are between another article of grizzly bar 11 and the 5th base island 8, 5th base island 8 is connected by the frame of another article of intercell connector 10 with frame body 1, second frame unit 1 pin B1, second frame unit 3 pin B2, second frame unit 3 pin B3 and the second frame unit 4 pin B4 is all positioned at the side that the 5th base island 8 deviates from another article of grizzly bar 11.
The back side of all Ji Dao is equipped with the pit of matrix form.All Ji Dao be connected with grizzly bar 11 are all processed with at least two apertures of break-through Ji Dao towards one end of grizzly bar 11, at least two apertures on each Ji Dao are arranged along the orientation of frame unit pin.
Frame unit is the distribution in matrix form on frame body 1, wherein line number is that the Ji Dao of the capable adjacent package unit capable with even number line 2n of 2n-1 of odd-numbered line is connected with framework border by intercell connector (Tie Bar), the outer lead pin of the adjacent package unit that 2n-1 is capable and 2n is capable is staggered, be connected with framework border by grizzly bar (Dam Bar is also middle muscle).
Staggered design in pin adjacent in lead frame of the present invention adopts, makes adjacent frame unit be that 13.716mm(is as DIP8L-5P framework in the step pitch of X-direction).And the pin of existing single or double lead frame is the connected design of pin of parallel adjacent frame, adjacent frame unit is that 18.288mm(is as DIP8L-2P framework in the step pitch of X-direction).Visible, in same model lead frame (DIP8L), the step pitch of the present invention 5 row lead frame decreases 4.572mm than the step pitch of existing double lead frame, improves the utilance of frame material.
Every bar lead frame of the present invention there are 5 row unit, often have 18 frame units in row unit, every bar lead frame has 90 frame units.
Lead frame inside of the present invention adopts multichip carrier design (title: special-shaped frame, to be different from traditional structure framework), namely multiple relatively independent Ji Dao is had in a frame unit, the pin that wherein two carriers (the Liang Geji island namely be arranged in parallel) are stretched out with outside is respectively connected, a remaining carrier is connected with the metal edge frame of framework border or indoor design, because product is to voltage request, the spacing >=0.30mm between each independently Ji Dao and adjacent base island; Simultaneously for strengthening product delamination ability, the carrier back side is designed with matrix form pitting; Two Ge compare great Ji islands there is the aperture of break-through, by physics mode, increase potting resin and metallic cohesion.The design feature of DIP many rows framework of the present invention is: frame size, within 255mm × 80mm, adopts adjacent leads staggered design, and every bar 90 ~ 108 unit are not etc.Adopt production equipment configuration optimization scheme, MGP plastic package die, automatically arranging machine and swash of wave road machine, automatically muscle formation system (cutting muscle, shaping, each secondary mould of separation) is cut, high-speed line plating line is electroplated, and this programme does not comprise new equipment (equipment such as original reduction scribing, pressure welding, printing, test still can with).
When producing packaging part with above-mentioned lead frame, by the stickup form of IC chip on carrier, packaging part is divided into multi-chip plane packaging part and Multichip stacking encapsulation part.The invention provides a kind of manufacture method of this packaging part, specifically carry out according to the following steps:
Step 1: wafer is thinning:
8 ~ 12 inch wafer reduced thickness machines of employing, carry out thinning to wafer, the thinning chip surface roughness Ra 0.10mm obtained under the condition of speed of mainshaft 2400rpm ~ 3000rpm; Reduction process is thinning with conventional QFN, corase grind+fine grinding polishing mode; Chip used thickness 380 μm in thinning rear multi-chip plane packaging part, chip used thickness 200 μm in thinning rear Multichip stacking encapsulation part;
Step 2: scribing:
For multi-chip plane packaging part: on 8 ~ 12 inch wafer scribing machines, adopt DIP to encapsulate general scribing process and scribing is carried out to the chip that thickness is 380 μm;
For Multichip stacking encapsulation part: on 8 ~ 12 inch wafer scribing machines, adopt DIP to encapsulate general scribing process and scribing is carried out to the chip that the thickness be directly pasted on carrier is 200 μm, during scribing, adopt cooling fin technique; When carrying out scribing to the chip be not directly pasted on carrier, first sticking film film after heating being pasted onto the back side of this chip, then adopting DIP to encapsulate general scribing process and carrying out scribing, during scribing, adopting cooling fin technique;
Step 3: upper core:
For multi-chip plane packaging part:
First on the first base island 4, put bonding die glue, equipment suction nozzle draws an IC chip 12 from wafer automatically, be placed on the bonding die glue on the first base island 4, complete the bonding of an IC chip 12 on the first frame unit 2, then a bonding IC chip 12 on the 4th base island 7 of the second frame unit 3, carry out the bonding of an IC chip 12 on each frame unit of whole piece framework successively, after whole piece framework the one IC chip 12 glues and gets, carry out the bonding of Article 2 framework the one IC chip 12, until entire block the one IC chip 12 is bonding complete;
Bonding die glue is put on second base island 5 of the first frame unit 2, the 2nd IC chip 13 is bonded on the second base island 5, then bonding 2nd IC chip 13 on the 5th base island 8 of the second frame unit 3 again; In each frame unit of whole piece framework, paste the 2nd IC chip 13 successively, after whole piece framework the 2nd IC chip 13 is bonding, carry out the bonding of Article 2 framework the 2nd IC chip 13, until the 2nd IC chip 13 is bonding complete in entire block;
Bonding die glue is put on 3rd base island 6, equipment suction nozzle automatic sucking the 3rd IC chip 14, be placed on the bonding die glue on the 3rd base island 6; The 3rd IC chip 14 is pasted again on the 6th base island 9 of the second frame unit 3; On each frame unit of whole piece framework, paste the 3rd IC chip 14 successively, whole piece framework carries out the stickup of the 3rd IC chip 14 on Article 2 framework, until the 3rd IC chip 13 is bonding complete in entire block, as shown in Figure 3 after pasting the 3rd IC chip 14;
The complete product of upper core toasts: adopt anti-absciss layer baking process to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h;
The upper core operation of multi-chip plane packaging part adopts AD829A die Bonder and AD828 die Bonder to carry out the stickup of chip usually, shape, the size of suction nozzle and Glue dripping head is selected according to chip form and chip size size, on suction nozzle, the adjustable height of core is 4000 ~ 6500step, thimble lifting height is 100 ~ 160mm, thimble delay rise time is 5 ~ 10ms, point glue height is 1400 ~ 2000step, and bonding die glue thickness is 8 μm ~ 38 μm;
For Multichip stacking encapsulation part:
Directly be pasted on the IC chip 12 on Ji Dao, taping process and the IC chip 12 in multi-chip plane packaging part of the 2nd IC chip 13 and the 3rd IC chip 14, the 2nd IC chip 13 are identical with the taping process of the 3rd IC chip 14;
Adopt the equipment with heating function, heating-up temperature is 150 DEG C, one IC chip 12 is heated, then the not chip be directly pasted on carrier is placed on an IC chip 12, make this chip bonding with an IC chip 12 by the film film not directly being pasted on chip back on carrier, this chip is the 4th IC chip 15, after completing the stickup of the 4th IC chip 15 on the first frame unit 2, carries out the stickup of the 4th IC chip 15 on the second frame unit 3; Carry out the stickup of the 4th IC chip 15 on each frame unit on whole piece framework successively, whole piece framework the 4th IC chip 15 carries out the stickup of the 4th IC chip 15 on Article 2 framework after having pasted, until the 4th IC chip 15 is pasted complete in entire block;
Then, adopt the equipment with heating function, heating-up temperature is 150 DEG C, 2nd IC chip 13 is heated, then be placed on the 2nd IC chip 13 by the not chip be directly pasted on carrier, make this chip bonding with the 2nd IC chip 13 by the film film not directly being pasted on chip back on carrier, this chip is the 5th IC chip 16, after completing the stickup of the 5th IC chip 16 on the first frame unit 2, carry out the stickup of the 5th IC chip 16 on the second frame unit 3; Carry out the stickup of the 5th IC chip 16 on each frame unit on whole piece framework successively, whole piece framework the 5th IC chip 16 carries out the stickup of Article 2 framework the 5th IC chip 16 after having pasted, until the 5th IC chip 16 is pasted complete in entire block;
Then, adopt the equipment with heating function, heating-up temperature is 150 DEG C, 3rd IC chip 14 is heated, then be placed on the 3rd IC chip 14 by the not chip be directly pasted on carrier, make this chip bonding with the 3rd IC chip 14 by the film film not directly being pasted on chip back on carrier, this chip is the 6th IC chip 17, after completing the stickup of the 6th IC chip 17 on the first frame unit 2, carry out the stickup of the 6th IC chip 17 on the second frame unit 3; Carry out the stickup of the 6th IC chip 17 on each frame unit on whole piece framework successively, after whole piece framework the 6th IC chip 17 has been pasted, carry out the stickup of Article 2 framework the 6th IC chip 17, until the 6th IC chip 17 is pasted complete in entire block, as shown in Figure 4;
After upper core completes, anti-absciss layer baking process is adopted to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h;
The upper core operation of Multichip stacking encapsulation part adopts several die Bonder of AD828, AD838, AD898, AD8312 and DB-700AD usually, the shape and size of suction nozzle and Glue dripping head are selected according to chip form and chip size size, on suction nozzle, the adjustable height of core is 4000 ~ 6500step, thimble lifting height is 100 ~ 160mm, thimble delay rise time is 5 ~ 10ms, point glue height is 1400 ~ 2000step, bonding die glue thickness 8 ~ 38 μm, it is 0.5 ~ 1N that bonding die picks up power, and bonding die bonding force is 0.5 ~ 1N.
Step 4: pressure welding:
For multi-chip plane packaging part: first make a call to the first bond ball (gold or copper ball) 21 on the pad of an IC chip 12 towards the 2nd IC chip 13, the pad of 2nd IC chip 13 towards an IC chip 12 is made a call to the second bond ball (gold or copper ball) 23, then, stacking welding in the first bond ball 21, welding wire evens up arc in the second bond ball 23, welding formation second bonding line 22; In like manner weld the bonding line between the 3rd IC chip 14 and an IC chip 12, and the bonding line between welding the 2nd IC chip 13 and the 3rd IC chip 14; Finally weld the first bonding line 19 from the inside pin 18 of an IC chip 12, the 2nd IC chip 13 and the 3rd IC chip 14, complete the bonding wire welding of the first frame unit 2, then the bonding wire welding of the second frame unit 3 is carried out, carry out all element solder of whole piece framework successively, until all frame weldings of entire block are complete;
Adopt and be applicable to spun gold (copper or other bonding wire) technique, substrate heating temperature 200 ~ 220 DEG C, regulate sparking flow 2600 ~ 3100 μ A, regulate be 630 ~ 710 μ s discharge time of striking sparks, gold goal head is melted, to obtain smooth surface and flawless gold goal FAB, time that wiring chopper adds is ultrasonic wave and the pressure of 10 ± 3ms, supersonic frequency 120 ± 10KHZ, and the way of output is electric current, power is 35 ± 7mW about, and Output pressure is 15 ± 5gf about.
For Multichip stacking encapsulation part: adopt and be applicable to spun gold (copper or other bonding wire) low arc technique (camber≤180 μm), use the pellet bonding machine of the shortest bonding wire (1.5 μm), substrate heating temperature 180 ~ 200 DEG C.
First adopt height arc-welding wire bonding from the 4th IC chip 15 to an IC chip 12, form the 3rd bonding line 25, Hi-Lo lines arc-welding wire bonding is adopted to the 2nd IC chip 13 again from the 5th IC chip 16, form the 5th bonding line 27, then use square bank sealing wire from the 4th IC chip 15 to the 5th IC chip 16, form the 4th sealing wire 26; Finally common bonding wire is adopted to weld camber line from the inside pin 18 of an IC chip 12, common bonding wire is adopted to weld camber line from the inside pin 18 of the 2nd IC chip 13, form the first bonding line 19, a square bank welding is adopted from an IC chip 12 to the 2nd IC chip 13, form the second bonding line 22, bonding line 22 direction is by the first chip 12 to the second chip 13; Connect with the bonding wire that identical order and method are carried out on the first base island 4 on IC chip and the 3rd base island 6 between IC chip, connect with the bonding wire that identical order and method are carried out on the second base island 5 on IC chip and the 3rd base island 6 between IC chip.Complete the bonding wire welding on the first frame unit 2, then carry out the bonding wire welding on the second frame unit 3, carry out the welding of IC chip in all frame units of whole piece framework successively, until all frame weldings of entire block are complete;
The ball bonding equipment such as the KS/ESEC/ASM that pressure welding device selects precision higher, optimum configurations is according to bonding wire material and IC chip soldering window construction feature comprehensive selection.
Step 5: plastic packaging:
Adopt the resin meeting green technology requirement of the coefficient of expansion (а 1≤1), water absorption rate (≤0.30%); Use MGP plastic package die, adopt our company's multistage Shooting Technique to carry out plastic packaging, injection pressure 1000 ~ 1800pai, injection time 7 ~ 15s, mold temperature 160 ~ 180 DEG C, clamping pressure 8 ~ 20MPa, encapsulating 120 ~ 150s curing time;
Solidify 5 hours at the temperature of 175 ~ 180 DEG C after encapsulating;
Step 6: print the printing technique that technique is produced with common DIP plastic packaged integrated circuit, adopts laser lettering;
Step 7: adopt high-speed line plating mode: first send High-speed Electric plate wire to electroplate the product after plastic packaging, material loading in automatic charging groove, the body periphery scrap rubber material that removes photoresist completes in a system with plating baking, bath temperature 35 ~ 45 DEG C, electroplating current 95 ± 5A/groove, thickness of coating 7.0 ~ 20.32 μm;
Step 8: adopt automatic Trim Molding system Trim Molding, automatic feed, enters pipe automatically;
Step 9: under high-power microscope (40X-100X), check that plastic-sealed body has flawless, pin with or without distortion, and detects apparent size, rejects defective item;
Step 10: adopt the method for testing of same DIP product to test qualified product, choose defective products, non-defective unit is obtained packaging part.
Adopt the packaging part that moisture proof, antistatic packaging technique packaging is obtained, shipment.
The manufacture method of the multi-chip plane packaging in packaging part of the present invention is the same with the production procedure of existing double DIP plastic packaged integrated circuit, but to add on secondary core in manufacture method of the present invention and repeatedly go up core, and pressure welding bonding pattern is different.
embodiment 1
8 ~ 12 inch wafer reduced thickness machines of employing, carry out thinning to wafer, the thinning chip thickness obtained 380 μm, chip surface roughness Ra 0.10mm under the condition of speed of mainshaft 2400rpm; Reduction process is thinning with conventional QFN, corase grind+fine grinding polishing mode; On 8 ~ 12 inch wafer scribing machines, adopt DIP to encapsulate general scribing process and scribing is carried out to chip; First on the first Ji Dao, put bonding die glue, equipment suction nozzle draws an IC chip from wafer automatically, be placed on the bonding die glue of the first Ji Dao, complete the bonding of an IC chip on the first frame unit, then a bonding IC chip on the 4th Ji Dao of the second frame unit, carry out the bonding of an IC chip on each frame unit of whole piece framework successively, after whole piece framework the one IC chip glues and gets, carry out the bonding of Article 2 framework the one IC chip, until entire block the one IC die bonding is complete; Second Ji Dao of the first frame unit puts bonding die glue, by the 2nd IC die bonding on the second Ji Dao, then bonding 2nd IC chip on the 5th Ji Dao of the second frame unit again; In each frame unit of whole piece framework, paste the 2nd IC chip successively, after whole piece framework the 2nd IC die bonding, carry out the bonding of Article 2 framework the 2nd IC chip, until the 2nd IC die bonding is complete in entire block; 3rd Ji Dao puts bonding die glue, equipment suction nozzle automatic sucking the 3rd IC chip, be placed on the bonding die glue on the 3rd Ji Dao; The 3rd IC chip is pasted again on the 6th Ji Dao of the second frame unit; On each frame unit of whole piece framework, paste the 3rd IC chip successively, whole piece framework carries out the stickup of the 3rd IC chip on Article 2 framework, until the 3rd IC chip is directly complete in entire block after pasting the 3rd IC chip; During upper core, on suction nozzle, the adjustable height of core is 4000step, and thimble lifting height is 100mm, and thimble delay rise time is 5ms, and some glue height is 1400step, and bonding die glue thickness is 8 μm, and bonding die picks up power 0.5N, and bonding die bonding force is 0.5N; Toast after upper core: adopt anti-absciss layer baking process to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h; First on the pad of an IC chip towards the 2nd IC chip, make a call to the first bond ball (gold goal), the pad of 2nd IC chip towards an IC chip makes a call to the second bond ball (gold goal), then, stacking welding in the first bond ball, welding wire evens up arc in the second bond ball, welding formation second bonding line; In like manner weld the bonding line between the 3rd IC chip and an IC chip, and the bonding line between welding the 2nd IC chip and the 3rd IC chip; Finally weld the first bonding line from an IC chip, the 2nd IC chip and the inside pin of the 3rd IC chip, complete the bonding wire welding of the first frame unit, then the bonding wire welding of the second frame unit is carried out, carry out all element solder of whole piece framework successively, until all frame weldings of entire block are complete; The technique being applicable to spun gold is adopted during bonding wire, substrate heating temperature 200 DEG C, regulate sparking flow 2600 μ A, regulate be 630 μ s discharge time of striking sparks, gold goal head is melted, to obtain smooth surface and flawless gold goal FAB, time that wiring chopper adds is ultrasonic wave and the pressure of 10ms, supersonic frequency 120KHZ, and the way of output is electric current, power is about 35mW, and Output pressure is about 15gf.Adopt the resin meeting green technology requirement of coefficient of expansion а 1≤1, water absorption rate≤0.30%; Use MGP plastic package die, adopt multistage Shooting Technique to carry out plastic packaging, injection pressure 1000pai, injection time 7s, mold temperature 160 DEG C, clamping pressure 8MPa, encapsulating 120s curing time; Solidify 5 hours at the temperature of 175 DEG C after encapsulating; With the printing technique that common DIP plastic packaged integrated circuit is produced, laser lettering; Send High-speed Electric plate wire to electroplate the product after plastic packaging, material loading in automatic charging groove, the body periphery scrap rubber material that removes photoresist completes in a system with plating baking, bath temperature 35 DEG C, electroplating current 95A/groove, thickness of coating 7.0 μm; Adopt automatic Trim Molding system Trim Molding, automatic feed, automatically enter pipe; Under high-power microscope, (40X-100X) checks that plastic-sealed body has flawless, and pin with or without distortion, and detects apparent size, rejects defective item; Method of testing with DIP product is tested qualified product, chooses defective products, and non-defective unit is obtained packaging part.
embodiment 2
Wafer is thinning, scribing and upper core to adopt the method for embodiment 1 to carry out, speed of mainshaft when wafer is thinning is 3000rpm, during upper core, on suction nozzle, the adjustable height of core is 6500step, thimble lifting height is 160mm, thimble delay rise time is 10ms, and some glue height is 2000step, and bonding die glue thickness is 38 μm, bonding die picks up power 1N, bonding die bonding force 1N; After upper core completes, anti-absciss layer baking process is adopted to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h; Pressure welding is carried out: adopt and be applicable to copper wire technique by the method for embodiment 1, substrate heating temperature 220 DEG C, regulate sparking flow 3100 μ A, regulate sparking μ s discharge time 710, copper ball head is melted, to obtain smooth surface and flawless gold goal FAB, time that wiring chopper adds is ultrasonic wave and the pressure of 13ms, supersonic frequency 130KHZ, and the way of output is electric current, power is about 42mW, and Output pressure is about 20gf.Injection pressure 1800pai, injection time 15s, mold temperature 180 DEG C, clamping pressure 20MPa, encapsulating 150s curing time during plastic packaging; Solidify 5 hours at the temperature of 180 DEG C after encapsulating; With the printing technique that common DIP plastic packaged integrated circuit is produced, laser lettering; Send High-speed Electric plate wire to electroplate the product after plastic packaging, material loading in automatic charging groove, the body periphery scrap rubber material that removes photoresist completes in a system with plating baking, bath temperature 45 DEG C, electroplating current 100A/groove, thickness of coating 20.32 μm; Then packaging part is obtained by the method for embodiment 1.
embodiment 3
Wafer is thinning, scribing and upper core to adopt the method for embodiment 1 to carry out, speed of mainshaft when wafer is thinning is 2700rpm, during upper core, on suction nozzle, the adjustable height of core is 5250step, thimble lifting height is 130mm, thimble delay rise time is 7.5ms, and some glue height is 1700step, and bonding die glue thickness is 23 μm, bonding die picks up power 0.75N, bonding die bonding force 0.75N; After upper core completes, anti-absciss layer baking process is adopted to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h; Pressure welding is carried out: adopt and be applicable to copper wire technique by the method for embodiment 1, substrate heating temperature 210 DEG C, regulate sparking flow 2850 μ A, regulate sparking μ s discharge time 670, gold goal head is melted, to obtain smooth surface and flawless gold goal FAB, time that wiring chopper adds is ultrasonic wave and the pressure of 7ms, supersonic frequency 110KHZ, and the way of output is electric current, power is about 28mW, and Output pressure is about 10gf.Injection pressure 1400pai, injection time 11s, mold temperature 170 DEG C, clamping pressure 14MPa, encapsulating 135s curing time during plastic packaging; Solidify 5 hours at the temperature of 177.5 DEG C after encapsulating; With the printing technique that common DIP plastic packaged integrated circuit is produced, laser lettering; Send High-speed Electric plate wire to electroplate the product after plastic packaging, material loading in automatic charging groove, the body periphery scrap rubber material that removes photoresist completes in a system with plating baking, bath temperature 40 DEG C, electroplating current 90A/groove, thickness of coating 13.66 μm; Then packaging part is obtained by the method for embodiment 1.
embodiment 4
8 ~ 12 inch wafer reduced thickness machines of employing, carry out thinning to wafer, the thinning chip thickness obtained 200 μm, chip surface roughness Ra 0.10mm under the condition of speed of mainshaft 2400rpm; On 8 ~ 12 inch wafer scribing machines, adopt DIP to encapsulate general scribing process and scribing is carried out to chip, during scribing, adopt cooling fin technique; When carrying out scribing to the chip be not directly pasted on carrier, first sticking film film after heating being pasted onto the back side of this chip, then adopting DIP to encapsulate general scribing process and carrying out scribing, during scribing, adopting cooling fin technique; Directly be pasted on the IC chip on Ji Dao, taping process and the IC chip in embodiment 1 of the 2nd IC chip and the 3rd IC chip, the 2nd IC chip are identical with the taping process of the 3rd IC chip; Adopt the equipment with heating function, heating-up temperature is 150 DEG C, one IC chip is heated, then the not chip be directly pasted on carrier is placed on an IC chip, this chip and an IC die bonding is made by the film film not directly being pasted on chip back on carrier, this chip is the 4th IC chip, after completing the stickup of the 4th IC chip on the first frame unit, carries out the stickup of the 4th IC chip on the second frame unit; Carry out the stickup of the 4th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 4th IC chip attach completes, carry out the stickup of the 4th IC chip on Article 2 framework, until the 4th IC chip attach is complete in entire block; Then, adopt the equipment with heating function, heating-up temperature is 150 DEG C, 2nd IC chip is heated, then be placed on the 2nd IC chip by the not chip be directly pasted on carrier, make this chip and the 2nd IC die bonding by the film film not directly being pasted on chip back on carrier, this chip is the 5th IC chip, after completing the stickup of the 5th IC chip on the first frame unit, carry out the stickup of the 5th IC chip on the second frame unit; Carry out the stickup of the 5th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 5th IC chip attach completes, carry out the stickup of Article 2 framework the 5th IC chip, until the 5th IC chip attach is complete in entire block; Then, adopt the equipment with heating function, heating-up temperature is 150 DEG C, 3rd IC chip is heated, then be placed on the 3rd IC chip by the not chip be directly pasted on carrier, make this chip and the 3rd IC die bonding by the film film not directly being pasted on chip back on carrier, this chip is the 6th IC chip, after completing the stickup of the 6th IC chip on the first frame unit, carry out the stickup of the 6th IC chip on the second frame unit; Carry out the stickup of the 6th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 6th IC chip attach completes, carry out the stickup of Article 2 framework the 6th IC chip, until the 6th IC chip attach is complete in entire block; Parameter during upper core is with embodiment 1; After upper core completes, anti-absciss layer baking process is adopted to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h; Adopt and be applicable to the low arc technique (camber≤180 μm) of spun gold, use the pellet bonding machine of the shortest bonding wire (1.5 μm), substrate heating temperature 180 DEG C.First adopt height arc-welding wire bonding from the 4th IC chip to an IC chip, form the 3rd bonding line, Hi-Lo lines arc-welding wire bonding is adopted again from the 5th IC chip to the 2nd IC chip, form the 5th bonding line, then use square bank sealing wire from the 4th IC chip to the 5th IC chip, form the 4th sealing wire; Finally common bonding wire is adopted to weld camber line from the inside pin of an IC chip, common bonding wire is adopted to weld camber line from the inside pin of the 2nd IC chip, form the first bonding line, a square bank welding is adopted from an IC chip to the 2nd IC chip, form the second bonding line, bonding line direction is by the first chip to the second chip; Connect with the bonding wire that identical order and method are carried out on the first Ji Dao on IC chip and the 3rd Ji Dao between IC chip, connect with the bonding wire that identical order and method are carried out on the second Ji Dao on IC chip and the 3rd Ji Dao between IC chip.Complete the bonding wire welding on the first frame unit, then carry out the bonding wire welding on the second frame unit, carry out the welding of IC chip in all frame units of whole piece framework successively, until all frame weldings of entire block are complete; Then, packaging part is obtained by the method for embodiment 1.
embodiment 5
8 ~ 12 inch wafer reduced thickness machines of employing, carry out thinning to wafer, the thinning chip thickness obtained 200 μm, chip surface roughness Ra 0.10mm under the condition of speed of mainshaft 3000rpm; Then, carry out scribing, upper core and pressure welding by the method for embodiment 4, then, obtain packaging part by the method for embodiment 2.
embodiment 6
8 ~ 12 inch wafer reduced thickness machines of employing, carry out thinning to wafer, the thinning chip thickness obtained 200 μm, chip surface roughness Ra 0.10mm under the condition of speed of mainshaft 2700rpm; Then, carry out scribing, upper core and pressure welding by the method for embodiment 4, then, obtain packaging part by the method for embodiment 3.
Although indicated in conjunction with preferred case study on implementation and described the present invention, those skilled in the art it will be understood that under the spirit and scope of the invention prerequisite not deviating from claims restriction, can modify and convert.

Claims (10)

1. the lead frame based on DIP Duo Ji island, comprise frame body (1), frame body (1) is provided with multiple row first frame unit group and multiple row second frame unit group, first frame unit group and the second frame unit group interval are arranged, and in all first frame unit groups, the quantity of the first frame unit (2) is identical, in all second frame unit groups, the quantity of the second frame unit (3) is identical, it is characterized in that, on first frame unit (2), orientation along pin is provided with the first Ji Dao (4) and the 3rd Ji Dao (6), first Ji Dao (4) is connected with four interior pins of the first frame unit (2) by grizzly bar (11) with the 3rd Ji Dao (6), first frame unit (2) is also provided with the second Ji Dao (5), first Ji Dao (4) and the 3rd Ji Dao (6) is positioned between grizzly bar (11) and the second Ji Dao (5), other four interior pins of the first frame unit (2) are disposed adjacent with the second Ji Dao (5), second frame unit (3) is upper, be arranged with the 4th Ji Dao (7) and the 6th Ji Dao (9) along the orientation of pin, 4th Ji Dao (7) is connected with four interior pins of the second frame unit (3) by another article of grizzly bar (11) with the 6th Ji Dao (9), second frame unit (3) is provided with the 5th Ji Dao (8), 4th Ji Dao (7) and the 6th Ji Dao (9) is positioned between another article of grizzly bar (11) and the 5th Ji Dao (8), and other four interior pins of the second frame unit (3) are disposed adjacent with the 5th Ji Dao (8), 5th Ji Dao (8) and the second Ji Dao (5) are all connected by the frame of intercell connector (10) with frame body (1), be crisscross arranged towards pin in adjacent frame unit and this adjacent frame unit towards pin in this frame unit in a frame unit.
2. the lead frame based on DIP Duo Ji island according to claim 1, it is characterized in that, the first frame unit (2) in described first frame unit group be arranged in parallel with the second frame unit (3) in the second adjacent frame unit group, and the distance between the second frame unit (3) and frame body (1) frame is less than the distance between the first frame unit (2) and frame body (1) frame, the pin that this first frame unit (2) and this second frame unit (3) are oppositely arranged is crisscross arranged.
3. the lead frame based on DIP Duo Ji island according to claim 1 and 2, is characterized in that, adjacent frame unit is 13.716mm in the step pitch of X-direction.
4. the lead frame based on DIP Duo Ji island according to claim 1, is characterized in that, the back side of all Ji Dao is equipped with the pit of matrix form.
5. the lead frame based on DIP Duo Ji island according to claim 1, it is characterized in that, all Ji Dao be connected with grizzly bar (11) are all processed with at least two apertures of this Ji Dao of break-through towards one end of grizzly bar (11), at least two apertures on each Ji Dao are arranged along the orientation of frame unit pin.
6. the lead frame based on DIP Duo Ji island according to claim 1,4 or 5, is characterized in that, the spacing >=0.30mm between adjacent base island.
7., by a method for lead frame manufacturing and encapsulation part described in claim 1, it is characterized in that, the method is specifically carried out according to the following steps:
Step 1: thinned wafer, obtains the chip of surface roughness Ra 0.10mm; Chip used thickness 380 μm in thinning rear multi-chip plane packaging part, chip used thickness 200 μm in thinning rear Multichip stacking encapsulation part;
Step 2: adopt DIP to encapsulate general scribing process and scribing is carried out to the chip that thickness is 380 μm;
Adopt DIP to encapsulate general scribing process and scribing is carried out to the chip that the thickness be directly pasted on carrier is 200 μm, during scribing, adopt cooling fin technique; When carrying out scribing to the chip be not directly pasted on carrier, first sticking film film after heating being pasted onto the back side of this chip, then adopting DIP to encapsulate general scribing process and carrying out scribing, during scribing, adopting cooling fin technique;
Step 3: upper core:
For multi-chip plane packaging part:
A first bonding IC chip on the first Ji Dao of first frame unit, then a bonding IC chip on the 4th Ji Dao of second frame unit adjacent with this first frame unit, carry out the bonding of an IC chip on each frame unit of whole piece framework successively, after whole piece framework the one IC chip glues and gets, carry out the bonding of Article 2 framework the one IC chip, until by the gross on framework an IC die bonding complete; Bonding 2nd IC chip on the second Ji Dao, then bonding 2nd IC chip on the 5th Ji Dao again; In each frame unit of whole piece framework, paste the 2nd IC chip successively, after whole piece framework the 2nd IC die bonding, carry out the bonding of Article 2 framework the 2nd IC chip, until the 2nd IC die bonding is complete on whole framework; The bonding 3rd IC chip on the 3rd base island, then the 3rd IC chip is pasted on the 6th Ji Dao of the second frame unit; On each frame unit of whole piece framework, paste the 3rd IC chip successively, whole piece framework carries out the stickup of the 3rd IC chip on Article 2 framework, until the 3rd IC die bonding is complete on whole framework after pasting the 3rd IC chip; Toast after upper core;
For Multichip stacking encapsulation part:
Directly be pasted on the IC chip on Ji Dao, taping process and the IC chip in multi-chip plane packaging part of the 2nd IC chip and the 3rd IC chip, the 2nd IC chip are identical with the taping process of the 3rd IC chip;
Heat an IC chip, it is pasted the 4th IC chip be not directly pasted on carrier, carry out the stickup of the 4th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 4th IC chip attach completes, carry out the stickup of the 4th IC chip on Article 2 framework, until the 4th IC chip attach is complete on whole framework; Then the 2nd IC chip is heated, paste the 5th IC chip thereon, carry out the stickup of the 5th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 5th IC chip attach completes, carry out the stickup of Article 2 framework the 5th IC chip, until the 5th IC chip attach is complete on whole framework; Then, heat the 3rd IC chip, paste the 6th IC chip thereon, carry out the stickup of the 6th IC chip on each frame unit on whole piece framework successively, after whole piece framework the 6th IC chip attach completes, carry out the stickup of Article 2 framework the 6th IC chip, until the 6th IC chip attach is complete on whole framework;
Step 4: pressure welding:
For multi-chip plane packaging part: first make a call to the first bond ball on the pad of an IC chip towards the 2nd IC chip, the pad of 2nd IC chip towards an IC chip makes a call to the second bond ball, then, stacking welding in the first bond ball, welding wire evens up arc in the second bond ball; In like manner weld the bonding line between the 3rd IC chip and an IC chip, the bonding line between welding the 2nd IC chip and the 3rd IC chip; Last from an IC chip, the 2nd IC chip and the inside pin bonding wire of the 3rd IC chip, complete the bonding wire welding of the first frame unit, then carry out the bonding wire welding of the second frame unit, carry out all element solder of whole piece framework successively, until all frame weldings are complete;
For Multichip stacking encapsulation part:
First adopt height arc-welding wire bonding from the 4th IC chip to an IC chip, Hi-Lo lines arc-welding wire bonding is adopted again from the 5th IC chip to the 2nd IC chip, , then square bank sealing wire is used from the 4th IC chip to the 5th IC chip, finally common bonding wire is adopted to weld camber line from the inside pin of an IC chip, common bonding wire is adopted to weld camber line from the inside pin of the 2nd IC chip, a square bank welding is adopted from an IC chip to the 2nd IC chip, connect with the bonding wire that identical order and method are carried out on the first Ji Dao on IC chip and the 3rd Ji Dao between IC chip, connect with the bonding wire that identical order and method are carried out on the second Ji Dao on IC chip and the 3rd Ji Dao between IC chip, complete the bonding wire welding on the first frame unit, then the bonding wire welding on the second frame unit is carried out, carry out the welding of IC chip in all frame units of whole piece framework successively, until all frame weldings are complete,
Step 5: plastic packaging, Post RDBMS, printing;
Step 6: send High-speed Electric plate wire to electroplate, material loading in automatic charging groove, the body periphery scrap rubber material that removes photoresist completes in a system with plating baking, bath temperature 35 ~ 45 DEG C, electroplating current 95 ± 5A/groove, thickness of coating 7.0 ~ 20.32 μm;
Step 7: Trim Molding, automatic feed, enters pipe automatically;
Step 8: check, rejects defective item;
Step 9: adopt the method for testing of same DIP product to test qualified product, choose defective products, non-defective unit is obtained packaging part.
8. complete product according to claim 7 toasts: adopt anti-absciss layer baking process to toast 3 hours, solidification baking nitrogen flow > 0.8m 2/ h.
9. the method for manufacturing and encapsulation part according to claim 7, it is characterized in that, in described step 3, during upper core: the adjustable height 4000 ~ 6500step of core on suction nozzle, thimble lifting height 100 ~ 160mm, thimble delay rise time 5 ~ 10ms, some glue height 1400 ~ 2000step, bonding die glue thickness 8 μm ~ 38 μm.
10. employing according to claim 7 is applicable to spun gold (copper or other bonding wire) technique, substrate heating temperature 200 ~ 220 DEG C, regulate sparking flow 2600 ~ 3100 μ A, regulate be 630 ~ 710 μ s discharge time of striking sparks, gold goal head is melted, to obtain smooth surface and flawless gold goal FAB, time that wiring chopper adds is ultrasonic wave and the pressure of 10 ± 3ms, supersonic frequency 120 ± 10KHZ, and the way of output is electric current, power is 35 ± 7mW about, and Output pressure is 15 ± 5gf about.
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CN107369626A (en) * 2016-05-12 2017-11-21 无锡华润安盛科技有限公司 A kind of pasting method of multiclass cake core
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CN110299331A (en) * 2019-07-07 2019-10-01 上海晶丰明源半导体股份有限公司 Multichip packaging structure and packaging frame array applied to power supply change-over device
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