CN210607237U - Digital isolation core packaging part - Google Patents
Digital isolation core packaging part Download PDFInfo
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- CN210607237U CN210607237U CN201921776457.6U CN201921776457U CN210607237U CN 210607237 U CN210607237 U CN 210607237U CN 201921776457 U CN201921776457 U CN 201921776457U CN 210607237 U CN210607237 U CN 210607237U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The utility model discloses a core packaging part is kept apart to digit belongs to microelectronics equipment and encapsulation field to the interface layering of the integrated circuit pin, carrier and the plastic envelope material of solving the prior art encapsulation can not reach standard requirement and the low problem of encapsulation yield. A digital isolation core packaging piece comprises packaging units arranged in a matrix form on a lead frame body, wherein each packaging unit comprises a plurality of carriers which are arranged oppositely, and a high-voltage chip and a low-voltage chip are respectively arranged on two opposite adjacent carriers; the height difference between two opposite adjacent carriers is more than 0, and the interval between two opposite adjacent carriers is more than 0. A plurality of radial pin array packaging units are arranged along the outer periphery of the carrier. The periphery of the carrier is provided with n fabrication holes, and the front surface and the back surface of each pin are provided with a plurality of asymmetric V-shaped transverse grooves. The utility model is used for produce high voltage isolation function's digital IC packaging part to reach high breakdown voltage's effect, realize the industrial function of weak current control forceful electric power.
Description
Technical Field
The utility model belongs to microelectronics equipment and encapsulation field, concretely relates to core packaging part is kept apart to digit.
Background
With the industrial 4.0 push and the popularity of smart manufacturing, there is a need for more reliable sensor controller actuators in industrial systems, and these systems all require isolation technology for safe driving. Isolation is a way to transfer data and power between high and low voltage circuits while preventing dangerous direct or uncontrolled transient currents from flowing between the two. Compared with the traditional optocoupler, the digital isolation chip can realize an isolation circuit which is lower in cost, smaller in size, high in isolation withstand voltage, wide in temperature range, high in integration performance, low in power consumption and more reliable, and has high communication rate and long service life. The rapid growth in emerging fields such as electric vehicles and photovoltaic power generation brings more high-performance isolation requirements, which cannot be met by traditional optocouplers. The small-outline IC plastic packaging part suitable for high-voltage isolation creates opportunities, and from the packaging cost perspective, the number of rows of the frame in the domestic market is lower, namely 4 rows, the material utilization rate is low, and the cost is higher. From a reliability point of view, currently only MSL3 is generally available.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a packaging part with digital isolation function to the interface layering of the integrated circuit pin, carrier and the plastic envelope material of solving the prior art encapsulation can not reach the problem that standard requirement and encapsulation yield are low.
The utility model adopts the technical proposal that: a digital isolation core packaging piece comprises packaging units arranged in a matrix form on a lead frame body, wherein each packaging unit comprises a plurality of carriers which are arranged oppositely, and a high-voltage chip and a low-voltage chip are respectively arranged on two opposite adjacent carriers; the height difference between two opposite adjacent carriers is greater than 0, the interval between two opposite adjacent carriers is greater than 0, an isolation space can be provided, and an isolation function is realized. A plurality of radial pin array packaging units are arranged along the outer periphery of the carrier, and are arranged on two long sides of the packaging unit to provide signal and heat dissipation transmission channels. N process holes are arranged on the periphery of the carrier, and the front surface and the back surface of each pin are provided with a plurality of asymmetric V-shaped transverse grooves; at least one end of the carrier other than the opposite periphery is connected with at least one pin. The function of supporting the carrier is realized.
Furthermore, a pair of lugs are symmetrically arranged on two sides of the packaging unit on the central axis of the interval between the two carriers. The balance of the internal structure of the packaging unit is realized, and the packaging strength and the deformation resistance of the packaging unit are increased.
Further, two adjacent carriers are opposed to each otherIs/are as followsThe spacing distance is equal to 0.3-0.8 mm.
Further, the length of the lead frame body is 269 mm-300 mm, and the width of the lead frame body is 83mm-100 mm.
The technical scheme discloses that the voltage is increased to a high-voltage IC by combining different lower-voltage components, the applied voltage is from tens of volts to tens of thousands of volts, the high-voltage resistance (breakdown voltage) is limited by the relative spacing distance between different carriers, the interconnection mode between chips and the selected filling plastic packaging material, and the high-voltage circuit is mainly applied to a mode of transmitting data and electric energy between a high-voltage circuit and a low-voltage circuit and preventing dangerous direct current or uncontrolled transient current from flowing between the high-voltage circuit and the low-voltage circuit.
The utility model discloses compare with base plate (customization) that the encapsulation is with low costs, communication signal between high-pressure chip and low pressure control chip switches on through the bonding wire, and the signal decay reduces. Compared with the traditional optocoupler, the digital isolation chip can realize an isolation circuit which is lower in cost, smaller in size, high in isolation withstand voltage, wide in temperature range, high in integration performance, low in power consumption and more reliable, and has high communication rate and long service life.
The utility model discloses the advantage as follows:
(1) the voltage (breakdown voltage) value is high, the application voltage of the existing product is less than 10 kilovolts, and the packaging piece can reach tens of thousands of volts).
(2) High reliability, long life: the existing reliability can reach MSL3, and the utility model discloses can reach more than the grade of MSL 3.
The plastic package material in the fabrication hole and the plastic package materials on the two sides of the lead frame are integrated, so that the self-locking of the colloid and the metal is realized, the pin layering is prevented, and the reliability of the plastic package part is improved; the plastic packaging material, the pins and the carrier form a bolt type fixing function, and partial path of external moisture entering the plastic packaging body is cut off; the V-shaped groove changes the direction of external moisture entering the plastic package and prolongs the path of the external moisture entering the plastic package. And the method has high efficiency and low cost, can be used for mass production, and is beneficial to the mass application of industrial products and consumer products.
(3) Integrated circuit packages that reach MSL3 or higher have relaxed storage conditions and increased plant life: MSL1 stage: less than or equal to 30 ℃/85% RH infinite plant life; MSL2 stage: less than or equal to 30 ℃/60% RH one year shop life; MSL2a stage: less than or equal to 30 ℃/60% RH four week plant life.
(4) The integration level is increased, and the packaging size and weight of the whole machine/module are reduced.
(5) A frame of prior art once encapsulates 64 integrated circuits, the utility model discloses a frame once encapsulates and accomplishes 112 integrated circuits and above, and encapsulation efficiency improves.
(6) Weight reduction of integrated circuits: through the fabrication holes, the weight of the pins and the carrier is reduced.
(7) The roughened metal lead frame forms countless nanoscale small holes and pits with different depths, increases the surface area of the frame, enhances the bonding force between the metal surface and the plastic package material, and solves the problem of interface layering of the pins, the carrier, the welding wire area and the plastic package material.
The utility model discloses digital isolation chip packaging part adopts novel packaging structure, and its is rational in infrastructure, and BOM easily realizes, compares traditional opto-coupler isolation product and can realize that the cost is lower, the size is littleer, high isolation is withstand voltage, wide temperature range, high integration performance, low consumption and more highly reliable buffer circuit to possess high communication rate long-life.
Drawings
FIG. 1 is a schematic view of the present invention;
figure 2 is a schematic cross-sectional view of the package of the present invention;
fig. 3 is a plan view of the distribution of the bonding wires of the present invention;
FIG. 4 is a schematic diagram of the interconnection line of the chip of the present invention;
FIG. 5 is a schematic diagram of the layout structure of the lead frame of the present invention;
fig. 6 is a schematic structural diagram of the packaging unit in the lead frame according to the present invention.
The reference numerals have the following meanings: 1. the lead frame comprises a lead frame body, 2 parts of a packaging unit, 3 parts of a carrier, 4 parts of pins, 5 parts of a high-voltage chip, 6 parts of a low-voltage chip, 7 parts of a process hole, 8 parts of lugs, 9 parts of V-shaped transverse grooves, 10 parts of opposite edges, 11 parts of welding wires and 12 parts of bonding materials.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
As shown in the figure, the digital isolation core packaging piece comprises a packaging unit 2 which is arranged on a lead frame body 1 in a matrix mode and comprises a plurality of carriers 3 which are arranged oppositely, wherein a high-voltage chip 5 and a low-voltage chip 6 are respectively arranged on two opposite adjacent carriers 3 and are bonded by adopting a bonding material 12; the height difference between two opposite adjacent carriers 3 is greater than 0, the interval between opposite edges 10 of the two opposite adjacent carriers 3 is greater than 0, a plurality of radial pins 4 are arranged along the outer periphery of the carriers 3 on two long edges of the row packaging unit 2, n fabrication holes 7 are arranged on the periphery of the carriers 3, and an asymmetric plurality of V-shaped transverse grooves 9 are arranged on the front side and the back side of each pin 4; at least one end of the carrier 3 other than the opposite periphery is connected to at least one pin 4. A pair of lugs 8 are symmetrically arranged on two sides of the packaging unit 2 on the central axis of the interval between the two carriers 3.
Two adjacent carriers 3 in oppositionIs/are as followsThe spacing distance is equal to 0.3-0.8 mm. The length of the lead frame body 1 is 269 mm-300 mm, and the width is 83mm-100 mm.
The surface of the frame is subjected to ME2 coarsening treatment, the microscopic surface appearance of the frame is changed into a plurality of rugged shapes, and the bonding capability of the frame and the plastic package material is improved.
Example 1
The manufacturing method comprises the steps of manufacturing a wire frame body with the length of 269.6mm and the width of 83.0mm, arranging 112 packaging units on the wire frame body, and arranging all the packaging units in a matrix form with 7 rows and 16 columns. The material utilization rate and the production efficiency are improved.
The packaging unit 2 comprises 2 carriers 3 and realizes multi-chip integrated packaging; the carriers 3 are oppositely arranged, the height difference between the carriers 3 is equal to 0, the spacing distance between the two carriers 3 is equal to 0.8mm, 16 radial pins 4 are arranged along the non-opposite periphery of the carriers 3 to divide two long sides of the packaging unit 2, and a pair of symmetrical lugs (8) are arranged on the spacing central axis of the two carriers 3; the carrier 3 is provided with n process holes 7 around the periphery thereof, which are determined according to the size of the chip. Each pin 4 is provided with a fabrication hole 7 and the front and back surfaces of the pin are provided with a plurality of asymmetric V-shaped transverse grooves 9; at least one end of the carrier 3 other than the opposite periphery is connected to at least one pin 4. The high-voltage chip 5 and the low-voltage chip 6 are connected by a welding wire 11.
The production process comprises the following steps:
a. thinning and scribing the wafer according to the conventional SOP packaging production process;
b. sticking the same or different types of chips onto the lead frame carrier 3 by using a multi-head sticking machine;
c. baking, wherein a fast curing anti-frame oxidation baking process with seven different oxygen-containing areas is adopted during baking, and the detailed flow of the fast curing anti-oxidation baking process comprises the following steps: the seven oxygen content areas are arranged up and down, the frame is transmitted to the first oxidation area after the core is arranged, the frame is transmitted to the second oxidation area after the primary curing of the first oxidation area, and the like in turn until the bonding material of the box product is subjected to sufficient cross-linking reaction, the oxygen content of each curing area adopts a gradual change type quantity difference, and the oxygen content from the first oxygen content area to the seventh oxygen content area is 20000ppm, 18000ppm, 15000ppm, 12000ppm, 6000ppm, 3000ppm and 1500ppm respectively;
d. plasma cleaning is carried out after baking;
e. bonding, wherein the existing SOP packaging production process is adopted for bonding, preferably, the Pre is 170 ℃, the Bond is 180 ℃, and the Post is 100 ℃; the interconnection between chips adopts right-angle arc bonding wires, and the detailed flow is as follows: firstly, performing ball planting on a second welding point, then drawing a wire arc to a proper height from the first welding point welding wire at a right angle by taking the surface of the chip as a reference, then horizontally drawing an arc to a proper length along the direction of the second welding point to be right above a welding ball of the second welding point, and finally vertically downwards bonding the welding ball of the second welding point; the other connecting wires are subjected to pressure welding according to the conventional SOP packaging production process;
plasma cleaning is needed before pressure welding, plasma cleaning after pressure welding is conducted before plastic packaging, and plastic packaging is needed immediately after plasma cleaning after pressure welding is completed. And after pressure welding, plasma cleaning is carried out before plastic packaging, so that silver surface contamination is improved.
f. Plastic packaging: and (3) carrying out plastic package by adopting a high-precision automatic packaging system, wherein the plastic package is selected from the following steps: the plastic package material is EME-G600FB, the injection pressure is 1000Psi, the injection time is 12s, the mold temperature is 175 ℃, the mold closing pressure is 130ton, and the curing time is 120 s;
g. post-curing after plastic packaging is finished, and the post-curing is carried out for 8.5 hours at the temperature of 175 ℃;
h. then, the materials are boiled by heat to soften the flash materials and then are tinned;
i. testing and printing by adopting the whole frame;
j. and (5) performing one-step molding and bar cutting to obtain the digital isolation core plastic SOW packaging piece.
Example 2
The manufacturing method comprises the steps of manufacturing a wire frame body with the length of 269mm and the width of 83mm, arranging 112 packaging units on the wire frame body, and arranging all the packaging units in a 7-row 16-column matrix manner. The packaging unit 2 comprises 2 carriers 3, the carriers 3 are oppositely arranged, the height difference between the carriers 3 is equal to 0.50mm, the spacing distance between the two carriers 3 is equal to 0.8mm, 16 radial pins 4 are arranged along the non-opposite periphery of the carriers 3 to divide two long sides of the packaging unit 2 in rows, and a pair of symmetrical lugs 8 are arranged on the central axis of the spacing distance between the two carriers 3; n fabrication holes 7 are formed in the periphery of the carrier 3, each pin 4 is provided with the fabrication hole 7, and the front surface and the back surface of each pin are provided with a plurality of asymmetric V-shaped transverse grooves 9; at least one end of the carrier 3 other than the opposite periphery is connected to at least one pin 4.
The production process comprises the following steps:
a. thinning and scribing the wafer according to the conventional SOP packaging production process;
b. attaching the chip to the lead frame carrier 3;
c. baking, wherein a fast curing anti-frame oxidation baking process with seven different oxygen-containing areas is adopted during baking, and the detailed flow of the fast curing anti-oxidation baking process comprises the following steps: the seven oxygen content areas are arranged up and down, the frame is transmitted to the first oxidation area after the core is arranged, the frame is transmitted to the second oxidation area after the primary curing of the first oxidation area, and the like in turn until the bonding material of the box product is subjected to sufficient cross-linking reaction, the oxygen content of each curing area adopts a gradual change type quantity difference, and the oxygen content from the first oxygen content area to the seventh oxygen content area is 20000ppm, 18000ppm, 15000ppm, 12000ppm, 6000ppm, 3000ppm and 1500ppm respectively;
d. plasma cleaning is carried out after baking;
e. pressure welding, preferably at the temperature of Pre:170 ℃, Bond:185 ℃ and Post:100 ℃; the interconnection between chips adopts right-angle arc bonding wires, and the detailed flow is as follows: firstly, performing ball planting on a second welding point, then drawing a wire arc to a proper height from the first welding point welding wire at a right angle by taking the surface of the chip as a reference, then horizontally drawing an arc to a proper length along the direction of the second welding point to be right above a welding ball of the second welding point, and finally vertically downwards bonding the welding ball of the second welding point; the other connecting wires are subjected to pressure welding according to the conventional SOP packaging production process; plasma cleaning is carried out before plastic packaging after pressure welding, so that silver surface contamination is improved;
f. plastic packaging: adopting a high-precision automatic packaging system and carrying out plastic packaging, wherein the plastic packaging is carried out by adopting the following steps: the plastic package material is EME, the injection pressure is 800Psi, the injection time is 10s, the mold temperature is 170 ℃, the mold closing pressure is 125ton, and the curing time is 110 s;
g. post-curing after plastic packaging is finished, and the post-curing is carried out for 8.5 hours at the temperature of 175 ℃;
h. then, the materials are boiled by heat to soften the flash materials and then are tinned;
i. testing and printing by adopting the whole frame;
j. and (5) performing one-step molding and bar cutting to obtain the digital isolation core plastic SOW packaging piece.
Example 3
And manufacturing a wire frame body with the length L of 300mm and the width of 100mm, and arranging 112 packaging units on the wire frame body, wherein all the packaging units are arranged in a matrix form of 7 rows and 16 columns. The packaging unit 2 comprises 2 carriers 3, the carriers 3 are oppositely arranged, the height difference between the carriers 3 is equal to 0, the distance between the two carriers 3 is equal to 0.3mm, 16 radial pins 4 are arranged along the non-opposite periphery of the carriers 3 to divide two long sides of the packaging unit 2 in rows, and a pair of symmetrical lugs 8 are arranged on the central axis of the interval between the two carriers 3; n fabrication holes 7 are formed in the periphery of the carrier 3, each pin 4 is provided with the fabrication hole 7, and the front surface and the back surface of each pin are provided with a plurality of asymmetric V-shaped transverse grooves 9; at least one end of the carrier 3 other than the opposite periphery is connected to at least one pin 4.
The production process comprises the following steps:
a. thinning and scribing the wafer according to the conventional SOP packaging production process;
b. attaching the chip to the lead frame carrier 3;
c. baking, wherein a fast curing anti-frame oxidation baking process with seven different oxygen-containing areas is adopted during baking, and the detailed flow of the fast curing anti-oxidation baking process comprises the following steps: the seven oxygen content areas are arranged up and down, the frame is transmitted to the first oxidation area after the core is arranged, the frame is transmitted to the second oxidation area after the primary curing of the first oxidation area, and the like in turn until the bonding material of the box product is subjected to sufficient cross-linking reaction, the oxygen content of each curing area adopts a gradual change type quantity difference, and the oxygen content from the first oxygen content area to the seventh oxygen content area is 20000ppm, 18000ppm, 15000ppm, 12000ppm, 6000ppm, 3000ppm and 1500ppm respectively;
d. plasma cleaning is carried out after baking;
e. pressure welding, preferably at 170 ℃ of Pre, 180 ℃ of Bond and 100 ℃ of Post; the interconnection between chips adopts right-angle arc bonding wires, and the detailed flow is as follows: firstly, performing ball planting on a second welding point, then drawing a wire arc to a proper height from the first welding point welding wire at a right angle by taking the surface of the chip as a reference, then horizontally drawing an arc to a proper length along the direction of the second welding point to be right above a welding ball of the second welding point, and finally vertically downwards bonding the welding ball of the second welding point; the other connecting wires are subjected to pressure welding according to the conventional SOP packaging production process; plasma cleaning is carried out before plastic packaging after pressure welding, so that silver surface contamination is improved;
f. plastic packaging: adopting a high-precision automatic packaging system and carrying out plastic packaging, wherein the plastic packaging is carried out by adopting the following steps: the plastic package material is G600FB, the injection pressure is 1200Psi, the injection time is 14s, the mold temperature is 180 ℃, the mold closing pressure is 135ton, and the curing time is 115 s;
g. post-curing after plastic packaging is finished, and the post-curing is carried out for 8.5 hours at the temperature of 175 ℃;
h. then, the materials are boiled by heat to soften the flash materials and then are tinned;
i. testing and printing by adopting the whole frame;
j. and (5) performing one-step molding and bar cutting to obtain the digital isolation core plastic SOW packaging piece.
Example 2 defines a height difference between the supports 3 equal to 0.50mm, with the aim of: in order to simultaneously stack and package a plurality of chips on a carrier from the vertical direction, the high-voltage breakdown voltage value is improved.
Example 3 the two supports 3 are defined to be spaced apart by a distance equal to 0.3mm, with the aim of: the distance between the two carriers 3 from the horizontal direction is equal to 0.3mm, so that the breakdown withstand voltage value of the carriers reaches a certain safety value.
Claims (4)
1. The utility model provides a core packaging part is kept apart to digit, includes the encapsulation unit that the matrix was arranged on lead frame body (1), its characterized in that: the chip packaging structure comprises a plurality of carriers (3) which are oppositely arranged, wherein a high-voltage chip (5) and a low-voltage chip (6) are respectively arranged on two opposite adjacent carriers (3); the height difference between two opposite adjacent carriers (3) is greater than 0, the interval between two opposite adjacent carriers (3) is greater than 0, and a plurality of radial pins (4) are arranged on two long sides of the packaging unit (2) in rows along the outer periphery of the carriers (3); n process holes (7) are formed in the periphery of the carrier (3), and a plurality of asymmetric V-shaped transverse grooves (9) are formed in the front surface and the back surface of each pin (4); at least one end of the carrier (3) other than the opposite periphery is connected to at least one pin (4).
2. A digital isolator core package according to claim 1, wherein: a pair of lugs (8) are symmetrically arranged on the two sides of the packaging unit (2) on the central axis of the interval between the two carriers (3).
3. A digital isolator core package according to claim 1 or 2, wherein: the distance between two opposite adjacent carriers (3) is equal to 0.3-0.8 mm.
4. A digital isolator core package according to claim 3, wherein: the length of the lead frame body (1) is 269-300 mm, and the width is 83-100 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921776457.6U CN210607237U (en) | 2019-10-22 | 2019-10-22 | Digital isolation core packaging part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921776457.6U CN210607237U (en) | 2019-10-22 | 2019-10-22 | Digital isolation core packaging part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210607237U true CN210607237U (en) | 2020-05-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921776457.6U Active CN210607237U (en) | 2019-10-22 | 2019-10-22 | Digital isolation core packaging part |
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| Country | Link |
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| CN (1) | CN210607237U (en) |
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- 2019-10-22 CN CN201921776457.6U patent/CN210607237U/en active Active
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